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freebsd/sys/arm/at91/at91_spireg.h

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Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
/*-
* Copyright (c) 2006 M. Warner Losh. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
/* $FreeBSD$ */
#ifndef ARM_AT91_AT91_SPIREG_H
#define ARM_AT91_AT91_SPIREG_H
MF p4: Adapt to forthcoming spi framework. The ioctls for SPI commands and such belong in the higher level driver.
2006-07-14 21:35:59 +00:00
#define SPI_CR 0x00 /* CR: Control Register */
#define SPI_CR_SPIEN 0x1
#define SPI_CR_SPIDIS 0x2
#define SPI_CR_SWRST 0x8
#define SPI_MR 0x04 /* MR: Mode Register */
#define SPI_MR_MSTR 0x01
#define SPI_MR_PS 0x02
#define SPI_MR_PCSDEC 0x04
#define SPI_MR_DIV32 0x08
#define SPI_MR_MODFDIS 0x10
#define SPI_MR_LLB 0x80
#define SPI_MR_PSC_CS0 0xe0000
#define SPI_MR_PSC_CS1 0xd0000
#define SPI_MR_PSC_CS2 0xb0000
#define SPI_MR_PSC_CS3 0x70000
#define SPI_RDR 0x08 /* RDR: Receive Data Register */
#define SPI_TDR 0x0c /* TDR: Transmit Data Register */
#define SPI_SR 0x10 /* SR: Status Register */
#define SPI_SR_RDRF 0x00001
#define SPI_SR_TDRE 0x00002
#define SPI_SR_MODF 0x00004
#define SPI_SR_OVRES 0x00008
#define SPI_SR_ENDRX 0x00010
#define SPI_SR_ENDTX 0x00020
#define SPI_SR_RXBUFE 0x00040
#define SPI_SR_TXBUFE 0x00080
#define SPI_SR_SPIENS 0x10000
#define SPI_IER 0x14 /* IER: Interrupt Enable Regsiter */
#define SPI_IDR 0x18 /* IDR: Interrupt Disable Regsiter */
#define SPI_IMR 0x1c /* IMR: Interrupt Mask Regsiter */
#define SPI_CSR0 0x30 /* CS0: Chip Select 0 */
#define SPI_CSR_CPOL 0x01
#define SPI_CSR1 0x34 /* CS1: Chip Select 1 */
#define SPI_CSR2 0x38 /* CS2: Chip Select 2 */
#define SPI_CSR3 0x3c /* CS3: Chip Select 3 */
Import support for the Atmel AT91RM9200 CPU/Microcontroller. This SoC is a ARM920T based CPU with a bunch of built-in peripherals. The inital import supports the SPI bus, the TWI bus (although iicbus integration is not complete), the uarts, the system timer and the onboard ethernet. Support for the Kwikbyte KB9202 (http://www.kwikbyte.com) board is also included, although there's no reason why the 9200 and the 9201 wouldn't also work. Primitive support for running under the skyeye emulator is also provided (although skyeye's support for the AT91RM9200 is a little weak). The code has been structured so that other members of Atmel's arm family can be supported in the future. The AT91SAM9260 is not presently supported due to lack of hardware. The arm7tdmi families are also not supported becasue they lack an MMU. Many thanks to cognet@ for his help and assistance in bringing up this board. He did much of the vm work and wrote parts of the uart and system timer code as well as the bus space implementation. The system boots to single user w/o problem, although the serial console is a little slow and the ethernet driver is still in flux. This work was sponsored by Timing Solutions, Corporation. I am grateful to their support of the FreeBSD project in this manner.
2006-02-04 23:32:13 +00:00
#endif /* ARM_AT91_AT91_SPIREG_H */
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