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Code Issues Releases Activity

Initialization of smp_tlb_wait does not require release semantic, no

Browse Source 
data is synchronized by store/load to the variable.  The
lapic_write_icr() function ensures that store buffers are flushed
before IPI command is issued.

Discussed with:	bde
Tested by:	pho
Sponsored by:	The FreeBSD Foundation
MFC after:	2 weeks
This commit is contained in:
Konstantin Belousov 2015-08-12 09:46:39 +00:00
parent c77d57c8b4
commit 0e190a486f
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=286658
2 changed files with 2 additions and 2 deletions
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2
sys/amd64/amd64/mp_machdep.c
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@ -440,7 +440,7 @@ smp_targeted_tlb_shootdown(cpuset_t mask, u_int vector, pmap_t pmap,
smp_tlb_addr1 = addr1;
smp_tlb_addr2 = addr2;
smp_tlb_pmap = pmap;
atomic_store_rel_int(&smp_tlb_wait, 0);
smp_tlb_wait = 0;
if (CPU_ISFULLSET(&mask)) {
ncpu = othercpus;
ipi_all_but_self(vector);

2
sys/i386/i386/mp_machdep.c
View File

@ -504,7 +504,7 @@ smp_tlb_shootdown(u_int vector, vm_offset_t addr1, vm_offset_t addr2)
mtx_lock_spin(&smp_ipi_mtx);
smp_tlb_addr1 = addr1;
smp_tlb_addr2 = addr2;
atomic_store_rel_int(&smp_tlb_wait, 0);
smp_tlb_wait = 0;
ipi_all_but_self(vector);
while (smp_tlb_wait < ncpu)
ia32_pause();