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arm64: Separate serror handler to EL1H and EL0 versions.

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In order to ensure the registers are saved and restored properly for
the exception level, we need separate handlers serror at each of
EL1H and EL0.

Reviewed by:	andrew
Differential Revision:	https://reviews.freebsd.org/D44630
This commit is contained in:
Stephen J. Kiernan 2024-04-03 19:38:56 -04:00
parent 8268a31bcc
commit 1b60bbfe65
1 changed files with 14 additions and 5 deletions
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19
sys/arm64/arm64/exception.S
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@ -236,6 +236,15 @@ ENTRY(handle_el1h_irq)
ERET
END(handle_el1h_irq)
ENTRY(handle_el1h_serror)
save_registers 1
KMSAN_ENTER
mov x0, sp
1: bl do_serror
b 1b
KMSAN_LEAVE
END(handle_el1h_serror)
ENTRY(handle_el0_sync)
save_registers 0
KMSAN_ENTER
@ -260,14 +269,14 @@ ENTRY(handle_el0_irq)
ERET
END(handle_el0_irq)
ENTRY(handle_serror)
ENTRY(handle_el0_serror)
save_registers 0
KMSAN_ENTER
mov x0, sp
1: bl do_serror
b 1b
KMSAN_LEAVE
END(handle_serror)
END(handle_el0_serror)
ENTRY(handle_empty_exception)
save_registers 0
@ -303,15 +312,15 @@ exception_vectors:
vector el1h_sync 1 /* Synchronous EL1h */
vector el1h_irq 1 /* IRQ EL1h */
vempty 1 /* FIQ EL1h */
vector serror 1 /* Error EL1h */
vector el1h_serror 1 /* Error EL1h */
vector el0_sync 0 /* Synchronous 64-bit EL0 */
vector el0_irq 0 /* IRQ 64-bit EL0 */
vempty 0 /* FIQ 64-bit EL0 */
vector serror 0 /* Error 64-bit EL0 */
vector el0_serror 0 /* Error 64-bit EL0 */
vector el0_sync 0 /* Synchronous 32-bit EL0 */
vector el0_irq 0 /* IRQ 32-bit EL0 */
vempty 0 /* FIQ 32-bit EL0 */
vector serror 0 /* Error 32-bit EL0 */
vector el0_serror 0 /* Error 32-bit EL0 */