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Remove sys/mips/rmi. It's been unmaintained since 2011. This hardware

Browse Source 
is now unobtanium. It's only had API changes in the last 7 years, and
is responsible for a very large number of them. In addition, there's a
lot of code that reimplements base FreeBSD functionality, diminishing
the chances it still works. Without hardware to teset it on, or
prospects of obtaining such hardware and without vendor support, it's
time to move on.

Suggested by: kan@ in mips@ retirement discussion
This commit is contained in:
Warner Losh 2018-01-01 05:13:03 +00:00
parent c3dbef68d5
commit 7167e16b49
Notes: svn2git 2020-12-20 02:59:44 +00:00 
svn path=/head/; revision=327461
46 changed files with 0 additions and 23229 deletions
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147
sys/mips/conf/XLR
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@ -1,147 +0,0 @@
#################################RMI_BSD#####################################
# Copyright (c) 2003-2009 RMI Corporation
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions
# are met:
# 1. Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# 2. Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# 3. Neither the name of RMI Corporation, nor the names of its contributors,
# may be used to endorse or promote products derived from this software
# without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
# ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
# FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
# DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
# OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
# HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
# OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
# SUCH DAMAGE.
#################################RMI_BSD#####################################
# XLR -- Generic kernel configuration file for FreeBSD/mips
#
# For more information on this file, please read the handbook section on
# Kernel Configuration Files:
#
# https://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html
#
# The handbook is also available locally in /usr/share/doc/handbook
# if you've installed the doc distribution, otherwise always see the
# FreeBSD World Wide Web server (https://www.FreeBSD.org/) for the
# latest information.
#
# An exhaustive list of options and more detailed explanations of the
# device lines is also present in the ../../conf/NOTES and NOTES files.
# If you are in doubt as to the purpose or necessity of a line, check first
# in NOTES.
#
# $FreeBSD$
machine mips mips
ident XLR
include "../rmi/std.xlr"
makeoptions MODULES_OVERRIDE=""
makeoptions DEBUG=-g # Build kernel with gdb(1) debug symbols
makeoptions KERNLOADADDR=0x80100000
#profile 2
options SCHED_ULE # ULE scheduler
#options VERBOSE_SYSINIT
#options SCHED_4BSD # 4BSD scheduler
options SMP
options PREEMPTION # Enable kernel thread preemption
#options FULL_PREEMPTION # Enable kernel thread preemption
options INET # InterNETworking
options INET6 # IPv6 communications protocols
options TCP_HHOOK # hhook(9) framework for TCP
options FFS # Berkeley Fast Filesystem
#options SOFTUPDATES # Enable FFS soft updates support
options UFS_ACL # Support for access control lists
options UFS_DIRHASH # Improve performance on big directories
options NFSCL
options NFS_ROOT
#
options BOOTP
options BOOTP_NFSROOT
options BOOTP_NFSV3
options BOOTP_WIRED_TO=nlge0
options BOOTP_COMPAT
options ROOTDEVNAME=\"nfs:10.1.1.8:/usr/extra/nfsroot\"
#
#options MD_ROOT # MD is a potential root device
#options MD_ROOT_SIZE=27000
#options MD_ROOT_SIZE=5120
#options ROOTDEVNAME=\"ufs:md0\"
options _KPOSIX_PRIORITY_SCHEDULING # POSIX P1003_1B real-time extensions
options HZ=1000
options NO_SWAPPING
#Debugging options
options KTRACE # ktrace(1) support
options DDB
options KDB
options GDB
options ALT_BREAK_TO_DEBUGGER
options BREAK_TO_DEBUGGER
#options DEADLKRES #Enable the deadlock resolver
options INVARIANTS #Enable calls of extra sanity checking
options INVARIANT_SUPPORT #Extra sanity checks of internal structures, required by INVARIANTS
#options WITNESS #Enable checks to detect deadlocks and cycles
#options WITNESS_SKIPSPIN #Don't run witness on spinlocks for speed
#options KTR # ktr(4) and ktrdump(8) support
#options KTR_COMPILE=(KTR_LOCK|KTR_PROC|KTR_INTR|KTR_CALLOUT|KTR_UMA|KTR_SYSC)
#options KTR_ENTRIES=131072
#options LOCK_PROFILING
#options SLEEPQUEUE_PROFILING
#options TURNSTILE_PROFILING
device pci
#device ata
device uart
# Pseudo
device loop
device random
device md
device bpf
# Network
device miibus
device nlge
device ether
device re
device msk
device da
device scbus
device ehci # EHCI PCI->USB interface (USB 2.0)
device usb # USB Bus (required)
#options USB_DEBUG # enable debug msgs
#device uhid # "Human Interface Devices"
device umass # Disks/Mass storage - Requires scbus and da
#device cfi
#i2c
device ic
device iic
device iicbb
device iicbus
device ds13rtc # RTC on XLR boards
device max6657 # Temparature sensor on XLR boards
device at24co2n # EEPROM on XLR boards
#crypto
# Not yet
#device cryptodev
#device crypto
#device rmisec

121
sys/mips/conf/XLR64
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@ -1,121 +0,0 @@
# XLR64 -- Kernel configuration file for N64 kernel on XLR/XLS
#
# For more information on this file, please read the handbook section on
# Kernel Configuration Files:
#
# https://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html
#
# The handbook is also available locally in /usr/share/doc/handbook
# if you've installed the doc distribution, otherwise always see the
# FreeBSD World Wide Web server (https://www.FreeBSD.org/) for the
# latest information.
#
# An exhaustive list of options and more detailed explanations of the
# device lines is also present in the ../../conf/NOTES and NOTES files.
# If you are in doubt as to the purpose or necessity of a line, check first
# in NOTES.
#
# $FreeBSD$
machine mips mips64
ident XLR64
include "../rmi/std.xlr"
makeoptions MODULES_OVERRIDE=""
makeoptions DEBUG=-g # Build kernel with gdb(1) debug symbols
makeoptions ARCH_FLAGS="-march=mips64 -mabi=64"
makeoptions KERNLOADADDR=0xffffffff80100000
#profile 2
options SCHED_ULE # ULE scheduler
#options VERBOSE_SYSINIT
#options SCHED_4BSD # 4BSD scheduler
options SMP
#options PREEMPTION # Enable kernel thread preemption
#options FULL_PREEMPTION # Enable kernel thread preemption
options INET # InterNETworking
options INET6 # IPv6 communications protocols
options TCP_HHOOK # hhook(9) framework for TCP
options FFS # Berkeley Fast Filesystem
#options SOFTUPDATES # Enable FFS soft updates support
options UFS_ACL # Support for access control lists
options UFS_DIRHASH # Improve performance on big directories
options NFSCL
options NFS_ROOT
#
options BOOTP
options BOOTP_NFSROOT
options BOOTP_NFSV3
options BOOTP_WIRED_TO=nlge0
options BOOTP_COMPAT
options ROOTDEVNAME=\"nfs:10.1.1.8:/usr/extra/nfsroot\"
#
#options MD_ROOT # MD is a potential root device
#options MD_ROOT_SIZE=27000
#options MD_ROOT_SIZE=5120
#options ROOTDEVNAME=\"ufs:md0\"
options _KPOSIX_PRIORITY_SCHEDULING # POSIX P1003_1B real-time extensions
options HZ=1000
options NO_SWAPPING
#Debugging options
options KTRACE # ktrace(1) support
options DDB
options KDB
options GDB
options ALT_BREAK_TO_DEBUGGER
options BREAK_TO_DEBUGGER
#options DEADLKRES #Enable the deadlock resolver
options INVARIANTS #Enable calls of extra sanity checking
options INVARIANT_SUPPORT #Extra sanity checks of internal structures, required by INVARIANTS
#options WITNESS #Enable checks to detect deadlocks and cycles
#options WITNESS_SKIPSPIN #Don't run witness on spinlocks for speed
#options KTR # ktr(4) and ktrdump(8) support
#options KTR_COMPILE=(KTR_LOCK|KTR_PROC|KTR_INTR|KTR_CALLOUT|KTR_UMA|KTR_SYSC)
#options KTR_ENTRIES=131072
#options LOCK_PROFILING
#options SLEEPQUEUE_PROFILING
#options TURNSTILE_PROFILING
device pci
#device ata
device uart
# Pseudo
device loop
device random
device md
device bpf
# Network
device miibus
device nlge
device ether
device re
device msk
device da
device scbus
device ehci # EHCI PCI->USB interface (USB 2.0)
device usb # USB Bus (required)
options USB_DEBUG # enable debug msgs
#device uhid # "Human Interface Devices"
device umass # Disks/Mass storage - Requires scbus and da
#device cfi
#i2c
device ic
device iic
device iicbb
device iicbus
device ds13rtc # RTC on XLR boards
device max6657 # Temparature sensor on XLR boards
device at24co2n # EEPROM on XLR boards
#crypto
# Not yet
#device cryptodev
#device crypto
#device rmisec

125
sys/mips/conf/XLRN32
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# XLRN32 -- Kernel configuration file for N32 kernel on XLR/XLS
#
# For more information on this file, please read the handbook section on
# Kernel Configuration Files:
#
# https://www.FreeBSD.org/doc/en_US.ISO8859-1/books/handbook/kernelconfig-config.html
#
# The handbook is also available locally in /usr/share/doc/handbook
# if you've installed the doc distribution, otherwise always see the
# FreeBSD World Wide Web server (https://www.FreeBSD.org/) for the
# latest information.
#
# An exhaustive list of options and more detailed explanations of the
# device lines is also present in the ../../conf/NOTES and NOTES files.
# If you are in doubt as to the purpose or necessity of a line, check first
# in NOTES.
#
# $FreeBSD$
machine mips mipsn32
ident XLRN32
include "../rmi/std.xlr"
makeoptions MODULES_OVERRIDE=""
makeoptions DEBUG=-g # Build kernel with gdb(1) debug symbols
makeoptions ARCH_FLAGS="-march=mips64 -mabi=n32"
makeoptions KERNLOADADDR=0x80100000
#profile 2
options SCHED_ULE # ULE scheduler
#options VERBOSE_SYSINIT
#options SCHED_4BSD # 4BSD scheduler
options SMP
options PREEMPTION # Enable kernel thread preemption
#options FULL_PREEMPTION # Enable kernel thread preemption
options INET # InterNETworking
options INET6 # IPv6 communications protocols
options TCP_HHOOK # hhook(9) framework for TCP
options FFS # Berkeley Fast Filesystem
#options SOFTUPDATES # Enable FFS soft updates support
options UFS_ACL # Support for access control lists
options UFS_DIRHASH # Improve performance on big directories
options NFSCL
options NFS_ROOT
#
options BOOTP
options BOOTP_NFSROOT
options BOOTP_NFSV3
options BOOTP_WIRED_TO=nlge0
options BOOTP_COMPAT
options ROOTDEVNAME=\"nfs:10.1.1.8:/usr/extra/nfsroot\"
#
#options MD_ROOT # MD is a potential root device
#options MD_ROOT_SIZE=27000
#options MD_ROOT_SIZE=5120
#options ROOTDEVNAME=\"ufs:md0\"
options _KPOSIX_PRIORITY_SCHEDULING # POSIX P1003_1B real-time extensions
options HZ=1000
options NO_SWAPPING
#Debugging options
options KTRACE # ktrace(1) support
#options DDB
#options KDB
#options GDB
#options ALT_BREAK_TO_DEBUGGER
#options DEADLKRES #Enable the deadlock resolver
options INVARIANTS #Enable calls of extra sanity checking
options INVARIANT_SUPPORT #Extra sanity checks of internal structures, required by INVARIANTS
#options WITNESS #Enable checks to detect deadlocks and cycles
#options WITNESS_SKIPSPIN #Don't run witness on spinlocks for speed
#options KTR # ktr(4) and ktrdump(8) support
#options KTR_COMPILE=(KTR_LOCK|KTR_PROC|KTR_INTR|KTR_CALLOUT|KTR_UMA|KTR_SYSC)
#options KTR_ENTRIES=131072
#options LOCK_PROFILING
#options SLEEPQUEUE_PROFILING
#options TURNSTILE_PROFILING
device pci
#device ata
#options XLR_PERFMON # Enable XLR processor activity monitoring
options BREAK_TO_DEBUGGER
device uart
# Pseudo
device loop
device random
device md
device bpf
# Network
device miibus
device nlge
device ether
device re
device msk
device da
device scbus
#device ohci # OHCI PCI->USB interface
device ehci # EHCI PCI->USB interface (USB 2.0)
device usb # USB Bus (required)
options USB_DEBUG # enable debug msgs
#device udbp # USB Double Bulk Pipe devices
#device ugen # Generic
#device uhid # "Human Interface Devices"
device umass # Disks/Mass storage - Requires scbus and da
#device cfi
#i2c
device ic
device iic
device iicbb
device iicbus
device ds13rtc # RTC on XLR boards
device max6657 # Temparature sensor on XLR boards
device at24co2n # EEPROM on XLR boards
#crypto
# Not yet
#device cryptodev
#device crypto
#device rmisec

14
sys/mips/rmi/Makefile.msgring
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RM = rm
MSGRNG_CFG = msgring.cfg
MSGRNG_CFG_C = $(patsubst %.cfg,%.c,$(MSGRNG_CFG))
#all: msgring.l msgring.y msgring.cfg
all: $(MSGRNG_CFG)
flex -omsgring.lex.c msgring.l
bison -d -omsgring.yacc.c msgring.y
gcc -g3 msgring.lex.c msgring.yacc.c -o msgring
./msgring -i $(MSGRNG_CFG) -o $(MSGRNG_CFG_C)
clean:
$(RM) -f msgring.lex.c msgring.yacc.c msgring.yacc.h msgring msgring.o*

595
sys/mips/rmi/board.c
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@ -1,595 +0,0 @@
/*********************************************************************
* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
*
*
* Copyright 2003-2006 Raza Microelectronics, Inc. (RMI). All rights
* reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY Raza Microelectronics, Inc. ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RMI OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES, LOSS OF USE, DATA, OR PROFITS, OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*
* *****************************RMI_2**********************************/
#include <sys/cdefs.h> /* RCS ID & Copyright macro defns */
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/kernel.h>
#include <sys/lock.h>
#include <sys/mutex.h>
#include <machine/cpufunc.h>
#include <mips/rmi/msgring.h>
#include <mips/rmi/rmi_boot_info.h>
#include <mips/rmi/board.h>
#include <mips/rmi/pic.h>
#define XLR_I2C_RTC_ADDR 0xd0
#define XLR_I2C_EEPROM_ADDR 0xa0
#define XLR_I2C_TEMPSENSOR_ADDR 0x98
#define XLR_I2C_ATX8_TEMPSENSOR_ADDR 0x9a
struct stn_cc *xlr_core_cc_configs[] = { &cc_table_cpu_0, &cc_table_cpu_1,
&cc_table_cpu_2, &cc_table_cpu_3, &cc_table_cpu_4, &cc_table_cpu_5,
&cc_table_cpu_6, &cc_table_cpu_7};
struct stn_cc *xls_core_cc_configs[] = { &xls_cc_table_cpu_0, &xls_cc_table_cpu_1,
&xls_cc_table_cpu_2, &xls_cc_table_cpu_3 };
struct xlr_board_info xlr_board_info;
static int
xlr_pcmcia_present(void)
{
xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_GPIO_OFFSET);
uint32_t resetconf;
resetconf = xlr_read_reg(mmio, 21);
return ((resetconf & 0x4000) != 0);
}
static void
xlr_chip_specific_overrides(struct xlr_board_info* board)
{
struct xlr_gmac_block_t *blk0, *blk1, *blk2;
uint32_t chipid;
uint32_t revision;
blk0 = &board->gmac_block[0];
blk1 = &board->gmac_block[1];
blk2 = &board->gmac_block[2];
chipid = xlr_processor_id();
revision = xlr_revision();
if (revision == 0x04) { /* B2 */
switch (chipid) {
case 0x07: /* XLR 508 */
case 0x08: /* XLR 516 */
case 0x09: /* XLR 532 */
/* NA[12] not available */
memset(blk1, 0, sizeof(*blk1));
memset(blk2, 0, sizeof(*blk2));
break;
case 0x06: /* XLR 308 */
/* NA0 has 3 ports */
blk0->gmac_port[3].valid = 0;
blk0->num_ports--;
/* NA[12] not available */
memset(blk1, 0, sizeof(*blk1));
memset(blk2, 0, sizeof(*blk2));
break;
default:
break;
}
} else if (revision == 0x91) { /* C4 */
switch (chipid) {
case 0x0B: /* XLR 508 */
case 0x0A: /* XLR 516 */
case 0x08: /* XLR 532 */
/* NA[12] not available */
memset(blk1, 0, sizeof(*blk1));
memset(blk2, 0, sizeof(*blk2));
break;
case 0x0F: /* XLR 308 */
/* NA0 has 3 ports */
blk0->gmac_port[3].valid = 0;
blk0->num_ports--;
/* NA[12] not available */
memset(blk1, 0, sizeof(*blk1));
memset(blk2, 0, sizeof(*blk2));
break;
default:
break;
}
} else { /* other pre-production silicon */
switch (chipid) {
/* XLR 5xx */
case 0x0B:
case 0x0A:
case 0x07:
case 0x08:
case 0x09:
/* NA[12] not available */
memset(blk1, 0, sizeof(*blk1));
memset(blk2, 0, sizeof(*blk2));
break;
/* XLR 3xx */
case 0x0F:
case 0x06:
/* NA0 has 3 ports */
blk0->gmac_port[3].valid = 0;
blk0->num_ports--;
/* NA[12] not available */
memset(blk1, 0, sizeof(*blk1));
memset(blk2, 0, sizeof(*blk2));
break;
default:
break;
}
}
}
static void
xlr_board_specific_overrides(struct xlr_board_info* board)
{
struct xlr_gmac_block_t *blk1, *blk2;
blk1 = &board->gmac_block[1];
blk2 = &board->gmac_block[2];
switch (xlr_boot1_info.board_major_version) {
case RMI_XLR_BOARD_ARIZONA_I:
/* ATX-I has SPI-4, not XGMAC */
blk1->type = XLR_SPI4;
blk1->enabled = 0; /* nlge does not
support SPI-4 */
blk2->type = XLR_SPI4;
blk2->enabled = 0;
break;
case RMI_XLR_BOARD_ARIZONA_II:
/* XGMII_A --> VSC7281, XGMII_B --> VSC7281 */
blk1->enabled = 1;
blk1->num_ports = 1;
blk1->gmac_port[0].valid = 1;
blk2->enabled = 1;
blk2->num_ports = 1;
blk2->gmac_port[0].valid = 1;
default:
break;
}
}
static int
quad0_xaui(void)
{
xlr_reg_t *gpio_mmio =
(unsigned int *)(DEFAULT_XLR_IO_BASE + XLR_IO_GPIO_OFFSET);
uint32_t bit24;
bit24 = (xlr_read_reg(gpio_mmio, 0x15) >> 24) & 0x1;
return (bit24);
}
static int
quad1_xaui(void)
{
xlr_reg_t *gpio_mmio =
(unsigned int *)(DEFAULT_XLR_IO_BASE + XLR_IO_GPIO_OFFSET);
uint32_t bit25;
bit25 = (xlr_read_reg(gpio_mmio, 0x15) >> 25) & 0x1;
return (bit25);
}
static void
xls_chip_specific_overrides(struct xlr_board_info* board)
{
struct xlr_gmac_block_t *blk0, *blk1;
uint32_t chipid;
blk0 = &board->gmac_block[0];
blk1 = &board->gmac_block[1];
chipid = xlr_processor_id();
switch (chipid) {
case 0x8E: /* XLS208 */
case 0x8F: /* XLS204 */
/* NA1 is not available */
memset(blk1, 0, sizeof(*blk1));
break;
case 0xCE: /* XLS108 */
case 0xCF: /* XLS104 */
/* NA0 has 3 ports */
blk0->gmac_port[3].valid = 0;
blk0->num_ports--;
/* NA1 is not available */
memset(blk1, 0, sizeof(*blk1));
break;
default:
break;
}
}
static void
xls_board_specific_overrides(struct xlr_board_info* board)
{
struct xlr_gmac_block_t *blk0, *blk1;
int i;
struct xlr_i2c_dev_t* iic_blk;
blk0 = &board->gmac_block[0];
blk1 = &board->gmac_block[1];
switch (xlr_boot1_info.board_major_version) {
case RMI_XLR_BOARD_ARIZONA_VI:
blk0->mode = XLR_PORT0_RGMII;
blk0->gmac_port[0].type = XLR_RGMII;
blk0->gmac_port[0].phy_addr = 0;
blk0->gmac_port[0].mii_addr = XLR_IO_GMAC_4_OFFSET;
/* Because of the Octal PHY, SGMII Quad1 is MII is also bound
* to the PHY attached to SGMII0_MDC/MDIO/MDINT. */
for (i = 0; i < 4; i++) {
blk1->gmac_port[i].mii_addr = XLR_IO_GMAC_0_OFFSET;
blk1->gmac_port[i].serdes_addr = XLR_IO_GMAC_0_OFFSET;
}
blk1->gmac_port[1].mii_addr = XLR_IO_GMAC_0_OFFSET;
blk1->gmac_port[2].mii_addr = XLR_IO_GMAC_0_OFFSET;
blk1->gmac_port[3].mii_addr = XLR_IO_GMAC_0_OFFSET;
blk1->gmac_port[1].serdes_addr = XLR_IO_GMAC_0_OFFSET;
blk1->gmac_port[2].serdes_addr = XLR_IO_GMAC_0_OFFSET;
blk1->gmac_port[3].serdes_addr = XLR_IO_GMAC_0_OFFSET;
/* RGMII MDIO interrupt is thru NA1 and SGMII MDIO
* interrupts for ports in blk1 are from NA0 */
blk0->gmac_port[0].mdint_id = 1;
blk1->gmac_port[0].mdint_id = 0;
blk1->gmac_port[1].mdint_id = 0;
blk1->gmac_port[2].mdint_id = 0;
blk1->gmac_port[3].mdint_id = 0;
/* If we have a 4xx lite chip, don't enable the
* GMACs which are disabled in hardware */
if (xlr_is_xls4xx_lite()) {
xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_GPIO_OFFSET);
uint32_t tmp;
/* Port 6 & 7 are not enabled on the condor 4xx, figure
* this out from the GPIO fuse bank */
tmp = xlr_read_reg(mmio, 35);
if ((tmp & (3 << 28)) != 0) {
blk1->enabled = 0x3;
blk1->gmac_port[2].valid = 0;
blk1->gmac_port[3].valid = 0;
blk1->num_ports = 2;
}
}
break;
case RMI_XLR_BOARD_ARIZONA_VIII:
iic_blk = &xlr_board_info.xlr_i2c_device[I2C_THERMAL];
if (iic_blk->enabled) {
iic_blk->addr = XLR_I2C_ATX8_TEMPSENSOR_ADDR;
}
if (blk1->enabled) {
/* There is just one Octal PHY on the board and it is
* connected to the MII interface for NA Quad 0. */
for (i = 0; i < 4; i++) {
blk1->gmac_port[i].mii_addr =
XLR_IO_GMAC_0_OFFSET;
blk1->gmac_port[i].mdint_id = 0;
}
}
break;
case RMI_XLR_BOARD_ARIZONA_XI:
case RMI_XLR_BOARD_ARIZONA_XII:
if (quad0_xaui()) { /* GMAC ports 0-3 are set to XAUI */
/* only GMAC0 is active i.e, the 0-th port on this quad.
* Disable all the other 7 possible ports. */
for (i = 1; i < MAX_NA_PORTS; i++) {
memset(&blk0->gmac_port[i], 0,
sizeof(blk0->gmac_port[i]));
}
/* Setup for XAUI on N/w Acc0: gmac0 */
blk0->type = XLR_XGMAC;
blk0->mode = XLR_XAUI;
blk0->num_ports = 1;
blk0->gmac_port[0].type = XLR_XAUI;
blk1->gmac_port[0].phy_addr = 16;
blk0->gmac_port[0].tx_bucket_id = blk0->station_txbase;
/* Other addresses etc need not be modified as XAUI_0
* shares its addresses with SGMII GMAC_0, which was
* set in the caller. */
}
else {
blk0->num_ports = 1; /* only 1 RGMII port */
blk0->mode = XLR_PORT0_RGMII;
blk0->gmac_port[0].type = XLR_RGMII;
blk0->gmac_port[0].phy_addr = 0;
blk0->gmac_port[0].mii_addr = XLR_IO_GMAC_0_OFFSET;
}
if (quad1_xaui()) { /* GMAC ports 4-7 are used for XAUI */
/* only GMAC4 is active i.e, the 0-th port on this quad.
* Disable all the other 7 possible ports. */
for (i = 1; i < MAX_NA_PORTS; i++) {
memset(&blk1->gmac_port[i], 0,
sizeof(blk1->gmac_port[i]));
}
/* Setup for XAUI on N/w Acc1: gmac4 */
blk1->type = XLR_XGMAC;
blk1->mode = XLR_XAUI;
blk1->num_ports = 1;
/* XAUI and SGMII ports share FMN buckets on N/w Acc 1;
so, station_txbase, station_rfr need not be
patched up. */
blk1->gmac_port[0].type = XLR_XAUI;
blk1->gmac_port[0].phy_addr = 16;
blk1->gmac_port[0].tx_bucket_id = blk1->station_txbase;
/* Other addresses etc need not be modified as XAUI_1
* shares its addresses with SGMII GMAC_4, which was
* set in the caller. */
}
break;
default:
break;
}
}
/*
* All our knowledge of chip and board that cannot be detected by probing
* at run-time goes here
*/
int
xlr_board_info_setup()
{
struct xlr_gmac_block_t *blk0, *blk1, *blk2;
struct xlr_i2c_dev_t* iic_blk;
int i;
/* This setup code is long'ish because the same base driver
* (if_nlge.c) is used for different:
* - CPUs (XLR/XLS)
* - boards (for each CPU, multiple board configs are possible
* and available).
*
* At the time of writing, there are atleast 12 boards, 4 with XLR
* and 8 with XLS. This means that the base driver needs to work with
* 12 different configurations, with varying levels of differences.
* To accomodate the different configs, the xlr_board_info struct
* has various attributes for paramters that could be different.
* These attributes are setup here and can be used directly in the
* base driver.
* It was seen that the setup code is not entirely trivial and
* it is possible to organize it in different ways. In the following,
* we choose an approach that sacrifices code-compactness/speed for
* readability. This is because configuration code executes once
* per reboot and hence has a minimal performance impact.
* On the other hand, driver debugging/enhancements require
* that different engineers can quickly comprehend the setup
* sequence. Hence, readability is seen as the key requirement for
* this code. It is for the reader to decide how much of this
* requirement is met with the current code organization !!
*
* The initialization is organized thus:
*
* if (CPU is XLS) {
* // initialize per XLS architecture
* // default inits (per chip spec)
* // chip-specific overrides
* // board-specific overrides
* } else if (CPU is XLR) {
* // initialize per XLR architecture
* // default inits (per chip spec)
* // chip-specific overrides
* // board-specific overrides
* }
*
* For each CPU family, all the default initializations
* are done for a fully-loaded device of that family.
* This configuration is then adjusted for the actual
* chip id. This is followed up with board specific
* overrides.
*/
/* start with a clean slate */
memset(&xlr_board_info, 0, sizeof(xlr_board_info));
xlr_board_info.ata = xlr_pcmcia_present();
blk0 = &xlr_board_info.gmac_block[0];
blk1 = &xlr_board_info.gmac_block[1];
blk2 = &xlr_board_info.gmac_block[2];
iic_blk = xlr_board_info.xlr_i2c_device;
iic_blk[I2C_RTC].enabled = 1;
iic_blk[I2C_RTC].addr = XLR_I2C_RTC_ADDR;
iic_blk[I2C_THERMAL].enabled = 1;
iic_blk[I2C_THERMAL].addr = XLR_I2C_TEMPSENSOR_ADDR;
iic_blk[I2C_EEPROM].enabled = 1;
iic_blk[I2C_EEPROM].addr = XLR_I2C_EEPROM_ADDR;
if (xlr_is_xls()) {
xlr_board_info.is_xls = 1;
xlr_board_info.nr_cpus = 8;
xlr_board_info.usb = 1;
/* Board version 8 has NAND flash */
xlr_board_info.cfi =
(xlr_boot1_info.board_major_version != RMI_XLR_BOARD_ARIZONA_VIII);
xlr_board_info.pci_irq = 0;
xlr_board_info.credit_configs = xls_core_cc_configs;
xlr_board_info.bucket_sizes = &xls_bucket_sizes;
xlr_board_info.gmacports = MAX_NA_PORTS;
/* ---------------- Network Acc 0 ---------------- */
blk0->type = XLR_GMAC;
blk0->enabled = 0xf;
blk0->credit_config = &xls_cc_table_gmac0;
blk0->station_id = MSGRNG_STNID_GMAC;
blk0->station_txbase = MSGRNG_STNID_GMACTX0;
blk0->station_rfr = MSGRNG_STNID_GMACRFR_0;
blk0->mode = XLR_SGMII;
blk0->baseaddr = XLR_IO_GMAC_0_OFFSET;
blk0->baseirq = PIC_GMAC_0_IRQ;
blk0->baseinst = 0;
/* By default, assume SGMII is setup. But this can change based
on board-specific or setting-specific info. */
for (i = 0; i < 4; i++) {
blk0->gmac_port[i].valid = 1;
blk0->gmac_port[i].instance = i + blk0->baseinst;
blk0->gmac_port[i].type = XLR_SGMII;
blk0->gmac_port[i].phy_addr = i + 16;
blk0->gmac_port[i].tx_bucket_id =
blk0->station_txbase + i;
blk0->gmac_port[i].mdint_id = 0;
blk0->num_ports++;
blk0->gmac_port[i].base_addr = XLR_IO_GMAC_0_OFFSET + i * 0x1000;
blk0->gmac_port[i].mii_addr = XLR_IO_GMAC_0_OFFSET;
blk0->gmac_port[i].pcs_addr = XLR_IO_GMAC_0_OFFSET;
blk0->gmac_port[i].serdes_addr = XLR_IO_GMAC_0_OFFSET;
}
/* ---------------- Network Acc 1 ---------------- */
blk1->type = XLR_GMAC;
blk1->enabled = 0xf;
blk1->credit_config = &xls_cc_table_gmac1;
blk1->station_id = MSGRNG_STNID_GMAC1;
blk1->station_txbase = MSGRNG_STNID_GMAC1_TX0;
blk1->station_rfr = MSGRNG_STNID_GMAC1_FR_0;
blk1->mode = XLR_SGMII;
blk1->baseaddr = XLR_IO_GMAC_4_OFFSET;
blk1->baseirq = PIC_XGS_0_IRQ;
blk1->baseinst = 4;
for (i = 0; i < 4; i++) {
blk1->gmac_port[i].valid = 1;
blk1->gmac_port[i].instance = i + blk1->baseinst;
blk1->gmac_port[i].type = XLR_SGMII;
blk1->gmac_port[i].phy_addr = i + 20;
blk1->gmac_port[i].tx_bucket_id =
blk1->station_txbase + i;
blk1->gmac_port[i].mdint_id = 1;
blk1->num_ports++;
blk1->gmac_port[i].base_addr = XLR_IO_GMAC_4_OFFSET + i * 0x1000;
blk1->gmac_port[i].mii_addr = XLR_IO_GMAC_4_OFFSET;
blk1->gmac_port[i].pcs_addr = XLR_IO_GMAC_4_OFFSET;
blk1->gmac_port[i].serdes_addr = XLR_IO_GMAC_0_OFFSET;
}
/* ---------------- Network Acc 2 ---------------- */
xlr_board_info.gmac_block[2].enabled = 0; /* disabled on XLS */
xls_chip_specific_overrides(&xlr_board_info);
xls_board_specific_overrides(&xlr_board_info);
} else { /* XLR */
xlr_board_info.is_xls = 0;
xlr_board_info.nr_cpus = 32;
xlr_board_info.usb = 0;
xlr_board_info.cfi = 1;
xlr_board_info.pci_irq = 0;
xlr_board_info.credit_configs = xlr_core_cc_configs;
xlr_board_info.bucket_sizes = &bucket_sizes;
xlr_board_info.gmacports = 4;
/* ---------------- GMAC0 ---------------- */
blk0->type = XLR_GMAC;
blk0->enabled = 0xf;
blk0->credit_config = &cc_table_gmac;
blk0->station_id = MSGRNG_STNID_GMAC;
blk0->station_txbase = MSGRNG_STNID_GMACTX0;
blk0->station_rfr = MSGRNG_STNID_GMACRFR_0;
blk0->mode = XLR_RGMII;
blk0->baseaddr = XLR_IO_GMAC_0_OFFSET;
blk0->baseirq = PIC_GMAC_0_IRQ;
blk0->baseinst = 0;
/* first, do the common/easy stuff for all the ports */
for (i = 0; i < 4; i++) {
blk0->gmac_port[i].valid = 1;
blk0->gmac_port[i].instance = i + blk0->baseinst;
blk0->gmac_port[i].type = XLR_RGMII;
blk0->gmac_port[i].phy_addr = i;
blk0->gmac_port[i].tx_bucket_id =
blk0->station_txbase + i;
blk0->gmac_port[i].mdint_id = 0;
blk0->gmac_port[i].base_addr = XLR_IO_GMAC_0_OFFSET + i * 0x1000;
blk0->gmac_port[i].mii_addr = XLR_IO_GMAC_0_OFFSET;
/* RGMII ports, no PCS/SERDES */
blk0->num_ports++;
}
/* ---------------- XGMAC0 ---------------- */
blk1->type = XLR_XGMAC;
blk1->mode = XLR_XGMII;
blk1->enabled = 0;
blk1->credit_config = &cc_table_xgs_0;
blk1->station_txbase = MSGRNG_STNID_XGS0_TX;
blk1->station_rfr = MSGRNG_STNID_XMAC0RFR;
blk1->station_id = MSGRNG_STNID_XGS0FR;
blk1->baseaddr = XLR_IO_XGMAC_0_OFFSET;
blk1->baseirq = PIC_XGS_0_IRQ;
blk1->baseinst = 4;
blk1->gmac_port[0].type = XLR_XGMII;
blk1->gmac_port[0].instance = 0;
blk1->gmac_port[0].phy_addr = 0;
blk1->gmac_port[0].base_addr = XLR_IO_XGMAC_0_OFFSET;
blk1->gmac_port[0].mii_addr = XLR_IO_XGMAC_0_OFFSET;
blk1->gmac_port[0].tx_bucket_id = blk1->station_txbase;
blk1->gmac_port[0].mdint_id = 1;
/* ---------------- XGMAC1 ---------------- */
blk2->type = XLR_XGMAC;
blk2->mode = XLR_XGMII;
blk2->enabled = 0;
blk2->credit_config = &cc_table_xgs_1;
blk2->station_txbase = MSGRNG_STNID_XGS1_TX;
blk2->station_rfr = MSGRNG_STNID_XMAC1RFR;
blk2->station_id = MSGRNG_STNID_XGS1FR;
blk2->baseaddr = XLR_IO_XGMAC_1_OFFSET;
blk2->baseirq = PIC_XGS_1_IRQ;
blk2->baseinst = 5;
blk2->gmac_port[0].type = XLR_XGMII;
blk2->gmac_port[0].instance = 0;
blk2->gmac_port[0].phy_addr = 0;
blk2->gmac_port[0].base_addr = XLR_IO_XGMAC_1_OFFSET;
blk2->gmac_port[0].mii_addr = XLR_IO_XGMAC_1_OFFSET;
blk2->gmac_port[0].tx_bucket_id = blk2->station_txbase;
blk2->gmac_port[0].mdint_id = 2;
/* Done with default setup. Now handle chip and board-specific
variations. */
xlr_chip_specific_overrides(&xlr_board_info);
xlr_board_specific_overrides(&xlr_board_info);
}
return 0;
}

252
sys/mips/rmi/board.h
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@ -1,252 +0,0 @@
/*-
* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright (c) 2003-2009 RMI Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of RMI Corporation, nor the names of its contributors,
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* RMI_BSD
* $FreeBSD$
*/
#ifndef _RMI_BOARD_H_
#define _RMI_BOARD_H_
/*
* Engineering boards have a major/minor number in their EEPROM to
* identify their configuration
*/
#define RMI_XLR_BOARD_ARIZONA_I 1
#define RMI_XLR_BOARD_ARIZONA_II 2
#define RMI_XLR_BOARD_ARIZONA_III 3
#define RMI_XLR_BOARD_ARIZONA_IV 4
#define RMI_XLR_BOARD_ARIZONA_V 5
#define RMI_XLR_BOARD_ARIZONA_VI 6
#define RMI_XLR_BOARD_ARIZONA_VII 7
#define RMI_XLR_BOARD_ARIZONA_VIII 8
#define RMI_XLR_BOARD_ARIZONA_XI 11
#define RMI_XLR_BOARD_ARIZONA_XII 12
/*
* RMI Chips - Values in Processor ID field
*/
#define RMI_CHIP_XLR732 0x00
#define RMI_CHIP_XLR716 0x02
#define RMI_CHIP_XLR308 0x06
#define RMI_CHIP_XLR532 0x09
/*
* XLR C revisions
*/
#define RMI_CHIP_XLR308_C 0x0F
#define RMI_CHIP_XLR508_C 0x0b
#define RMI_CHIP_XLR516_C 0x0a
#define RMI_CHIP_XLR532_C 0x08
/*
* XLS processors
*/
#define RMI_CHIP_XLS408 0x88 /* Lite "Condor" */
#define RMI_CHIP_XLS608 0x80 /* Internal */
#define RMI_CHIP_XLS404 0x8c /* Lite "Condor" */
#define RMI_CHIP_XLS208 0x8e
#define RMI_CHIP_XLS204 0x8f
#define RMI_CHIP_XLS108 0xce
#define RMI_CHIP_XLS104 0xcf
/*
* XLS B revision chips
*/
#define RMI_CHIP_XLS616_B0 0x40
#define RMI_CHIP_XLS608_B0 0x4a
#define RMI_CHIP_XLS416_B0 0x44
#define RMI_CHIP_XLS412_B0 0x4c
#define RMI_CHIP_XLS408_B0 0x4e
#define RMI_CHIP_XLS404_B0 0x4f
/*
* The XLS product line has chip versions 0x4x and 0x8x
*/
static __inline unsigned int
xlr_is_xls(void)
{
uint32_t prid = mips_rd_prid();
return ((prid & 0xf000) == 0x8000 || (prid & 0xf000) == 0x4000 ||
(prid & 0xf000) == 0xc000);
}
/*
* The last byte of the processor id field is revision
*/
static __inline unsigned int
xlr_revision(void)
{
return (mips_rd_prid() & 0xff);
}
/*
* The 15:8 byte of the PR Id register is the Processor ID
*/
static __inline unsigned int
xlr_processor_id(void)
{
return ((mips_rd_prid() & 0xff00) >> 8);
}
/*
* The processor is XLR and C-Series
*/
static __inline unsigned int
xlr_is_c_revision(void)
{
int processor_id = xlr_processor_id();
int revision_id = xlr_revision();
switch (processor_id) {
/*
* These are the relevant PIDs for XLR
* steppings (hawk and above). For these,
* PIDs, Rev-Ids of [5-9] indicate 'C'.
*/
case RMI_CHIP_XLR308_C:
case RMI_CHIP_XLR508_C:
case RMI_CHIP_XLR516_C:
case RMI_CHIP_XLR532_C:
case RMI_CHIP_XLR716:
case RMI_CHIP_XLR732:
if (revision_id >= 5 && revision_id <= 9)
return (1);
default:
return (0);
}
return (0);
}
/*
* RMI Engineering boards which are PCI cards
* These should come up in PCI device mode (not yet)
*/
static __inline int
xlr_board_pci(int board_major)
{
return ((board_major == RMI_XLR_BOARD_ARIZONA_III) ||
(board_major == RMI_XLR_BOARD_ARIZONA_V));
}
static __inline int
xlr_is_xls1xx(void)
{
uint32_t chipid = xlr_processor_id();
return (chipid == 0xce || chipid == 0xcf);
}
static __inline int
xlr_is_xls2xx(void)
{
uint32_t chipid = xlr_processor_id();
return (chipid == 0x8e || chipid == 0x8f);
}
static __inline int
xlr_is_xls4xx_lite(void)
{
uint32_t chipid = xlr_processor_id();
return (chipid == 0x88 || chipid == 0x8c);
}
static __inline unsigned int
xlr_is_xls_b0(void)
{
uint32_t chipid = xlr_processor_id();
return (chipid >= 0x40 && chipid <= 0x4f);
}
/* SPI-4 --> 8 ports, 1G MAC --> 4 ports and 10G MAC --> 1 port */
#define MAX_NA_PORTS 8
/* all our knowledge of chip and board that cannot be detected run-time goes here */
enum gmac_block_types { XLR_GMAC, XLR_XGMAC, XLR_SPI4};
enum gmac_port_types { XLR_RGMII, XLR_SGMII, XLR_PORT0_RGMII, XLR_XGMII, XLR_XAUI };
enum i2c_dev_types { I2C_RTC, I2C_THERMAL, I2C_EEPROM };
struct xlr_board_info {
int is_xls;
int nr_cpus;
int usb; /* usb enabled ? */
int cfi; /* compact flash driver for NOR? */
int ata; /* ata driver */
int pci_irq;
struct stn_cc **credit_configs; /* pointer to Core station credits */
struct bucket_size *bucket_sizes; /* pointer to Core station bucket */
int *msgmap; /* mapping of message station to devices */
int gmacports; /* number of gmac ports on the board */
struct xlr_i2c_dev_t {
uint32_t addr;
unsigned int enabled; /* mask of devs enabled */
int type;
int unit;
char *dev_name;
} xlr_i2c_device[3];
struct xlr_gmac_block_t { /* refers to the set of GMACs controlled by a
network accelarator */
int type; /* see enum gmac_block_types */
unsigned int enabled; /* mask of ports enabled */
struct stn_cc *credit_config; /* credit configuration */
int station_id; /* station id for sending msgs */
int station_txbase; /* station id for tx */
int station_rfr; /* free desc bucket */
int mode; /* see gmac_block_modes */
uint32_t baseaddr; /* IO base */
int baseirq; /* first irq for this block, the rest are in sequence */
int baseinst; /* the first rge unit for this block */
int num_ports;
struct xlr_gmac_port {
int valid;
int type; /* see enum gmac_port_types */
uint32_t instance; /* identifies the GMAC to which
this port is bound to. */
uint32_t phy_addr;
uint32_t base_addr;
uint32_t mii_addr;
uint32_t pcs_addr;
uint32_t serdes_addr;
uint32_t tx_bucket_id;
uint32_t mdint_id;
} gmac_port[MAX_NA_PORTS];
} gmac_block [3];
};
extern struct xlr_board_info xlr_board_info;
int xlr_board_info_setup(void);
#endif

688
sys/mips/rmi/bus_space_rmi.c
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@ -1,688 +0,0 @@
/*-
* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
*
* Copyright (c) 2009 RMI Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/kernel.h>
#include <sys/endian.h>
#include <sys/malloc.h>
#include <sys/ktr.h>
#include <vm/vm.h>
#include <vm/pmap.h>
#include <vm/vm_kern.h>
#include <vm/vm_extern.h>
#include <machine/bus.h>
#include <machine/cache.h>
static int
rmi_bus_space_map(void *t, bus_addr_t addr,
bus_size_t size, int flags,
bus_space_handle_t * bshp);
static void
rmi_bus_space_unmap(void *t, bus_space_handle_t bsh,
bus_size_t size);
static int
rmi_bus_space_subregion(void *t,
bus_space_handle_t bsh,
bus_size_t offset, bus_size_t size,
bus_space_handle_t * nbshp);
static u_int8_t
rmi_bus_space_read_1(void *t,
bus_space_handle_t handle,
bus_size_t offset);
static u_int16_t
rmi_bus_space_read_2(void *t,
bus_space_handle_t handle,
bus_size_t offset);
static u_int32_t
rmi_bus_space_read_4(void *t,
bus_space_handle_t handle,
bus_size_t offset);
static void
rmi_bus_space_read_multi_1(void *t,
bus_space_handle_t handle,
bus_size_t offset, u_int8_t * addr,
size_t count);
static void
rmi_bus_space_read_multi_2(void *t,
bus_space_handle_t handle,
bus_size_t offset, u_int16_t * addr,
size_t count);
static void
rmi_bus_space_read_multi_4(void *t,
bus_space_handle_t handle,
bus_size_t offset, u_int32_t * addr,
size_t count);
static void
rmi_bus_space_read_region_1(void *t,
bus_space_handle_t bsh,
bus_size_t offset, u_int8_t * addr,
size_t count);
static void
rmi_bus_space_read_region_2(void *t,
bus_space_handle_t bsh,
bus_size_t offset, u_int16_t * addr,
size_t count);
static void
rmi_bus_space_read_region_4(void *t,
bus_space_handle_t bsh,
bus_size_t offset, u_int32_t * addr,
size_t count);
static void
rmi_bus_space_write_1(void *t,
bus_space_handle_t handle,
bus_size_t offset, u_int8_t value);
static void
rmi_bus_space_write_2(void *t,
bus_space_handle_t handle,
bus_size_t offset, u_int16_t value);
static void
rmi_bus_space_write_4(void *t,
bus_space_handle_t handle,
bus_size_t offset, u_int32_t value);
static void
rmi_bus_space_write_multi_1(void *t,
bus_space_handle_t handle,
bus_size_t offset,
const u_int8_t * addr,
size_t count);
static void
rmi_bus_space_write_multi_2(void *t,
bus_space_handle_t handle,
bus_size_t offset,
const u_int16_t * addr,
size_t count);
static void
rmi_bus_space_write_multi_4(void *t,
bus_space_handle_t handle,
bus_size_t offset,
const u_int32_t * addr,
size_t count);
static void
rmi_bus_space_write_region_2(void *t,
bus_space_handle_t bsh,
bus_size_t offset,
const u_int16_t * addr,
size_t count);
static void
rmi_bus_space_write_region_4(void *t,
bus_space_handle_t bsh,
bus_size_t offset,
const u_int32_t * addr,
size_t count);
static void
rmi_bus_space_set_region_2(void *t,
bus_space_handle_t bsh,
bus_size_t offset, u_int16_t value,
size_t count);
static void
rmi_bus_space_set_region_4(void *t,
bus_space_handle_t bsh,
bus_size_t offset, u_int32_t value,
size_t count);
static void
rmi_bus_space_barrier(void *tag __unused, bus_space_handle_t bsh __unused,
bus_size_t offset __unused, bus_size_t len __unused, int flags);
static void
rmi_bus_space_copy_region_2(void *t,
bus_space_handle_t bsh1,
bus_size_t off1,
bus_space_handle_t bsh2,
bus_size_t off2, size_t count);
u_int8_t
rmi_bus_space_read_stream_1(void *t, bus_space_handle_t handle,
bus_size_t offset);
static u_int16_t
rmi_bus_space_read_stream_2(void *t, bus_space_handle_t handle,
bus_size_t offset);
static u_int32_t
rmi_bus_space_read_stream_4(void *t, bus_space_handle_t handle,
bus_size_t offset);
static void
rmi_bus_space_read_multi_stream_1(void *t,
bus_space_handle_t handle,
bus_size_t offset, u_int8_t * addr,
size_t count);
static void
rmi_bus_space_read_multi_stream_2(void *t,
bus_space_handle_t handle,
bus_size_t offset, u_int16_t * addr,
size_t count);
static void
rmi_bus_space_read_multi_stream_4(void *t,
bus_space_handle_t handle,
bus_size_t offset, u_int32_t * addr,
size_t count);
void
rmi_bus_space_write_stream_1(void *t, bus_space_handle_t bsh,
bus_size_t offset, u_int8_t value);
static void
rmi_bus_space_write_stream_2(void *t, bus_space_handle_t handle,
bus_size_t offset, u_int16_t value);
static void
rmi_bus_space_write_stream_4(void *t, bus_space_handle_t handle,
bus_size_t offset, u_int32_t value);
static void
rmi_bus_space_write_multi_stream_1(void *t,
bus_space_handle_t handle,
bus_size_t offset,
const u_int8_t * addr,
size_t count);
static void
rmi_bus_space_write_multi_stream_2(void *t,
bus_space_handle_t handle,
bus_size_t offset,
const u_int16_t * addr,
size_t count);
static void
rmi_bus_space_write_multi_stream_4(void *t,
bus_space_handle_t handle,
bus_size_t offset,
const u_int32_t * addr,
size_t count);
#define TODO() printf("XLR memory bus space function '%s' unimplemented\n", __func__)
static struct bus_space local_rmi_bus_space = {
/* cookie */
(void *)0,
/* mapping/unmapping */
rmi_bus_space_map,
rmi_bus_space_unmap,
rmi_bus_space_subregion,
/* allocation/deallocation */
NULL,
NULL,
/* barrier */
rmi_bus_space_barrier,
/* read (single) */
rmi_bus_space_read_1,
rmi_bus_space_read_2,
rmi_bus_space_read_4,
NULL,
/* read multiple */
rmi_bus_space_read_multi_1,
rmi_bus_space_read_multi_2,
rmi_bus_space_read_multi_4,
NULL,
/* read region */
rmi_bus_space_read_region_1,
rmi_bus_space_read_region_2,
rmi_bus_space_read_region_4,
NULL,
/* write (single) */
rmi_bus_space_write_1,
rmi_bus_space_write_2,
rmi_bus_space_write_4,
NULL,
/* write multiple */
rmi_bus_space_write_multi_1,
rmi_bus_space_write_multi_2,
rmi_bus_space_write_multi_4,
NULL,
/* write region */
NULL,
rmi_bus_space_write_region_2,
rmi_bus_space_write_region_4,
NULL,
/* set multiple */
NULL,
NULL,
NULL,
NULL,
/* set region */
NULL,
rmi_bus_space_set_region_2,
rmi_bus_space_set_region_4,
NULL,
/* copy */
NULL,
rmi_bus_space_copy_region_2,
NULL,
NULL,
/* read (single) stream */
rmi_bus_space_read_stream_1,
rmi_bus_space_read_stream_2,
rmi_bus_space_read_stream_4,
NULL,
/* read multiple stream */
rmi_bus_space_read_multi_stream_1,
rmi_bus_space_read_multi_stream_2,
rmi_bus_space_read_multi_stream_4,
NULL,
/* read region stream */
rmi_bus_space_read_region_1,
rmi_bus_space_read_region_2,
rmi_bus_space_read_region_4,
NULL,
/* write (single) stream */
rmi_bus_space_write_stream_1,
rmi_bus_space_write_stream_2,
rmi_bus_space_write_stream_4,
NULL,
/* write multiple stream */
rmi_bus_space_write_multi_stream_1,
rmi_bus_space_write_multi_stream_2,
rmi_bus_space_write_multi_stream_4,
NULL,
/* write region stream */
NULL,
rmi_bus_space_write_region_2,
rmi_bus_space_write_region_4,
NULL,
};
/* generic bus_space tag */
bus_space_tag_t rmi_bus_space = &local_rmi_bus_space;
/*
* Map a region of device bus space into CPU virtual address space.
*/
static int
rmi_bus_space_map(void *t __unused, bus_addr_t addr,
bus_size_t size __unused, int flags __unused,
bus_space_handle_t * bshp)
{
*bshp = addr;
return (0);
}
/*
* Unmap a region of device bus space.
*/
static void
rmi_bus_space_unmap(void *t __unused, bus_space_handle_t bsh __unused,
bus_size_t size __unused)
{
}
/*
* Get a new handle for a subregion of an already-mapped area of bus space.
*/
static int
rmi_bus_space_subregion(void *t __unused, bus_space_handle_t bsh,
bus_size_t offset, bus_size_t size __unused,
bus_space_handle_t * nbshp)
{
*nbshp = bsh + offset;
return (0);
}
/*
* Read a 1, 2, 4, or 8 byte quantity from bus space
* described by tag/handle/offset.
*/
static u_int8_t
rmi_bus_space_read_1(void *tag, bus_space_handle_t handle,
bus_size_t offset)
{
return (u_int8_t) (*(volatile u_int32_t *)(handle + offset));
}
static u_int16_t
rmi_bus_space_read_2(void *tag, bus_space_handle_t handle,
bus_size_t offset)
{
return (u_int16_t)(*(volatile u_int32_t *)(handle + offset));
}
static u_int32_t
rmi_bus_space_read_4(void *tag, bus_space_handle_t handle,
bus_size_t offset)
{
return (*(volatile u_int32_t *)(handle + offset));
}
/*
* Read `count' 1, 2, 4, or 8 byte quantities from bus space
* described by tag/handle/offset and copy into buffer provided.
*/
static void
rmi_bus_space_read_multi_1(void *tag, bus_space_handle_t handle,
bus_size_t offset, u_int8_t * addr, size_t count)
{
TODO();
}
static void
rmi_bus_space_read_multi_2(void *tag, bus_space_handle_t handle,
bus_size_t offset, u_int16_t * addr, size_t count)
{
TODO();
}
static void
rmi_bus_space_read_multi_4(void *tag, bus_space_handle_t handle,
bus_size_t offset, u_int32_t * addr, size_t count)
{
TODO();
}
/*
* Write the 1, 2, 4, or 8 byte value `value' to bus space
* described by tag/handle/offset.
*/
static void
rmi_bus_space_write_1(void *tag, bus_space_handle_t handle,
bus_size_t offset, u_int8_t value)
{
*(volatile u_int32_t *)(handle + offset) = (u_int32_t)value;
}
static void
rmi_bus_space_write_2(void *tag, bus_space_handle_t handle,
bus_size_t offset, u_int16_t value)
{
*(volatile u_int32_t *)(handle + offset) = (u_int32_t)value;
}
static void
rmi_bus_space_write_4(void *tag, bus_space_handle_t handle,
bus_size_t offset, u_int32_t value)
{
*(volatile u_int32_t *)(handle + offset) = value;
}
/*
* Write `count' 1, 2, 4, or 8 byte quantities from the buffer
* provided to bus space described by tag/handle/offset.
*/
static void
rmi_bus_space_write_multi_1(void *tag, bus_space_handle_t handle,
bus_size_t offset, const u_int8_t * addr, size_t count)
{
TODO();
}
static void
rmi_bus_space_write_multi_2(void *tag, bus_space_handle_t handle,
bus_size_t offset, const u_int16_t * addr, size_t count)
{
TODO();
}
static void
rmi_bus_space_write_multi_4(void *tag, bus_space_handle_t handle,
bus_size_t offset, const u_int32_t * addr, size_t count)
{
TODO();
}
/*
* Write `count' 1, 2, 4, or 8 byte value `val' to bus space described
* by tag/handle starting at `offset'.
*/
static void
rmi_bus_space_set_region_2(void *t, bus_space_handle_t bsh,
bus_size_t offset, u_int16_t value, size_t count)
{
bus_addr_t addr = bsh + offset;
for (; count != 0; count--, addr += 2)
(*(volatile u_int32_t *)(addr)) = value;
}
static void
rmi_bus_space_set_region_4(void *t, bus_space_handle_t bsh,
bus_size_t offset, u_int32_t value, size_t count)
{
bus_addr_t addr = bsh + offset;
for (; count != 0; count--, addr += 4)
(*(volatile u_int32_t *)(addr)) = value;
}
/*
* Copy `count' 1, 2, 4, or 8 byte values from bus space starting
* at tag/bsh1/off1 to bus space starting at tag/bsh2/off2.
*/
static void
rmi_bus_space_copy_region_2(void *t, bus_space_handle_t bsh1,
bus_size_t off1, bus_space_handle_t bsh2,
bus_size_t off2, size_t count)
{
printf("bus_space_copy_region_2 - unimplemented\n");
}
/*
* Read `count' 1, 2, 4, or 8 byte quantities from bus space
* described by tag/handle/offset and copy into buffer provided.
*/
u_int8_t
rmi_bus_space_read_stream_1(void *t, bus_space_handle_t handle,
bus_size_t offset)
{
return *((volatile u_int8_t *)(handle + offset));
}
static u_int16_t
rmi_bus_space_read_stream_2(void *t, bus_space_handle_t handle,
bus_size_t offset)
{
return *(volatile u_int16_t *)(handle + offset);
}
static u_int32_t
rmi_bus_space_read_stream_4(void *t, bus_space_handle_t handle,
bus_size_t offset)
{
return (*(volatile u_int32_t *)(handle + offset));
}
static void
rmi_bus_space_read_multi_stream_1(void *tag, bus_space_handle_t handle,
bus_size_t offset, u_int8_t * addr, size_t count)
{
TODO();
}
static void
rmi_bus_space_read_multi_stream_2(void *tag, bus_space_handle_t handle,
bus_size_t offset, u_int16_t * addr, size_t count)
{
TODO();
}
static void
rmi_bus_space_read_multi_stream_4(void *tag, bus_space_handle_t handle,
bus_size_t offset, u_int32_t * addr, size_t count)
{
TODO();
}
/*
* Read `count' 1, 2, 4, or 8 byte quantities from bus space
* described by tag/handle and starting at `offset' and copy into
* buffer provided.
*/
void
rmi_bus_space_read_region_1(void *t, bus_space_handle_t bsh,
bus_size_t offset, u_int8_t * addr, size_t count)
{
TODO();
}
void
rmi_bus_space_read_region_2(void *t, bus_space_handle_t bsh,
bus_size_t offset, u_int16_t * addr, size_t count)
{
TODO();
}
void
rmi_bus_space_read_region_4(void *t, bus_space_handle_t bsh,
bus_size_t offset, u_int32_t * addr, size_t count)
{
bus_addr_t baddr = bsh + offset;
while (count--) {
*addr++ = (*(volatile u_int32_t *)(baddr));
baddr += 4;
}
}
void
rmi_bus_space_write_stream_1(void *t, bus_space_handle_t handle,
bus_size_t offset, u_int8_t value)
{
TODO();
}
static void
rmi_bus_space_write_stream_2(void *t, bus_space_handle_t handle,
bus_size_t offset, u_int16_t value)
{
TODO();
}
static void
rmi_bus_space_write_stream_4(void *t, bus_space_handle_t handle,
bus_size_t offset, u_int32_t value)
{
TODO();
}
static void
rmi_bus_space_write_multi_stream_1(void *tag, bus_space_handle_t handle,
bus_size_t offset, const u_int8_t * addr, size_t count)
{
TODO();
}
static void
rmi_bus_space_write_multi_stream_2(void *tag, bus_space_handle_t handle,
bus_size_t offset, const u_int16_t * addr, size_t count)
{
TODO();
}
static void
rmi_bus_space_write_multi_stream_4(void *tag, bus_space_handle_t handle,
bus_size_t offset, const u_int32_t * addr, size_t count)
{
TODO();
}
void
rmi_bus_space_write_region_2(void *t,
bus_space_handle_t bsh,
bus_size_t offset,
const u_int16_t * addr,
size_t count)
{
TODO();
}
void
rmi_bus_space_write_region_4(void *t, bus_space_handle_t bsh,
bus_size_t offset, const u_int32_t * addr, size_t count)
{
TODO();
}
static void
rmi_bus_space_barrier(void *tag __unused, bus_space_handle_t bsh __unused,
bus_size_t offset __unused, bus_size_t len __unused, int flags)
{
}

763
sys/mips/rmi/bus_space_rmi_pci.c
View File

@ -1,763 +0,0 @@
/*-
* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
*
* Copyright (c) 2009 RMI Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/kernel.h>
#include <sys/endian.h>
#include <sys/malloc.h>
#include <sys/ktr.h>
#include <vm/vm.h>
#include <vm/pmap.h>
#include <vm/vm_kern.h>
#include <vm/vm_extern.h>
#include <machine/bus.h>
#include <machine/cache.h>
static int
rmi_pci_bus_space_map(void *t, bus_addr_t addr,
bus_size_t size, int flags,
bus_space_handle_t * bshp);
static void
rmi_pci_bus_space_unmap(void *t, bus_space_handle_t bsh,
bus_size_t size);
static int
rmi_pci_bus_space_subregion(void *t,
bus_space_handle_t bsh,
bus_size_t offset, bus_size_t size,
bus_space_handle_t * nbshp);
static u_int8_t
rmi_pci_bus_space_read_1(void *t,
bus_space_handle_t handle,
bus_size_t offset);
static u_int16_t
rmi_pci_bus_space_read_2(void *t,
bus_space_handle_t handle,
bus_size_t offset);
static u_int32_t
rmi_pci_bus_space_read_4(void *t,
bus_space_handle_t handle,
bus_size_t offset);
static void
rmi_pci_bus_space_read_multi_1(void *t,
bus_space_handle_t handle,
bus_size_t offset, u_int8_t * addr,
size_t count);
static void
rmi_pci_bus_space_read_multi_2(void *t,
bus_space_handle_t handle,
bus_size_t offset, u_int16_t * addr,
size_t count);
static void
rmi_pci_bus_space_read_multi_4(void *t,
bus_space_handle_t handle,
bus_size_t offset, u_int32_t * addr,
size_t count);
static void
rmi_pci_bus_space_read_region_1(void *t,
bus_space_handle_t bsh,
bus_size_t offset, u_int8_t * addr,
size_t count);
static void
rmi_pci_bus_space_read_region_2(void *t,
bus_space_handle_t bsh,
bus_size_t offset, u_int16_t * addr,
size_t count);
static void
rmi_pci_bus_space_read_region_4(void *t,
bus_space_handle_t bsh,
bus_size_t offset, u_int32_t * addr,
size_t count);
static void
rmi_pci_bus_space_write_1(void *t,
bus_space_handle_t handle,
bus_size_t offset, u_int8_t value);
static void
rmi_pci_bus_space_write_2(void *t,
bus_space_handle_t handle,
bus_size_t offset, u_int16_t value);
static void
rmi_pci_bus_space_write_4(void *t,
bus_space_handle_t handle,
bus_size_t offset, u_int32_t value);
static void
rmi_pci_bus_space_write_multi_1(void *t,
bus_space_handle_t handle,
bus_size_t offset,
const u_int8_t * addr,
size_t count);
static void
rmi_pci_bus_space_write_multi_2(void *t,
bus_space_handle_t handle,
bus_size_t offset,
const u_int16_t * addr,
size_t count);
static void
rmi_pci_bus_space_write_multi_4(void *t,
bus_space_handle_t handle,
bus_size_t offset,
const u_int32_t * addr,
size_t count);
static void
rmi_pci_bus_space_write_region_2(void *t,
bus_space_handle_t bsh,
bus_size_t offset,
const u_int16_t * addr,
size_t count);
static void
rmi_pci_bus_space_write_region_4(void *t,
bus_space_handle_t bsh,
bus_size_t offset,
const u_int32_t * addr,
size_t count);
static void
rmi_pci_bus_space_set_region_2(void *t,
bus_space_handle_t bsh,
bus_size_t offset, u_int16_t value,
size_t count);
static void
rmi_pci_bus_space_set_region_4(void *t,
bus_space_handle_t bsh,
bus_size_t offset, u_int32_t value,
size_t count);
static void
rmi_pci_bus_space_barrier(void *tag __unused, bus_space_handle_t bsh __unused,
bus_size_t offset __unused, bus_size_t len __unused, int flags);
static void
rmi_pci_bus_space_copy_region_2(void *t,
bus_space_handle_t bsh1,
bus_size_t off1,
bus_space_handle_t bsh2,
bus_size_t off2, size_t count);
u_int8_t
rmi_pci_bus_space_read_stream_1(void *t, bus_space_handle_t handle,
bus_size_t offset);
static u_int16_t
rmi_pci_bus_space_read_stream_2(void *t, bus_space_handle_t handle,
bus_size_t offset);
static u_int32_t
rmi_pci_bus_space_read_stream_4(void *t, bus_space_handle_t handle,
bus_size_t offset);
static void
rmi_pci_bus_space_read_multi_stream_1(void *t,
bus_space_handle_t handle,
bus_size_t offset, u_int8_t * addr,
size_t count);
static void
rmi_pci_bus_space_read_multi_stream_2(void *t,
bus_space_handle_t handle,
bus_size_t offset, u_int16_t * addr,
size_t count);
static void
rmi_pci_bus_space_read_multi_stream_4(void *t,
bus_space_handle_t handle,
bus_size_t offset, u_int32_t * addr,
size_t count);
void
rmi_pci_bus_space_write_stream_1(void *t, bus_space_handle_t bsh,
bus_size_t offset, u_int8_t value);
static void
rmi_pci_bus_space_write_stream_2(void *t, bus_space_handle_t handle,
bus_size_t offset, u_int16_t value);
static void
rmi_pci_bus_space_write_stream_4(void *t, bus_space_handle_t handle,
bus_size_t offset, u_int32_t value);
static void
rmi_pci_bus_space_write_multi_stream_1(void *t,
bus_space_handle_t handle,
bus_size_t offset,
const u_int8_t * addr,
size_t count);
static void
rmi_pci_bus_space_write_multi_stream_2(void *t,
bus_space_handle_t handle,
bus_size_t offset,
const u_int16_t * addr,
size_t count);
static void
rmi_pci_bus_space_write_multi_stream_4(void *t,
bus_space_handle_t handle,
bus_size_t offset,
const u_int32_t * addr,
size_t count);
#define TODO() printf("XLR memory bus space function '%s' unimplemented\n", __func__)
static struct bus_space local_rmi_pci_bus_space = {
/* cookie */
(void *)0,
/* mapping/unmapping */
rmi_pci_bus_space_map,
rmi_pci_bus_space_unmap,
rmi_pci_bus_space_subregion,
/* allocation/deallocation */
NULL,
NULL,
/* barrier */
rmi_pci_bus_space_barrier,
/* read (single) */
rmi_pci_bus_space_read_1,
rmi_pci_bus_space_read_2,
rmi_pci_bus_space_read_4,
NULL,
/* read multiple */
rmi_pci_bus_space_read_multi_1,
rmi_pci_bus_space_read_multi_2,
rmi_pci_bus_space_read_multi_4,
NULL,
/* read region */
rmi_pci_bus_space_read_region_1,
rmi_pci_bus_space_read_region_2,
rmi_pci_bus_space_read_region_4,
NULL,
/* write (single) */
rmi_pci_bus_space_write_1,
rmi_pci_bus_space_write_2,
rmi_pci_bus_space_write_4,
NULL,
/* write multiple */
rmi_pci_bus_space_write_multi_1,
rmi_pci_bus_space_write_multi_2,
rmi_pci_bus_space_write_multi_4,
NULL,
/* write region */
NULL,
rmi_pci_bus_space_write_region_2,
rmi_pci_bus_space_write_region_4,
NULL,
/* set multiple */
NULL,
NULL,
NULL,
NULL,
/* set region */
NULL,
rmi_pci_bus_space_set_region_2,
rmi_pci_bus_space_set_region_4,
NULL,
/* copy */
NULL,
rmi_pci_bus_space_copy_region_2,
NULL,
NULL,
/* read (single) stream */
rmi_pci_bus_space_read_stream_1,
rmi_pci_bus_space_read_stream_2,
rmi_pci_bus_space_read_stream_4,
NULL,
/* read multiple stream */
rmi_pci_bus_space_read_multi_stream_1,
rmi_pci_bus_space_read_multi_stream_2,
rmi_pci_bus_space_read_multi_stream_4,
NULL,
/* read region stream */
rmi_pci_bus_space_read_region_1,
rmi_pci_bus_space_read_region_2,
rmi_pci_bus_space_read_region_4,
NULL,
/* write (single) stream */
rmi_pci_bus_space_write_stream_1,
rmi_pci_bus_space_write_stream_2,
rmi_pci_bus_space_write_stream_4,
NULL,
/* write multiple stream */
rmi_pci_bus_space_write_multi_stream_1,
rmi_pci_bus_space_write_multi_stream_2,
rmi_pci_bus_space_write_multi_stream_4,
NULL,
/* write region stream */
NULL,
rmi_pci_bus_space_write_region_2,
rmi_pci_bus_space_write_region_4,
NULL,
};
/* generic bus_space tag */
bus_space_tag_t rmi_pci_bus_space = &local_rmi_pci_bus_space;
/*
* Map a region of device bus space into CPU virtual address space.
*/
static int
rmi_pci_bus_space_map(void *t __unused, bus_addr_t addr,
bus_size_t size __unused, int flags __unused,
bus_space_handle_t * bshp)
{
*bshp = addr;
return (0);
}
/*
* Unmap a region of device bus space.
*/
static void
rmi_pci_bus_space_unmap(void *t __unused, bus_space_handle_t bsh __unused,
bus_size_t size __unused)
{
}
/*
* Get a new handle for a subregion of an already-mapped area of bus space.
*/
static int
rmi_pci_bus_space_subregion(void *t __unused, bus_space_handle_t bsh,
bus_size_t offset, bus_size_t size __unused,
bus_space_handle_t * nbshp)
{
*nbshp = bsh + offset;
return (0);
}
/*
* Read a 1, 2, 4, or 8 byte quantity from bus space
* described by tag/handle/offset.
*/
static u_int8_t
rmi_pci_bus_space_read_1(void *tag, bus_space_handle_t handle,
bus_size_t offset)
{
return (u_int8_t) (*(volatile u_int8_t *)(handle + offset));
}
static u_int16_t
rmi_pci_bus_space_read_2(void *tag, bus_space_handle_t handle,
bus_size_t offset)
{
return bswap16((u_int16_t) (*(volatile u_int16_t *)(handle + offset)));
}
static u_int32_t
rmi_pci_bus_space_read_4(void *tag, bus_space_handle_t handle,
bus_size_t offset)
{
return bswap32((*(volatile u_int32_t *)(handle + offset)));
}
/*
* Read `count' 1, 2, 4, or 8 byte quantities from bus space
* described by tag/handle/offset and copy into buffer provided.
*/
static void
rmi_pci_bus_space_read_multi_1(void *tag, bus_space_handle_t handle,
bus_size_t offset, u_int8_t * addr, size_t count)
{
while (count--) {
*addr = (*(volatile u_int8_t *)(handle + offset));
addr++;
}
}
static void
rmi_pci_bus_space_read_multi_2(void *tag, bus_space_handle_t handle,
bus_size_t offset, u_int16_t * addr, size_t count)
{
while (count--) {
*addr = *(volatile u_int16_t *)(handle + offset);
*addr = bswap16(*addr);
addr++;
}
}
static void
rmi_pci_bus_space_read_multi_4(void *tag, bus_space_handle_t handle,
bus_size_t offset, u_int32_t * addr, size_t count)
{
while (count--) {
*addr = *(volatile u_int32_t *)(handle + offset);
*addr = bswap32(*addr);
addr++;
}
}
/*
* Write the 1, 2, 4, or 8 byte value `value' to bus space
* described by tag/handle/offset.
*/
static void
rmi_pci_bus_space_write_1(void *tag, bus_space_handle_t handle,
bus_size_t offset, u_int8_t value)
{
mips_sync();
*(volatile u_int8_t *)(handle + offset) = value;
}
static void
rmi_pci_bus_space_write_2(void *tag, bus_space_handle_t handle,
bus_size_t offset, u_int16_t value)
{
mips_sync();
*(volatile u_int16_t *)(handle + offset) = bswap16(value);
}
static void
rmi_pci_bus_space_write_4(void *tag, bus_space_handle_t handle,
bus_size_t offset, u_int32_t value)
{
mips_sync();
*(volatile u_int32_t *)(handle + offset) = bswap32(value);
}
/*
* Write `count' 1, 2, 4, or 8 byte quantities from the buffer
* provided to bus space described by tag/handle/offset.
*/
static void
rmi_pci_bus_space_write_multi_1(void *tag, bus_space_handle_t handle,
bus_size_t offset, const u_int8_t * addr, size_t count)
{
mips_sync();
while (count--) {
(*(volatile u_int8_t *)(handle + offset)) = *addr;
addr++;
}
}
static void
rmi_pci_bus_space_write_multi_2(void *tag, bus_space_handle_t handle,
bus_size_t offset, const u_int16_t * addr, size_t count)
{
mips_sync();
while (count--) {
(*(volatile u_int16_t *)(handle + offset)) = bswap16(*addr);
addr++;
}
}
static void
rmi_pci_bus_space_write_multi_4(void *tag, bus_space_handle_t handle,
bus_size_t offset, const u_int32_t * addr, size_t count)
{
mips_sync();
while (count--) {
(*(volatile u_int32_t *)(handle + offset)) = bswap32(*addr);
addr++;
}
}
/*
* Write `count' 1, 2, 4, or 8 byte value `val' to bus space described
* by tag/handle starting at `offset'.
*/
static void
rmi_pci_bus_space_set_region_2(void *t, bus_space_handle_t bsh,
bus_size_t offset, u_int16_t value, size_t count)
{
bus_addr_t addr = bsh + offset;
for (; count != 0; count--, addr += 2)
(*(volatile u_int16_t *)(addr)) = value;
}
static void
rmi_pci_bus_space_set_region_4(void *t, bus_space_handle_t bsh,
bus_size_t offset, u_int32_t value, size_t count)
{
bus_addr_t addr = bsh + offset;
for (; count != 0; count--, addr += 4)
(*(volatile u_int32_t *)(addr)) = value;
}
/*
* Copy `count' 1, 2, 4, or 8 byte values from bus space starting
* at tag/bsh1/off1 to bus space starting at tag/bsh2/off2.
*/
static void
rmi_pci_bus_space_copy_region_2(void *t, bus_space_handle_t bsh1,
bus_size_t off1, bus_space_handle_t bsh2,
bus_size_t off2, size_t count)
{
TODO();
}
/*
* Read `count' 1, 2, 4, or 8 byte quantities from bus space
* described by tag/handle/offset and copy into buffer provided.
*/
u_int8_t
rmi_pci_bus_space_read_stream_1(void *t, bus_space_handle_t handle,
bus_size_t offset)
{
return *((volatile u_int8_t *)(handle + offset));
}
static u_int16_t
rmi_pci_bus_space_read_stream_2(void *t, bus_space_handle_t handle,
bus_size_t offset)
{
return *(volatile u_int16_t *)(handle + offset);
}
static u_int32_t
rmi_pci_bus_space_read_stream_4(void *t, bus_space_handle_t handle,
bus_size_t offset)
{
return (*(volatile u_int32_t *)(handle + offset));
}
static void
rmi_pci_bus_space_read_multi_stream_1(void *tag, bus_space_handle_t handle,
bus_size_t offset, u_int8_t * addr, size_t count)
{
while (count--) {
*addr = (*(volatile u_int8_t *)(handle + offset));
addr++;
}
}
static void
rmi_pci_bus_space_read_multi_stream_2(void *tag, bus_space_handle_t handle,
bus_size_t offset, u_int16_t * addr, size_t count)
{
while (count--) {
*addr = (*(volatile u_int16_t *)(handle + offset));
addr++;
}
}
static void
rmi_pci_bus_space_read_multi_stream_4(void *tag, bus_space_handle_t handle,
bus_size_t offset, u_int32_t * addr, size_t count)
{
while (count--) {
*addr = (*(volatile u_int32_t *)(handle + offset));
addr++;
}
}
/*
* Read `count' 1, 2, 4, or 8 byte quantities from bus space
* described by tag/handle and starting at `offset' and copy into
* buffer provided.
*/
void
rmi_pci_bus_space_read_region_1(void *t, bus_space_handle_t bsh,
bus_size_t offset, u_int8_t * addr, size_t count)
{
bus_addr_t baddr = bsh + offset;
while (count--) {
*addr++ = (*(volatile u_int8_t *)(baddr));
baddr += 1;
}
}
void
rmi_pci_bus_space_read_region_2(void *t, bus_space_handle_t bsh,
bus_size_t offset, u_int16_t * addr, size_t count)
{
bus_addr_t baddr = bsh + offset;
while (count--) {
*addr++ = (*(volatile u_int16_t *)(baddr));
baddr += 2;
}
}
void
rmi_pci_bus_space_read_region_4(void *t, bus_space_handle_t bsh,
bus_size_t offset, u_int32_t * addr, size_t count)
{
bus_addr_t baddr = bsh + offset;
while (count--) {
*addr++ = (*(volatile u_int32_t *)(baddr));
baddr += 4;
}
}
void
rmi_pci_bus_space_write_stream_1(void *t, bus_space_handle_t handle,
bus_size_t offset, u_int8_t value)
{
mips_sync();
*(volatile u_int8_t *)(handle + offset) = value;
}
static void
rmi_pci_bus_space_write_stream_2(void *t, bus_space_handle_t handle,
bus_size_t offset, u_int16_t value)
{
mips_sync();
*(volatile u_int16_t *)(handle + offset) = value;
}
static void
rmi_pci_bus_space_write_stream_4(void *t, bus_space_handle_t handle,
bus_size_t offset, u_int32_t value)
{
mips_sync();
*(volatile u_int32_t *)(handle + offset) = value;
}
static void
rmi_pci_bus_space_write_multi_stream_1(void *tag, bus_space_handle_t handle,
bus_size_t offset, const u_int8_t * addr, size_t count)
{
mips_sync();
while (count--) {
(*(volatile u_int8_t *)(handle + offset)) = *addr;
addr++;
}
}
static void
rmi_pci_bus_space_write_multi_stream_2(void *tag, bus_space_handle_t handle,
bus_size_t offset, const u_int16_t * addr, size_t count)
{
mips_sync();
while (count--) {
(*(volatile u_int16_t *)(handle + offset)) = *addr;
addr++;
}
}
static void
rmi_pci_bus_space_write_multi_stream_4(void *tag, bus_space_handle_t handle,
bus_size_t offset, const u_int32_t * addr, size_t count)
{
mips_sync();
while (count--) {
(*(volatile u_int32_t *)(handle + offset)) = *addr;
addr++;
}
}
void
rmi_pci_bus_space_write_region_2(void *t,
bus_space_handle_t bsh,
bus_size_t offset,
const u_int16_t * addr,
size_t count)
{
bus_addr_t baddr = (bus_addr_t) bsh + offset;
while (count--) {
(*(volatile u_int16_t *)(baddr)) = *addr;
addr++;
baddr += 2;
}
}
void
rmi_pci_bus_space_write_region_4(void *t, bus_space_handle_t bsh,
bus_size_t offset, const u_int32_t * addr, size_t count)
{
bus_addr_t baddr = bsh + offset;
while (count--) {
(*(volatile u_int32_t *)(baddr)) = *addr;
addr++;
baddr += 4;
}
}
static void
rmi_pci_bus_space_barrier(void *tag __unused, bus_space_handle_t bsh __unused,
bus_size_t offset __unused, bus_size_t len __unused, int flags)
{
}

142
sys/mips/rmi/dev/iic/at24co2n.c
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@ -1,142 +0,0 @@
/*-
* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright (c) 2003-2009 RMI Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of RMI Corporation, nor the names of its contributors,
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* RMI_BSD */
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
/*
* reading eeprom for the mac address .
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/lock.h>
#include <sys/module.h>
#include <sys/mutex.h>
#include <sys/bus.h>
#include <sys/resource.h>
#include <sys/rman.h>
#include <sys/sysctl.h>
#include <machine/bus.h>
#include <machine/cpu.h>
#include <machine/cpufunc.h>
#include <machine/frame.h>
#include <machine/resource.h>
#include <dev/iicbus/iiconf.h>
#include <dev/iicbus/iicbus.h>
#include "iicbus_if.h"
#define AT24CO_EEPROM_ETH_MACADDR 0x20
struct at24co2n_softc {
uint32_t sc_addr;
device_t sc_dev;
uint8_t sc_mac_addr[6];
};
static void at24co2n_read_mac(struct at24co2n_softc *);
static int
at24co2n_probe(device_t dev)
{
device_set_desc(dev, "AT24Co2N-10SE-2.7 EEPROM for mac address");
return (0);
}
static int
at24co2n_mac_sysctl(SYSCTL_HANDLER_ARGS)
{
struct at24co2n_softc *sc = arg1;
char buf[24];
int len;
uint8_t *p;
at24co2n_read_mac(sc);
p = sc->sc_mac_addr;
len = snprintf(buf, sizeof(buf), "%02x:%02x:%02x:%02x:%02x:%02x",
p[0], p[1], p[2], p[3], p[4], p[5]);
return SYSCTL_OUT_STR(req, buf);
}
static int
at24co2n_attach(device_t dev)
{
struct at24co2n_softc *sc = device_get_softc(dev);
struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev);
struct sysctl_oid *tree = device_get_sysctl_tree(dev);
if(sc == NULL) {
printf("at24co2n_attach device_get_softc failed\n");
return (0);
}
sc->sc_dev = dev;
sc->sc_addr = iicbus_get_addr(dev);
SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
"eeprom-mac", CTLTYPE_STRING | CTLFLAG_RD, sc, 0,
at24co2n_mac_sysctl, "A", "mac address");
return (0);
}
static void
at24co2n_read_mac(struct at24co2n_softc *sc)
{
uint8_t addr = AT24CO_EEPROM_ETH_MACADDR;
struct iic_msg msgs[2] = {
{ sc->sc_addr, IIC_M_WR, 1, &addr },
{ sc->sc_addr, IIC_M_RD, 6, sc->sc_mac_addr},
};
iicbus_transfer(sc->sc_dev, msgs, 2);
}
static device_method_t at24co2n_methods[] = {
DEVMETHOD(device_probe, at24co2n_probe),
DEVMETHOD(device_attach, at24co2n_attach),
{0, 0},
};
static driver_t at24co2n_driver = {
"at24co2n",
at24co2n_methods,
sizeof(struct at24co2n_softc),
};
static devclass_t at24co2n_devclass;
DRIVER_MODULE(at24co2n, iicbus, at24co2n_driver, at24co2n_devclass, 0, 0);
MODULE_VERSION(at24co2n, 1);
MODULE_DEPEND(at24co2n, iicbus, 1, 1, 1);

160
sys/mips/rmi/dev/iic/max6657.c
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@ -1,160 +0,0 @@
/*-
* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright (c) 2003-2009 RMI Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of RMI Corporation, nor the names of its contributors,
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* RMI_BSD */
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
/*
* temperature sensor chip sitting on the I2C bus.
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/lock.h>
#include <sys/module.h>
#include <sys/mutex.h>
#include <sys/bus.h>
#include <sys/resource.h>
#include <sys/rman.h>
#include <sys/sysctl.h>
#include <machine/bus.h>
#include <machine/cpu.h>
#include <machine/cpufunc.h>
#include <machine/frame.h>
#include <machine/resource.h>
#include <dev/iicbus/iiconf.h>
#include <dev/iicbus/iicbus.h>
#include <mips/rmi/board.h>
#include <mips/rmi/rmi_boot_info.h>
#include "iicbus_if.h"
#define MAX6657_EXT_TEMP 1
struct max6657_softc {
uint32_t sc_addr;
device_t sc_dev;
int sc_curtemp;
int sc_lastupdate; /* in ticks */
};
static void max6657_update(struct max6657_softc *);
static int max6657_read(device_t dev, uint32_t addr, int reg) ;
static int
max6657_probe(device_t dev)
{
device_set_desc(dev, "MAX6657MSA Temperature Sensor");
return (0);
}
static int
max6657_sysctl_temp(SYSCTL_HANDLER_ARGS)
{
struct max6657_softc *sc = arg1;
int temp;
max6657_update(sc);
temp = sc->sc_curtemp ;
return sysctl_handle_int(oidp, &temp, 0, req);
}
static int
max6657_attach(device_t dev)
{
struct max6657_softc *sc = device_get_softc(dev);
struct sysctl_ctx_list *ctx = device_get_sysctl_ctx(dev);
struct sysctl_oid *tree = device_get_sysctl_tree(dev);
if(sc==NULL) {
printf("max6657_attach device_get_softc failed\n");
return (0);
}
sc->sc_dev = dev;
sc->sc_addr = iicbus_get_addr(dev);
SYSCTL_ADD_PROC(ctx, SYSCTL_CHILDREN(tree), OID_AUTO,
"temp", CTLTYPE_INT | CTLFLAG_RD, sc, 0,
max6657_sysctl_temp, "I", "operating temperature");
device_printf(dev, "Chip temperature {%d} Degree Celsius\n",
max6657_read(sc->sc_dev, sc->sc_addr, MAX6657_EXT_TEMP));
return (0);
}
static int
max6657_read(device_t dev, uint32_t slave_addr, int reg)
{
uint8_t addr = reg;
uint8_t data[1];
struct iic_msg msgs[2] = {
{ slave_addr, IIC_M_WR, 1, &addr },
{ slave_addr, IIC_M_RD, 1, data },
};
return iicbus_transfer(dev, msgs, 2) != 0 ? -1 : data[0];
}
static void
max6657_update(struct max6657_softc *sc)
{
int v;
/* NB: no point in updating any faster than the chip */
if (ticks - sc->sc_lastupdate > hz) {
v = max6657_read(sc->sc_dev, sc->sc_addr, MAX6657_EXT_TEMP);
if (v >= 0)
sc->sc_curtemp = v;
sc->sc_lastupdate = ticks;
}
}
static device_method_t max6657_methods[] = {
DEVMETHOD(device_probe, max6657_probe),
DEVMETHOD(device_attach, max6657_attach),
{0, 0},
};
static driver_t max6657_driver = {
"max6657",
max6657_methods,
sizeof(struct max6657_softc),
};
static devclass_t max6657_devclass;
DRIVER_MODULE(max6657, iicbus, max6657_driver, max6657_devclass, 0, 0);
MODULE_VERSION(max6657, 1);
MODULE_DEPEND(max6657, iicbus, 1, 1, 1);

2565
sys/mips/rmi/dev/nlge/if_nlge.c
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1184
sys/mips/rmi/dev/nlge/if_nlge.h
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3070
sys/mips/rmi/dev/sec/desc.h
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3076
sys/mips/rmi/dev/sec/rmilib.c
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1002
sys/mips/rmi/dev/sec/rmilib.h
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573
sys/mips/rmi/dev/sec/rmisec.c
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@ -1,573 +0,0 @@
/*-
* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright (c) 2003-2009 RMI Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of RMI Corporation, nor the names of its contributors,
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* RMI_BSD
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/proc.h>
#include <sys/errno.h>
#include <sys/malloc.h>
#include <sys/kernel.h>
#include <sys/module.h>
#include <sys/mbuf.h>
#include <sys/lock.h>
#include <sys/mutex.h>
#include <sys/sysctl.h>
#include <sys/bus.h>
#include <sys/random.h>
#include <sys/rman.h>
#include <sys/uio.h>
#include <sys/kobj.h>
#include <opencrypto/cryptodev.h>
#include "cryptodev_if.h"
#include <vm/vm.h>
#include <vm/pmap.h>
#include <mips/rmi/dev/sec/rmilib.h>
/* #define RMI_SEC_DEBUG */
void xlr_sec_print_data(struct cryptop *crp);
static int xlr_sec_newsession(device_t dev, uint32_t * sidp, struct cryptoini *cri);
static int xlr_sec_freesession(device_t dev, uint64_t tid);
static int xlr_sec_process(device_t dev, struct cryptop *crp, int hint);
static int xlr_sec_probe(device_t);
static int xlr_sec_attach(device_t);
static int xlr_sec_detach(device_t);
static device_method_t xlr_sec_methods[] = {
/* device interface */
DEVMETHOD(device_probe, xlr_sec_probe),
DEVMETHOD(device_attach, xlr_sec_attach),
DEVMETHOD(device_detach, xlr_sec_detach),
/* crypto device methods */
DEVMETHOD(cryptodev_newsession, xlr_sec_newsession),
DEVMETHOD(cryptodev_freesession,xlr_sec_freesession),
DEVMETHOD(cryptodev_process, xlr_sec_process),
DEVMETHOD_END
};
static driver_t xlr_sec_driver = {
"rmisec",
xlr_sec_methods,
sizeof(struct xlr_sec_softc)
};
static devclass_t xlr_sec_devclass;
DRIVER_MODULE(rmisec, iodi, xlr_sec_driver, xlr_sec_devclass, 0, 0);
MODULE_DEPEND(rmisec, crypto, 1, 1, 1);
static int
xlr_sec_probe(device_t dev)
{
device_set_desc(dev, "XLR Security Accelerator");
return (BUS_PROBE_DEFAULT);
}
/*
* Attach an interface that successfully probed.
*/
static int
xlr_sec_attach(device_t dev)
{
struct xlr_sec_softc *sc = device_get_softc(dev);
sc->sc_dev = dev;
mtx_init(&sc->sc_mtx, device_get_nameunit(dev), "rmi crypto driver",
MTX_DEF);
sc->sc_cid = crypto_get_driverid(dev, CRYPTOCAP_F_HARDWARE);
if (sc->sc_cid < 0) {
printf("xlr_sec - error : could not get the driver id\n");
goto error_exit;
}
if (crypto_register(sc->sc_cid, CRYPTO_DES_CBC, 0, 0) != 0)
printf("register failed for CRYPTO_DES_CBC\n");
if (crypto_register(sc->sc_cid, CRYPTO_3DES_CBC, 0, 0) != 0)
printf("register failed for CRYPTO_3DES_CBC\n");
if (crypto_register(sc->sc_cid, CRYPTO_AES_CBC, 0, 0) != 0)
printf("register failed for CRYPTO_AES_CBC\n");
if (crypto_register(sc->sc_cid, CRYPTO_ARC4, 0, 0) != 0)
printf("register failed for CRYPTO_ARC4\n");
if (crypto_register(sc->sc_cid, CRYPTO_MD5, 0, 0) != 0)
printf("register failed for CRYPTO_MD5\n");
if (crypto_register(sc->sc_cid, CRYPTO_SHA1, 0, 0) != 0)
printf("register failed for CRYPTO_SHA1\n");
if (crypto_register(sc->sc_cid, CRYPTO_MD5_HMAC, 0, 0) != 0)
printf("register failed for CRYPTO_MD5_HMAC\n");
if (crypto_register(sc->sc_cid, CRYPTO_SHA1_HMAC, 0, 0) != 0)
printf("register failed for CRYPTO_SHA1_HMAC\n");
xlr_sec_init(sc);
device_printf(dev, "Initialization complete!\n");
return (0);
error_exit:
return (ENXIO);
}
/*
* Detach an interface that successfully probed.
*/
static int
xlr_sec_detach(device_t dev)
{
int sesn;
struct xlr_sec_softc *sc = device_get_softc(dev);
struct xlr_sec_session *ses = NULL;
symkey_desc_pt desc;
for (sesn = 0; sesn < sc->sc_nsessions; sesn++) {
ses = &sc->sc_sessions[sesn];
desc = (symkey_desc_pt) ses->desc_ptr;
free(desc->user.kern_src, M_DEVBUF);
free(desc->user.kern_dest, M_DEVBUF);
free(desc->next_src_buf, M_DEVBUF);
free(desc->next_dest_buf, M_DEVBUF);
free(ses->desc_ptr, M_DEVBUF);
}
return (0);
}
/*
* Allocate a new 'session' and return an encoded session id. 'sidp'
* contains our registration id, and should contain an encoded session
* id on successful allocation.
*/
static int
xlr_sec_newsession(device_t dev, u_int32_t *sidp, struct cryptoini *cri)
{
struct cryptoini *c;
struct xlr_sec_softc *sc = device_get_softc(dev);
int mac = 0, cry = 0, sesn;
struct xlr_sec_session *ses = NULL;
if (sidp == NULL || cri == NULL || sc == NULL)
return (EINVAL);
if (sc->sc_sessions == NULL) {
ses = sc->sc_sessions = (struct xlr_sec_session *)malloc(
sizeof(struct xlr_sec_session), M_DEVBUF, M_NOWAIT);
if (ses == NULL)
return (ENOMEM);
sesn = 0;
sc->sc_nsessions = 1;
} else {
for (sesn = 0; sesn < sc->sc_nsessions; sesn++) {
if (!sc->sc_sessions[sesn].hs_used) {
ses = &sc->sc_sessions[sesn];
break;
}
}
if (ses == NULL) {
sesn = sc->sc_nsessions;
ses = (struct xlr_sec_session *)malloc((sesn + 1) *
sizeof(struct xlr_sec_session), M_DEVBUF, M_NOWAIT);
if (ses == NULL)
return (ENOMEM);
bcopy(sc->sc_sessions, ses, sesn * sizeof(*ses));
bzero(sc->sc_sessions, sesn * sizeof(*ses));
free(sc->sc_sessions, M_DEVBUF);
sc->sc_sessions = ses;
ses = &sc->sc_sessions[sesn];
sc->sc_nsessions++;
}
}
bzero(ses, sizeof(*ses));
ses->sessionid = sesn;
ses->desc_ptr = xlr_sec_allocate_desc(ses);
if (ses->desc_ptr == NULL)
return (ENOMEM);
ses->hs_used = 1;
for (c = cri; c != NULL; c = c->cri_next) {
switch (c->cri_alg) {
case CRYPTO_MD5:
case CRYPTO_SHA1:
case CRYPTO_MD5_HMAC:
case CRYPTO_SHA1_HMAC:
if (mac)
return (EINVAL);
mac = 1;
ses->hs_mlen = c->cri_mlen;
if (ses->hs_mlen == 0) {
switch (c->cri_alg) {
case CRYPTO_MD5:
case CRYPTO_MD5_HMAC:
ses->hs_mlen = 16;
break;
case CRYPTO_SHA1:
case CRYPTO_SHA1_HMAC:
ses->hs_mlen = 20;
break;
}
}
break;
case CRYPTO_DES_CBC:
case CRYPTO_3DES_CBC:
case CRYPTO_AES_CBC:
/* XXX this may read fewer, does it matter? */
/*
* read_random(ses->hs_iv, c->cri_alg ==
* CRYPTO_AES_CBC ? XLR_SEC_AES_IV_LENGTH :
* XLR_SEC_IV_LENGTH);
*/
/* FALLTHROUGH */
case CRYPTO_ARC4:
if (cry)
return (EINVAL);
cry = 1;
break;
default:
return (EINVAL);
}
}
if (mac == 0 && cry == 0)
return (EINVAL);
*sidp = XLR_SEC_SID(device_get_unit(sc->sc_dev), sesn);
return (0);
}
/*
* Deallocate a session.
* XXX this routine should run a zero'd mac/encrypt key into context ram.
* XXX to blow away any keys already stored there.
*/
static int
xlr_sec_freesession(device_t dev, u_int64_t tid)
{
struct xlr_sec_softc *sc = device_get_softc(dev);
int session;
u_int32_t sid = CRYPTO_SESID2LID(tid);
if (sc == NULL)
return (EINVAL);
session = XLR_SEC_SESSION(sid);
if (session >= sc->sc_nsessions)
return (EINVAL);
sc->sc_sessions[session].hs_used = 0;
return (0);
}
#ifdef RMI_SEC_DEBUG
void
xlr_sec_print_data(struct cryptop *crp)
{
int i, key_len;
struct cryptodesc *crp_desc;
printf("session id = 0x%llx, crp_ilen = %d, crp_olen=%d \n",
crp->crp_sid, crp->crp_ilen, crp->crp_olen);
printf("crp_flags = 0x%x\n", crp->crp_flags);
printf("crp buf:\n");
for (i = 0; i < crp->crp_ilen; i++) {
printf("%c ", crp->crp_buf[i]);
if (i % 10 == 0)
printf("\n");
}
printf("\n");
printf("****************** desc ****************\n");
crp_desc = crp->crp_desc;
printf("crd_skip=%d, crd_len=%d, crd_flags=0x%x, crd_alg=%d\n",
crp_desc->crd_skip, crp_desc->crd_len, crp_desc->crd_flags, crp_desc->crd_alg);
key_len = crp_desc->crd_klen / 8;
printf("key(%d) :\n", key_len);
for (i = 0; i < key_len; i++)
printf("%d", crp_desc->crd_key[i]);
printf("\n");
printf(" IV : \n");
for (i = 0; i < EALG_MAX_BLOCK_LEN; i++)
printf("%d", crp_desc->crd_iv[i]);
printf("\n");
printf("crd_next=%p\n", crp_desc->crd_next);
return;
}
#endif
static int
xlr_sec_process(device_t dev, struct cryptop *crp, int hint)
{
struct xlr_sec_softc *sc = device_get_softc(dev);
struct xlr_sec_command *cmd = NULL;
int session, err;
struct cryptodesc *crd1, *crd2, *maccrd, *enccrd;
struct xlr_sec_session *ses;
if (crp == NULL || crp->crp_callback == NULL) {
return (EINVAL);
}
session = XLR_SEC_SESSION(crp->crp_sid);
if (sc == NULL || session >= sc->sc_nsessions) {
err = EINVAL;
goto errout;
}
ses = &sc->sc_sessions[session];
cmd = &ses->cmd;
if (cmd == NULL) {
err = ENOMEM;
goto errout;
}
crd1 = crp->crp_desc;
if (crd1 == NULL) {
err = EINVAL;
goto errout;
}
crd2 = crd1->crd_next;
if (crd2 == NULL) {
if (crd1->crd_alg == CRYPTO_MD5_HMAC ||
crd1->crd_alg == CRYPTO_SHA1_HMAC ||
crd1->crd_alg == CRYPTO_SHA1 ||
crd1->crd_alg == CRYPTO_MD5) {
maccrd = crd1;
enccrd = NULL;
} else if (crd1->crd_alg == CRYPTO_DES_CBC ||
crd1->crd_alg == CRYPTO_3DES_CBC ||
crd1->crd_alg == CRYPTO_AES_CBC ||
crd1->crd_alg == CRYPTO_ARC4) {
maccrd = NULL;
enccrd = crd1;
} else {
err = EINVAL;
goto errout;
}
} else {
if ((crd1->crd_alg == CRYPTO_MD5_HMAC ||
crd1->crd_alg == CRYPTO_SHA1_HMAC ||
crd1->crd_alg == CRYPTO_MD5 ||
crd1->crd_alg == CRYPTO_SHA1) &&
(crd2->crd_alg == CRYPTO_DES_CBC ||
crd2->crd_alg == CRYPTO_3DES_CBC ||
crd2->crd_alg == CRYPTO_AES_CBC ||
crd2->crd_alg == CRYPTO_ARC4)) {
maccrd = crd1;
enccrd = crd2;
} else if ((crd1->crd_alg == CRYPTO_DES_CBC ||
crd1->crd_alg == CRYPTO_ARC4 ||
crd1->crd_alg == CRYPTO_3DES_CBC ||
crd1->crd_alg == CRYPTO_AES_CBC) &&
(crd2->crd_alg == CRYPTO_MD5_HMAC ||
crd2->crd_alg == CRYPTO_SHA1_HMAC ||
crd2->crd_alg == CRYPTO_MD5 ||
crd2->crd_alg == CRYPTO_SHA1) &&
(crd1->crd_flags & CRD_F_ENCRYPT)) {
enccrd = crd1;
maccrd = crd2;
} else {
err = EINVAL;
goto errout;
}
}
bzero(&cmd->op, sizeof(xlr_sec_io_t));
cmd->op.source_buf = (uint64_t) (unsigned long)crp->crp_buf;
cmd->op.source_buf_size = crp->crp_ilen;
cmd->op.dest_buf = (uint64_t) (unsigned long)crp->crp_buf;
cmd->op.dest_buf_size = crp->crp_ilen;
cmd->op.num_packets = 1;
cmd->op.num_fragments = 1;
if (cmd->op.source_buf_size > SEC_MAX_FRAG_LEN) {
ses->multi_frag_flag = 1;
} else {
ses->multi_frag_flag = 0;
}
if (maccrd) {
cmd->maccrd = maccrd;
cmd->op.cipher_op = XLR_SEC_CIPHER_MODE_PASS;
cmd->op.cipher_mode = XLR_SEC_CIPHER_MODE_NONE;
cmd->op.cipher_type = XLR_SEC_CIPHER_TYPE_NONE;
cmd->op.cipher_init = 0;
cmd->op.cipher_offset = 0;
switch (maccrd->crd_alg) {
case CRYPTO_MD5:
cmd->op.digest_type = XLR_SEC_DIGEST_TYPE_MD5;
cmd->op.digest_init = XLR_SEC_DIGEST_INIT_NEWKEY;
cmd->op.digest_src = XLR_SEC_DIGEST_SRC_DMA;
cmd->op.digest_offset = 0;
cmd->op.cksum_type = XLR_SEC_CKSUM_TYPE_NOP;
cmd->op.cksum_src = XLR_SEC_CKSUM_SRC_CIPHER;
cmd->op.cksum_offset = 0;
cmd->op.pkt_hmac = XLR_SEC_LOADHMACKEY_MODE_OLD;
cmd->op.pkt_hash = XLR_SEC_PADHASH_PAD;
cmd->op.pkt_hashbytes = XLR_SEC_HASHBYTES_ALL8;
cmd->op.pkt_next = XLR_SEC_NEXT_FINISH;
cmd->op.pkt_iv = XLR_SEC_PKT_IV_OLD;
cmd->op.pkt_lastword = XLR_SEC_LASTWORD_128;
default:
printf("currently not handled\n");
}
}
if (enccrd) {
cmd->enccrd = enccrd;
#ifdef RMI_SEC_DEBUG
xlr_sec_print_data(crp);
#endif
if (enccrd->crd_flags & CRD_F_ENCRYPT) {
cmd->op.cipher_op = XLR_SEC_CIPHER_OP_ENCRYPT;
} else
cmd->op.cipher_op = XLR_SEC_CIPHER_OP_DECRYPT;
switch (enccrd->crd_alg) {
case CRYPTO_DES_CBC:
case CRYPTO_3DES_CBC:
if (enccrd->crd_alg == CRYPTO_DES_CBC) {
cmd->op.cipher_type = XLR_SEC_CIPHER_TYPE_DES;
memcpy(&cmd->op.crypt_key[0], enccrd->crd_key, XLR_SEC_DES_KEY_LENGTH);
} else {
cmd->op.cipher_type = XLR_SEC_CIPHER_TYPE_3DES;
//if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT)
{
memcpy(&cmd->op.crypt_key[0], enccrd->crd_key,
XLR_SEC_3DES_KEY_LENGTH);
}
}
cmd->op.cipher_mode = XLR_SEC_CIPHER_MODE_CBC;
cmd->op.cipher_init = XLR_SEC_CIPHER_INIT_NK;
cmd->op.cipher_offset = XLR_SEC_DES_IV_LENGTH;
cmd->op.digest_type = XLR_SEC_DIGEST_TYPE_NONE;
cmd->op.digest_init = XLR_SEC_DIGEST_INIT_OLDKEY;
cmd->op.digest_src = XLR_SEC_DIGEST_SRC_DMA;
cmd->op.digest_offset = 0;
cmd->op.cksum_type = XLR_SEC_CKSUM_TYPE_NOP;
cmd->op.cksum_src = XLR_SEC_CKSUM_SRC_CIPHER;
cmd->op.cksum_offset = 0;
cmd->op.pkt_hmac = XLR_SEC_LOADHMACKEY_MODE_OLD;
cmd->op.pkt_hash = XLR_SEC_PADHASH_PAD;
cmd->op.pkt_hashbytes = XLR_SEC_HASHBYTES_ALL8;
cmd->op.pkt_next = XLR_SEC_NEXT_FINISH;
cmd->op.pkt_iv = XLR_SEC_PKT_IV_NEW;
cmd->op.pkt_lastword = XLR_SEC_LASTWORD_128;
//if ((!(enccrd->crd_flags & CRD_F_IV_PRESENT)) &&
if ((enccrd->crd_flags & CRD_F_IV_EXPLICIT)) {
memcpy(&cmd->op.initial_vector[0], enccrd->crd_iv,
XLR_SEC_DES_IV_LENGTH);
}
break;
case CRYPTO_AES_CBC:
if (enccrd->crd_alg == CRYPTO_AES_CBC) {
cmd->op.cipher_type = XLR_SEC_CIPHER_TYPE_AES128;
//if (enccrd->crd_flags & CRD_F_KEY_EXPLICIT)
{
memcpy(&cmd->op.crypt_key[0], enccrd->crd_key,
XLR_SEC_AES128_KEY_LENGTH);
}
}
cmd->op.cipher_mode = XLR_SEC_CIPHER_MODE_CBC;
cmd->op.cipher_init = XLR_SEC_CIPHER_INIT_NK;
cmd->op.cipher_offset = XLR_SEC_AES_BLOCK_SIZE;
cmd->op.digest_type = XLR_SEC_DIGEST_TYPE_NONE;
cmd->op.digest_init = XLR_SEC_DIGEST_INIT_OLDKEY;
cmd->op.digest_src = XLR_SEC_DIGEST_SRC_DMA;
cmd->op.digest_offset = 0;
cmd->op.cksum_type = XLR_SEC_CKSUM_TYPE_NOP;
cmd->op.cksum_src = XLR_SEC_CKSUM_SRC_CIPHER;
cmd->op.cksum_offset = 0;
cmd->op.pkt_hmac = XLR_SEC_LOADHMACKEY_MODE_OLD;
cmd->op.pkt_hash = XLR_SEC_PADHASH_PAD;
cmd->op.pkt_hashbytes = XLR_SEC_HASHBYTES_ALL8;
cmd->op.pkt_next = XLR_SEC_NEXT_FINISH;
cmd->op.pkt_iv = XLR_SEC_PKT_IV_NEW;
cmd->op.pkt_lastword = XLR_SEC_LASTWORD_128;
//if (!(enccrd->crd_flags & CRD_F_IV_PRESENT)) {
if ((enccrd->crd_flags & CRD_F_IV_EXPLICIT)) {
memcpy(&cmd->op.initial_vector[0], enccrd->crd_iv,
XLR_SEC_AES_BLOCK_SIZE);
}
//}
break;
}
}
cmd->crp = crp;
cmd->session_num = session;
xlr_sec_setup(ses, cmd, (symkey_desc_pt) ses->desc_ptr);
return (0);
errout:
if (cmd != NULL)
free(cmd, M_DEVBUF);
crp->crp_etype = err;
crypto_done(crp);
return (err);
}

56
sys/mips/rmi/dev/xlr/atx_cpld.h
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@ -1,56 +0,0 @@
/*-
* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright (c) 2003-2009 RMI Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of RMI Corporation, nor the names of its contributors,
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
* RMI_BSD */
#ifndef _RMI_ATX_CPLD_H_
#define _RMI_ATX_CPLD_H_
/*
* bit_0 : xgs0 phy reset, bit_1 : xgs1 phy reset, bit_2 : HT reset, bit_3 :
* RTC reset, bit_4 : gmac phy soft reset, bit_5 : gmac phy hard reset, bit_6
* : board reset, bit_7 : reserved
*/
#define ATX_CPLD_RESET_1 2
/*
* bit_0_2 : reserved, bit_3 : turn off xpak_0 tx, bit_4 : turn off xpak_1
* tx, bit_5 : HT stop (active low), bit_6 : flash program enable, bit_7 :
* compact flash io mode
*/
#define ATX_CPLD_MISC_CTRL 8
/*
* bit_0 : reset tcam, bit_1 : reset xpak_0 module, bit_2 : reset xpak_1
* module, bit_3_7 : reserved
*/
#define ATX_CPLD_RESET_2 9
#endif /* _RMI_ATX_CPLD_H_ */

107
sys/mips/rmi/dev/xlr/debug.h
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@ -1,107 +0,0 @@
/*-
* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright (c) 2003-2009 RMI Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of RMI Corporation, nor the names of its contributors,
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* RMI_BSD
* $FreeBSD$
*/
#ifndef _RMI_DEBUG_H_
#define _RMI_DEBUG_H_
#include <machine/atomic.h>
enum {
//cacheline 0
MSGRNG_INT,
MSGRNG_PIC_INT,
MSGRNG_MSG,
MSGRNG_EXIT_STATUS,
MSGRNG_MSG_CYCLES,
//cacheline 1
NETIF_TX = 8,
NETIF_RX,
NETIF_TX_COMPLETE,
NETIF_TX_COMPLETE_TX,
NETIF_RX_CYCLES,
NETIF_TX_COMPLETE_CYCLES,
NETIF_TX_CYCLES,
NETIF_TIMER_START_Q,
//NETIF_REG_FRIN,
//NETIF_INT_REG,
//cacheline 2
REPLENISH_ENTER = 16,
REPLENISH_ENTER_COUNT,
REPLENISH_CPU,
REPLENISH_FRIN,
REPLENISH_CYCLES,
NETIF_STACK_TX,
NETIF_START_Q,
NETIF_STOP_Q,
//cacheline 3
USER_MAC_START = 24,
USER_MAC_INT = 24,
USER_MAC_TX_COMPLETE,
USER_MAC_RX,
USER_MAC_POLL,
USER_MAC_TX,
USER_MAC_TX_FAIL,
USER_MAC_TX_COUNT,
USER_MAC_FRIN,
//cacheline 4
USER_MAC_TX_FAIL_GMAC_CREDITS = 32,
USER_MAC_DO_PAGE_FAULT,
USER_MAC_UPDATE_TLB,
USER_MAC_UPDATE_BIGTLB,
USER_MAC_UPDATE_TLB_PFN0,
USER_MAC_UPDATE_TLB_PFN1,
XLR_MAX_COUNTERS = 40
};
extern int xlr_counters[MAXCPU][XLR_MAX_COUNTERS];
extern __uint32_t msgrng_msg_cycles;
#ifdef ENABLE_DEBUG
#define xlr_inc_counter(x) atomic_add_int(&xlr_counters[PCPU_GET(cpuid)][(x)], 1)
#define xlr_dec_counter(x) atomic_subtract_int(&xlr_counters[PCPU_GET(cpuid)][(x)], 1)
#define xlr_set_counter(x, value) atomic_set_int(&xlr_counters[PCPU_GET(cpuid)][(x)], (value))
#define xlr_get_counter(x) (&xlr_counters[0][(x)])
#else /* default mode */
#define xlr_inc_counter(x)
#define xlr_dec_counter(x)
#define xlr_set_counter(x, value)
#define xlr_get_counter(x)
#endif
#define dbg_msg(fmt, args...) printf(fmt, ##args)
#define dbg_panic(fmt, args...) panic(fmt, ##args)
#endif

130
sys/mips/rmi/dev/xlr/xgmac_mdio.h
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@ -1,130 +0,0 @@
/*-
* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright (c) 2003-2009 RMI Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of RMI Corporation, nor the names of its contributors,
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
* RMI_BSD */
/* MDIO Low level Access routines */
/* All Phy's accessed from GMAC0 base */
#ifndef _XGMAC_MDIO_H_
#define _XGMAC_MDIO_H_
static inline int
xmdio_read(volatile unsigned int *_mmio,
uint32_t phy_addr, uint32_t address);
static inline void
xmdio_write(volatile unsigned int *_mmio,
uint32_t phy_addr, uint32_t address, uint32_t data);
static inline void
xmdio_address(volatile unsigned int *_mmio,
uint32_t phy_addr, uint32_t dev_ad, uint32_t address);
static inline void
xmdio_address(volatile unsigned int *_mmio,
uint32_t phy_addr, uint32_t dev_ad, uint32_t address)
{
uint32_t st_field = 0x0;
uint32_t op_type = 0x0; /* address operation */
uint32_t ta_field = 0x2;/* ta field */
_mmio[0x11] = ((st_field & 0x3) << 30) |
((op_type & 0x3) << 28) |
((phy_addr & 0x1F) << 23) |
((dev_ad & 0x1F) << 18) |
((ta_field & 0x3) << 16) |
((address & 0xffff) << 0);
_mmio[0x10] = (0x0 << 3) | 0x5;
_mmio[0x10] = (0x1 << 3) | 0x5;
_mmio[0x10] = (0x0 << 3) | 0x5;
/* wait for dev_ad cycle to complete */
while (_mmio[0x14] & 0x1) {
};
}
/* function prototypes */
static inline int
xmdio_read(volatile unsigned int *_mmio,
uint32_t phy_addr, uint32_t address)
{
uint32_t st_field = 0x0;
uint32_t op_type = 0x3; /* read operation */
uint32_t ta_field = 0x2;/* ta field */
uint32_t data = 0;
xmdio_address(_mmio, phy_addr, 5, address);
_mmio[0x11] = ((st_field & 0x3) << 30) |
((op_type & 0x3) << 28) |
((phy_addr & 0x1F) << 23) |
((5 & 0x1F) << 18) |
((ta_field & 0x3) << 16) |
((data & 0xffff) << 0);
_mmio[0x10] = (0x0 << 3) | 0x5;
_mmio[0x10] = (0x1 << 3) | 0x5;
_mmio[0x10] = (0x0 << 3) | 0x5;
/* wait for write cycle to complete */
while (_mmio[0x14] & 0x1) {
};
data = _mmio[0x11] & 0xffff;
return (data);
}
static inline void
xmdio_write(volatile unsigned int *_mmio,
uint32_t phy_addr, uint32_t address, uint32_t data)
{
uint32_t st_field = 0x0;
uint32_t op_type = 0x1; /* write operation */
uint32_t ta_field = 0x2;/* ta field */
xmdio_address(_mmio, phy_addr, 5, address);
_mmio[0x11] = ((st_field & 0x3) << 30) |
((op_type & 0x3) << 28) |
((phy_addr & 0x1F) << 23) |
((5 & 0x1F) << 18) |
((ta_field & 0x3) << 16) |
((data & 0xffff) << 0);
_mmio[0x10] = (0x0 << 3) | 0x5;
_mmio[0x10] = (0x1 << 3) | 0x5;
_mmio[0x10] = (0x0 << 3) | 0x5;
/* wait for write cycle to complete */
while (_mmio[0x14] & 0x1) {
};
}
#endif

25
sys/mips/rmi/files.xlr
View File

@ -1,25 +0,0 @@
# $FreeBSD$
#mips/rmi/xlr_boot1_console.c standard
mips/rmi/xlr_machdep.c standard
#mips/rmi/clock.c standard
mips/rmi/tick.c standard
mips/rmi/iodi.c standard
mips/rmi/msgring.c standard
mips/rmi/msgring_xls.c standard
mips/rmi/board.c standard
mips/rmi/fmn.c standard
mips/rmi/intr_machdep.c standard
mips/rmi/mpwait.S optional smp
mips/rmi/xlr_i2c.c optional iic
mips/rmi/uart_bus_xlr_iodi.c optional uart
mips/rmi/uart_cpu_mips_xlr.c optional uart
mips/rmi/xlr_pci.c optional pci
mips/rmi/xlr_pcmcia.c optional ata
mips/rmi/xls_ehci.c optional usb ehci
mips/rmi/bus_space_rmi.c standard
mips/rmi/bus_space_rmi_pci.c standard
mips/rmi/dev/sec/rmisec.c optional rmisec
mips/rmi/dev/sec/rmilib.c optional rmisec
mips/rmi/dev/nlge/if_nlge.c optional nlge
mips/rmi/dev/iic/max6657.c optional max6657
mips/rmi/dev/iic/at24co2n.c optional at24co2n

493
sys/mips/rmi/fmn.c
View File

@ -1,493 +0,0 @@
/*-
* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright (c) 2003-2009 RMI Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of RMI Corporation, nor the names of its contributors,
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* RMI_BSD */
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/types.h>
#include <sys/systm.h>
#include <sys/param.h>
#include <sys/lock.h>
#include <sys/mutex.h>
#include <sys/proc.h>
#include <sys/limits.h>
#include <sys/bus.h>
#include <sys/sbuf.h>
#include <sys/ktr.h>
#include <sys/kernel.h>
#include <sys/kthread.h>
#include <sys/resourcevar.h>
#include <sys/sched.h>
#include <sys/unistd.h>
#include <sys/sysctl.h>
#include <sys/malloc.h>
#include <machine/reg.h>
#include <machine/cpu.h>
#include <machine/hwfunc.h>
#include <machine/mips_opcode.h>
#include <machine/intr_machdep.h>
#include <mips/rmi/interrupt.h>
#include <mips/rmi/msgring.h>
#include <mips/rmi/pic.h>
#include <mips/rmi/board.h>
#define MSGRNG_CC_INIT_CPU_DEST(dest, counter) \
do { \
msgrng_write_cc(MSGRNG_CC_##dest##_REG, counter[dest][0], 0 ); \
msgrng_write_cc(MSGRNG_CC_##dest##_REG, counter[dest][1], 1 ); \
msgrng_write_cc(MSGRNG_CC_##dest##_REG, counter[dest][2], 2 ); \
msgrng_write_cc(MSGRNG_CC_##dest##_REG, counter[dest][3], 3 ); \
msgrng_write_cc(MSGRNG_CC_##dest##_REG, counter[dest][4], 4 ); \
msgrng_write_cc(MSGRNG_CC_##dest##_REG, counter[dest][5], 5 ); \
msgrng_write_cc(MSGRNG_CC_##dest##_REG, counter[dest][6], 6 ); \
msgrng_write_cc(MSGRNG_CC_##dest##_REG, counter[dest][7], 7 ); \
} while(0)
/*
* Keep track of our message ring handler threads, each core has a
* different message station. Ideally we will need to start a few
* message handling threads every core, and wake them up depending on
* load
*/
struct msgring_thread {
struct {
struct thread *thread; /* msgring handler threads */
int needed; /* thread needs to wake up */
} threads[XLR_NTHREADS];
int running; /* number of threads running */
int nthreads; /* number of threads started */
struct mtx lock; /* for changing running/active */
};
static struct msgring_thread msgring_threads[XLR_MAX_CORES];
static struct proc *msgring_proc; /* all threads are under a proc */
/*
* The maximum number of software message handler threads to be started
* per core. Default is 3 per core
*/
static int msgring_maxthreads = 3;
TUNABLE_INT("hw.fmn.maxthreads", &msgring_maxthreads);
/*
* The device drivers can register a handler for the messages sent
* from a station (corresponding to the device).
*/
struct tx_stn_handler {
msgring_handler action;
void *arg;
};
static struct tx_stn_handler msgmap[MSGRNG_NSTATIONS];
static struct mtx msgmap_lock;
/*
* Initialize the messaging subsystem.
*
* Message Stations are shared among all threads in a cpu core, this
* has to be called once from every core which is online.
*/
void
xlr_msgring_cpu_init(void)
{
struct stn_cc *cc_config;
struct bucket_size *bucket_sizes;
uint32_t flags;
int id;
KASSERT(xlr_thr_id() == 0,
("xlr_msgring_cpu_init from non-zero thread"));
id = xlr_core_id();
bucket_sizes = xlr_board_info.bucket_sizes;
cc_config = xlr_board_info.credit_configs[id];
flags = msgrng_access_enable();
/*
* FMN messages are received in 8 buckets per core, set up
* the bucket sizes for each bucket
*/
msgrng_write_bucksize(0, bucket_sizes->bucket[id * 8 + 0]);
msgrng_write_bucksize(1, bucket_sizes->bucket[id * 8 + 1]);
msgrng_write_bucksize(2, bucket_sizes->bucket[id * 8 + 2]);
msgrng_write_bucksize(3, bucket_sizes->bucket[id * 8 + 3]);
msgrng_write_bucksize(4, bucket_sizes->bucket[id * 8 + 4]);
msgrng_write_bucksize(5, bucket_sizes->bucket[id * 8 + 5]);
msgrng_write_bucksize(6, bucket_sizes->bucket[id * 8 + 6]);
msgrng_write_bucksize(7, bucket_sizes->bucket[id * 8 + 7]);
/*
* For sending FMN messages, we need credits on the destination
* bucket. Program the credits this core has on the 128 possible
* destination buckets.
* We cannot use a loop here, because the first argument has
* to be a constant integer value.
*/
MSGRNG_CC_INIT_CPU_DEST(0, cc_config->counters);
MSGRNG_CC_INIT_CPU_DEST(1, cc_config->counters);
MSGRNG_CC_INIT_CPU_DEST(2, cc_config->counters);
MSGRNG_CC_INIT_CPU_DEST(3, cc_config->counters);
MSGRNG_CC_INIT_CPU_DEST(4, cc_config->counters);
MSGRNG_CC_INIT_CPU_DEST(5, cc_config->counters);
MSGRNG_CC_INIT_CPU_DEST(6, cc_config->counters);
MSGRNG_CC_INIT_CPU_DEST(7, cc_config->counters);
MSGRNG_CC_INIT_CPU_DEST(8, cc_config->counters);
MSGRNG_CC_INIT_CPU_DEST(9, cc_config->counters);
MSGRNG_CC_INIT_CPU_DEST(10, cc_config->counters);
MSGRNG_CC_INIT_CPU_DEST(11, cc_config->counters);
MSGRNG_CC_INIT_CPU_DEST(12, cc_config->counters);
MSGRNG_CC_INIT_CPU_DEST(13, cc_config->counters);
MSGRNG_CC_INIT_CPU_DEST(14, cc_config->counters);
MSGRNG_CC_INIT_CPU_DEST(15, cc_config->counters);
msgrng_restore(flags);
}
/*
* Boot time init, called only once
*/
void
xlr_msgring_config(void)
{
mtx_init(&msgmap_lock, "msgring", NULL, MTX_SPIN);
/* check value */
if (msgring_maxthreads < 0 || msgring_maxthreads > XLR_NTHREADS)
msgring_maxthreads = XLR_NTHREADS;
}
/*
* Drain out max_messages for the buckets set in the bucket mask.
* Use max_messages = 0 to drain out all messages.
*/
uint32_t
xlr_msgring_handler(uint8_t bucket_mask, uint32_t max_messages)
{
int bucket = 0;
int size = 0, code = 0, rx_stid = 0;
struct msgrng_msg msg;
struct tx_stn_handler *he;
unsigned int status = 0;
unsigned long mflags;
uint32_t n_msgs;
uint32_t msgbuckets;
n_msgs = 0;
mflags = msgrng_access_enable();
for (;;) {
msgbuckets = (~msgrng_read_status() >> 24) & bucket_mask;
/* all buckets empty, break */
if (msgbuckets == 0)
break;
for (bucket = 0; bucket < 8; bucket++) {
if ((msgbuckets & (1 << bucket)) == 0) /* empty */
continue;
status = message_receive(bucket, &size, &code,
&rx_stid, &msg);
if (status != 0)
continue;
n_msgs++;
he = &msgmap[rx_stid];
if (he->action == NULL) {
printf("[%s]: No Handler for message from "
"stn_id=%d, bucket=%d, size=%d, msg0=%jx\n",
__func__, rx_stid, bucket, size,
(uintmax_t)msg.msg0);
} else {
msgrng_restore(mflags);
(*he->action)(bucket, size, code, rx_stid,
&msg, he->arg);
mflags = msgrng_access_enable();
}
if (max_messages > 0 && n_msgs >= max_messages)
goto done;
}
}
done:
msgrng_restore(mflags);
return (n_msgs);
}
/*
* XLR COP2 supports watermark interrupts based on the number of
* messages pending in all the buckets in the core. We increase
* the watermark until all the possible handler threads in the core
* are woken up.
*/
static void
msgrng_setconfig(int running, int nthr)
{
uint32_t config, mflags;
int watermark = 1; /* non zero needed */
int wm_intr_value;
KASSERT(nthr >= 0 && nthr <= msgring_maxthreads,
("Bad value of nthr %d", nthr));
KASSERT(running <= nthr, ("Bad value of running %d", running));
if (running == nthr) {
wm_intr_value = 0;
} else {
switch (running) {
case 0: break; /* keep default */
case 1:
watermark = 32; break;
case 2:
watermark = 48; break;
case 3:
watermark = 56; break;
}
wm_intr_value = 0x2; /* set watermark enable interrupt */
}
mflags = msgrng_access_enable();
config = (watermark << 24) | (IRQ_MSGRING << 16) | (1 << 8) |
wm_intr_value;
/* clear pending interrupts, they will get re-raised if still valid */
write_c0_eirr64(1ULL << IRQ_MSGRING);
msgrng_write_config(config);
msgrng_restore(mflags);
}
/* Debug counters */
static int msgring_nintr[XLR_MAX_CORES];
static int msgring_badintr[XLR_MAX_CORES];
static int msgring_wakeup_sleep[XLR_MAX_CORES * XLR_NTHREADS];
static int msgring_wakeup_nosleep[XLR_MAX_CORES * XLR_NTHREADS];
static int msgring_nmsgs[XLR_MAX_CORES * XLR_NTHREADS];
static int
msgring_process_fast_intr(void *arg)
{
struct msgring_thread *mthd;
struct thread *td;
uint32_t mflags;
int core, nt;
core = xlr_core_id();
mthd = &msgring_threads[core];
msgring_nintr[core]++;
mtx_lock_spin(&mthd->lock);
nt = mthd->running;
if(nt >= mthd->nthreads) {
msgring_badintr[core]++;
mtx_unlock_spin(&mthd->lock);
return (FILTER_HANDLED);
}
td = mthd->threads[nt].thread;
mflags = msgrng_access_enable();
/* default value with interrupts disabled */
msgrng_write_config((1 << 24) | (IRQ_MSGRING << 16) | (1 << 8));
/* clear pending interrupts */
write_c0_eirr64(1ULL << IRQ_MSGRING);
msgrng_restore(mflags);
mtx_unlock_spin(&mthd->lock);
/* wake up the target thread */
mthd->threads[nt].needed = 1;
thread_lock(td);
if (TD_AWAITING_INTR(td)) {
msgring_wakeup_sleep[core*4+nt]++;
TD_CLR_IWAIT(td);
sched_add(td, SRQ_INTR);
} else
msgring_wakeup_nosleep[core*4+nt]++;
thread_unlock(td);
return (FILTER_HANDLED);
}
static void
msgring_process(void *arg)
{
struct msgring_thread *mthd;
struct thread *td;
int hwtid, tid, core;
int nmsgs;
hwtid = (intptr_t)arg;
core = hwtid / 4;
tid = hwtid % 4;
mthd = &msgring_threads[core];
td = mthd->threads[tid].thread;
KASSERT(curthread == td,
("Incorrect thread core %d, thread %d", core, hwtid));
/* First bind this thread to the right CPU */
thread_lock(td);
sched_bind(td, xlr_hwtid_to_cpuid[hwtid]);
thread_unlock(td);
mtx_lock_spin(&mthd->lock);
++mthd->nthreads; /* Active thread count */
mtx_unlock_spin(&mthd->lock);
/* start processing messages */
for(;;) {
mtx_lock_spin(&mthd->lock);
++mthd->running;
msgrng_setconfig(mthd->running, mthd->nthreads);
mtx_unlock_spin(&mthd->lock);
atomic_store_rel_int(&mthd->threads[tid].needed, 0);
nmsgs = xlr_msgring_handler(0xff, 0);
msgring_nmsgs[hwtid] += nmsgs;
mtx_lock_spin(&mthd->lock);
--mthd->running;
msgrng_setconfig(mthd->running, mthd->nthreads);
mtx_unlock_spin(&mthd->lock);
/* sleep */
thread_lock(td);
if (mthd->threads[tid].needed) {
thread_unlock(td);
continue;
}
sched_class(td, PRI_ITHD);
TD_SET_IWAIT(td);
mi_switch(SW_VOL, NULL);
thread_unlock(td);
}
}
static void
create_msgring_thread(int hwtid)
{
struct msgring_thread *mthd;
struct thread *td;
int tid, core;
int error;
core = hwtid / 4;
tid = hwtid % 4;
mthd = &msgring_threads[core];
if (tid == 0) {
mtx_init(&mthd->lock, "msgrngcore", NULL, MTX_SPIN);
mthd->running = mthd->nthreads = 0;
}
error = kproc_kthread_add(msgring_process, (void *)(uintptr_t)hwtid,
&msgring_proc, &td, RFSTOPPED, 2, "msgrngproc",
"msgthr%d", hwtid);
if (error)
panic("kproc_kthread_add() failed with %d", error);
mthd->threads[tid].thread = td;
thread_lock(td);
sched_class(td, PRI_ITHD);
sched_add(td, SRQ_INTR);
thread_unlock(td);
CTR2(KTR_INTR, "%s: created %s", __func__, td->td_name);
}
int
register_msgring_handler(int startb, int endb, msgring_handler action,
void *arg)
{
void *cookie;
int i;
static int msgring_int_enabled = 0;
KASSERT(startb >= 0 && startb <= endb && endb < MSGRNG_NSTATIONS,
("Invalid value for for bucket range %d,%d", startb, endb));
mtx_lock_spin(&msgmap_lock);
for (i = startb; i <= endb; i++) {
KASSERT(msgmap[i].action == NULL,
("Bucket %d already used [action %p]", i, msgmap[i].action));
msgmap[i].action = action;
msgmap[i].arg = arg;
}
mtx_unlock_spin(&msgmap_lock);
if (xlr_test_and_set(&msgring_int_enabled)) {
create_msgring_thread(0);
if (msgring_maxthreads > xlr_threads_per_core)
msgring_maxthreads = xlr_threads_per_core;
cpu_establish_hardintr("msgring", msgring_process_fast_intr,
NULL, NULL, IRQ_MSGRING,
INTR_TYPE_NET, &cookie);
}
return (0);
}
/*
* Start message ring processing threads on other CPUs, after SMP start
*/
static void
start_msgring_threads(void *arg)
{
int hwt, tid;
for (hwt = 1; hwt < XLR_MAX_CORES * XLR_NTHREADS; hwt++) {
if ((xlr_hw_thread_mask & (1 << hwt)) == 0)
continue;
tid = hwt % XLR_NTHREADS;
if (tid >= msgring_maxthreads)
continue;
create_msgring_thread(hwt);
}
}
SYSINIT(start_msgring_threads, SI_SUB_SMP, SI_ORDER_MIDDLE,
start_msgring_threads, NULL);
/*
* DEBUG support, XXX: static buffer, not locked
*/
static int
sys_print_debug(SYSCTL_HANDLER_ARGS)
{
struct sbuf sb;
int error, i;
sbuf_new_for_sysctl(&sb, NULL, 64, req);
sbuf_printf(&sb,
"\nID INTR ER WU-SLP WU-ERR MSGS\n");
for (i = 0; i < 32; i++) {
if ((xlr_hw_thread_mask & (1 << i)) == 0)
continue;
sbuf_printf(&sb, "%2d: %8d %4d %8d %8d %8d\n", i,
msgring_nintr[i/4], msgring_badintr[i/4],
msgring_wakeup_sleep[i], msgring_wakeup_nosleep[i],
msgring_nmsgs[i]);
}
error = sbuf_finish(&sb);
sbuf_delete(&sb);
return (error);
}
SYSCTL_PROC(_debug, OID_AUTO, msgring, CTLTYPE_STRING | CTLFLAG_RD, 0, 0,
sys_print_debug, "A", "msgring debug info");

52
sys/mips/rmi/interrupt.h
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@ -1,52 +0,0 @@
/*-
* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright (c) 2003-2009 RMI Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of RMI Corporation, nor the names of its contributors,
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* RMI_BSD
* $FreeBSD$
*/
#ifndef _RMI_INTERRUPT_H_
#define _RMI_INTERRUPT_H_
/* Defines for the IRQ numbers */
#define IRQ_IPI 41 /* 8-39 are mapped by PIC intr 0-31 */
#define IRQ_MSGRING 6
#define IRQ_TIMER 7
/*
* XLR needs custom pre and post handlers for PCI/PCI-e interrupts
* XXX: maybe follow i386 intsrc model
*/
void xlr_establish_intr(const char *name, driver_filter_t filt,
driver_intr_t handler, void *arg, int irq, int flags,
void **cookiep, void (*busack)(int));
void xlr_enable_irq(int irq);
#endif /* _RMI_INTERRUPT_H_ */

251
sys/mips/rmi/intr_machdep.c
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@ -1,251 +0,0 @@
/*-
* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
*
* Copyright (c) 2006-2009 RMI Corporation
* Copyright (c) 2002-2004 Juli Mallett <jmallett@FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions, and the following disclaimer,
* without modification, immediately at the beginning of the file.
* 2. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/interrupt.h>
#include <sys/kernel.h>
#include <machine/cpu.h>
#include <machine/cpufunc.h>
#include <machine/cpuinfo.h>
#include <machine/cpuregs.h>
#include <machine/frame.h>
#include <machine/intr_machdep.h>
#include <machine/md_var.h>
#include <machine/trap.h>
#include <machine/hwfunc.h>
#include <mips/rmi/rmi_mips_exts.h>
#include <mips/rmi/interrupt.h>
#include <mips/rmi/pic.h>
struct xlr_intrsrc {
void (*busack)(int); /* Additional ack */
struct intr_event *ie; /* event corresponding to intr */
int irq;
};
static struct xlr_intrsrc xlr_interrupts[XLR_MAX_INTR];
static mips_intrcnt_t mips_intr_counters[XLR_MAX_INTR];
static int intrcnt_index;
void
xlr_enable_irq(int irq)
{
uint64_t eimr;
eimr = read_c0_eimr64();
write_c0_eimr64(eimr | (1ULL << irq));
}
void
cpu_establish_softintr(const char *name, driver_filter_t * filt,
void (*handler) (void *), void *arg, int irq, int flags,
void **cookiep)
{
panic("Soft interrupts unsupported!\n");
}
void
cpu_establish_hardintr(const char *name, driver_filter_t * filt,
void (*handler) (void *), void *arg, int irq, int flags,
void **cookiep)
{
xlr_establish_intr(name, filt, handler, arg, irq, flags,
cookiep, NULL);
}
static void
xlr_post_filter(void *source)
{
struct xlr_intrsrc *src = source;
if (src->busack)
src->busack(src->irq);
pic_ack(PIC_IRQ_TO_INTR(src->irq));
}
static void
xlr_pre_ithread(void *source)
{
struct xlr_intrsrc *src = source;
if (src->busack)
src->busack(src->irq);
}
static void
xlr_post_ithread(void *source)
{
struct xlr_intrsrc *src = source;
pic_ack(PIC_IRQ_TO_INTR(src->irq));
}
void
xlr_establish_intr(const char *name, driver_filter_t filt,
driver_intr_t handler, void *arg, int irq, int flags,
void **cookiep, void (*busack)(int))
{
struct intr_event *ie; /* descriptor for the IRQ */
struct xlr_intrsrc *src = NULL;
int errcode;
if (irq < 0 || irq > XLR_MAX_INTR)
panic("%s called for unknown hard intr %d", __func__, irq);
/*
* FIXME locking - not needed now, because we do this only on
* startup from CPU0
*/
src = &xlr_interrupts[irq];
ie = src->ie;
if (ie == NULL) {
/*
* PIC based interrupts need ack in PIC, and some SoC
* components need additional acks (e.g. PCI)
*/
if (PIC_IRQ_IS_PICINTR(irq))
errcode = intr_event_create(&ie, src, 0, irq,
xlr_pre_ithread, xlr_post_ithread, xlr_post_filter,
NULL, "hard intr%d:", irq);
else {
if (filt == NULL)
panic("Not supported - non filter percpu intr");
errcode = intr_event_create(&ie, src, 0, irq,
NULL, NULL, NULL, NULL, "hard intr%d:", irq);
}
if (errcode) {
printf("Could not create event for intr %d\n", irq);
return;
}
src->irq = irq;
src->busack = busack;
src->ie = ie;
}
intr_event_add_handler(ie, name, filt, handler, arg,
intr_priority(flags), flags, cookiep);
xlr_enable_irq(irq);
}
void
cpu_intr(struct trapframe *tf)
{
struct intr_event *ie;
uint64_t eirr, eimr;
int i;
critical_enter();
/* find a list of enabled interrupts */
eirr = read_c0_eirr64();
eimr = read_c0_eimr64();
eirr &= eimr;
if (eirr == 0) {
critical_exit();
return;
}
/*
* No need to clear the EIRR here as the handler writes to
* compare which ACKs the interrupt.
*/
if (eirr & (1 << IRQ_TIMER)) {
intr_event_handle(xlr_interrupts[IRQ_TIMER].ie, tf);
critical_exit();
return;
}
/* FIXME sched pin >? LOCK>? */
for (i = sizeof(eirr) * 8 - 1; i >= 0; i--) {
if ((eirr & (1ULL << i)) == 0)
continue;
ie = xlr_interrupts[i].ie;
/* Don't account special IRQs */
switch (i) {
case IRQ_IPI:
case IRQ_MSGRING:
break;
default:
mips_intrcnt_inc(mips_intr_counters[i]);
}
/* Ack the IRQ on the CPU */
write_c0_eirr64(1ULL << i);
if (intr_event_handle(ie, tf) != 0) {
printf("stray interrupt %d\n", i);
}
}
critical_exit();
}
void
mips_intrcnt_setname(mips_intrcnt_t counter, const char *name)
{
int idx = counter - intrcnt;
KASSERT(counter != NULL, ("mips_intrcnt_setname: NULL counter"));
snprintf(intrnames + (MAXCOMLEN + 1) * idx,
MAXCOMLEN + 1, "%-*s", MAXCOMLEN, name);
}
mips_intrcnt_t
mips_intrcnt_create(const char* name)
{
mips_intrcnt_t counter = &intrcnt[intrcnt_index++];
mips_intrcnt_setname(counter, name);
return counter;
}
void
cpu_init_interrupts()
{
int i;
char name[MAXCOMLEN + 1];
/*
* Initialize all available vectors so spare IRQ
* would show up in systat output
*/
for (i = 0; i < XLR_MAX_INTR; i++) {
snprintf(name, MAXCOMLEN + 1, "int%d:", i);
mips_intr_counters[i] = mips_intrcnt_create(name);
}
}

277
sys/mips/rmi/iodi.c
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@ -1,277 +0,0 @@
/*-
* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright (c) 2003-2009 RMI Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of RMI Corporation, nor the names of its contributors,
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* RMI_BSD
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#define __RMAN_RESOURCE_VISIBLE
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/kernel.h>
#include <sys/lock.h>
#include <sys/mutex.h>
#include <sys/reboot.h>
#include <sys/rman.h>
#include <sys/types.h>
#include <sys/malloc.h>
#include <sys/interrupt.h>
#include <sys/module.h>
#include <machine/cpu.h>
#include <machine/bus.h>
#include <machine/intr_machdep.h>
#include <machine/clock.h> /* for DELAY */
#include <machine/resource.h>
#include <mips/rmi/board.h>
#include <mips/rmi/pic.h>
#include <mips/rmi/interrupt.h>
#include <mips/rmi/msgring.h>
#include <mips/rmi/iomap.h>
#include <mips/rmi/rmi_mips_exts.h>
#include <mips/rmi/dev/xlr/atx_cpld.h>
#include <mips/rmi/dev/xlr/xgmac_mdio.h>
extern bus_space_tag_t uart_bus_space_mem;
static struct resource *
iodi_alloc_resource(device_t, device_t, int, int *,
rman_res_t, rman_res_t, rman_res_t, u_int);
static int
iodi_activate_resource(device_t, device_t, int, int,
struct resource *);
static int
iodi_setup_intr(device_t, device_t, struct resource *, int,
driver_filter_t *, driver_intr_t *, void *, void **);
struct iodi_softc *iodi_softc; /* There can be only one. */
/*
* We will manage the Flash/PCMCIA devices in IODI for now.
* The NOR flash, Compact flash etc. which can be connected on
* various chip selects on the peripheral IO, should have a
* separate bus later.
*/
static void
bridge_pcmcia_ack(int irq)
{
xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_FLASH_OFFSET);
xlr_write_reg(mmio, 0x60, 0xffffffff);
}
static int
iodi_setup_intr(device_t dev, device_t child,
struct resource *ires, int flags, driver_filter_t *filt,
driver_intr_t *intr, void *arg, void **cookiep)
{
const char *name = device_get_name(child);
if (strcmp(name, "uart") == 0) {
/* FIXME uart 1? */
cpu_establish_hardintr("uart", filt, intr, arg,
PIC_UART_0_IRQ, flags, cookiep);
pic_setup_intr(PIC_IRT_UART_0_INDEX, PIC_UART_0_IRQ, 0x1, 1);
} else if (strcmp(name, "nlge") == 0) {
int irq;
/* This is a hack to pass in the irq */
irq = (intptr_t)ires->__r_i;
cpu_establish_hardintr("nlge", filt, intr, arg, irq, flags,
cookiep);
pic_setup_intr(irq - PIC_IRQ_BASE, irq, 0x1, 1);
} else if (strcmp(name, "ehci") == 0) {
cpu_establish_hardintr("ehci", filt, intr, arg, PIC_USB_IRQ, flags,
cookiep);
pic_setup_intr(PIC_USB_IRQ - PIC_IRQ_BASE, PIC_USB_IRQ, 0x1, 1);
} else if (strcmp(name, "ata") == 0) {
xlr_establish_intr("ata", filt, intr, arg, PIC_PCMCIA_IRQ, flags,
cookiep, bridge_pcmcia_ack);
pic_setup_intr(PIC_PCMCIA_IRQ - PIC_IRQ_BASE, PIC_PCMCIA_IRQ, 0x1, 1);
}
return (0);
}
static struct resource *
iodi_alloc_resource(device_t bus, device_t child, int type, int *rid,
rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
{
struct resource *res = malloc(sizeof(*res), M_DEVBUF, M_WAITOK);
const char *name = device_get_name(child);
int unit;
#ifdef DEBUG
switch (type) {
case SYS_RES_IRQ:
device_printf(bus, "IRQ resource - for %s %jx-%jx\n",
device_get_nameunit(child), start, end);
break;
case SYS_RES_IOPORT:
device_printf(bus, "IOPORT resource - for %s %jx-%jx\n",
device_get_nameunit(child), start, end);
break;
case SYS_RES_MEMORY:
device_printf(bus, "MEMORY resource - for %s %jx-%jx\n",
device_get_nameunit(child), start, end);
break;
}
#endif
if (strcmp(name, "uart") == 0) {
if ((unit = device_get_unit(child)) == 0) { /* uart 0 */
res->r_bushandle = (xlr_io_base + XLR_IO_UART_0_OFFSET);
} else if (unit == 1) {
res->r_bushandle = (xlr_io_base + XLR_IO_UART_1_OFFSET);
} else
printf("%s: Unknown uart unit\n", __FUNCTION__);
res->r_bustag = uart_bus_space_mem;
} else if (strcmp(name, "ehci") == 0) {
res->r_bushandle = MIPS_PHYS_TO_KSEG1(0x1ef24000);
res->r_bustag = rmi_pci_bus_space;
} else if (strcmp(name, "cfi") == 0) {
res->r_bushandle = MIPS_PHYS_TO_KSEG1(0x1c000000);
res->r_bustag = 0;
} else if (strcmp(name, "ata") == 0) {
res->r_bushandle = MIPS_PHYS_TO_KSEG1(0x1d000000);
res->r_bustag = rmi_pci_bus_space; /* byte swapping (not really PCI) */
}
/* res->r_start = *rid; */
return (res);
}
static int
iodi_activate_resource(device_t bus, device_t child, int type, int rid,
struct resource *r)
{
return (0);
}
/* prototypes */
static int iodi_probe(device_t);
static int iodi_attach(device_t);
static int iodi_detach(device_t);
static void iodi_identify(driver_t *, device_t);
int
iodi_probe(device_t dev)
{
return (BUS_PROBE_NOWILDCARD);
}
void
iodi_identify(driver_t * driver, device_t parent)
{
BUS_ADD_CHILD(parent, 0, "iodi", 0);
}
int
iodi_attach(device_t dev)
{
device_t tmpd;
int i;
/*
* Attach each devices
*/
device_add_child(dev, "uart", 0);
device_add_child(dev, "xlr_i2c", 0);
device_add_child(dev, "xlr_i2c", 1);
device_add_child(dev, "pcib", 0);
device_add_child(dev, "rmisec", -1);
if (xlr_board_info.usb)
device_add_child(dev, "ehci", 0);
if (xlr_board_info.cfi)
device_add_child(dev, "cfi", 0);
if (xlr_board_info.ata)
device_add_child(dev, "ata", 0);
for (i = 0; i < 3; i++) {
if (xlr_board_info.gmac_block[i].enabled == 0)
continue;
tmpd = device_add_child(dev, "nlna", i);
device_set_ivars(tmpd, &xlr_board_info.gmac_block[i]);
}
bus_generic_probe(dev);
bus_generic_attach(dev);
return 0;
}
int
iodi_detach(device_t dev)
{
device_t nlna_dev;
int error, i, ret;
error = 0;
ret = 0;
for (i = 0; i < 3; i++) {
nlna_dev = device_find_child(dev, "nlna", i);
if (nlna_dev != NULL)
error = bus_generic_detach(nlna_dev);
if (error)
ret = error;
}
return ret;
}
static device_method_t iodi_methods[] = {
DEVMETHOD(device_probe, iodi_probe),
DEVMETHOD(device_attach, iodi_attach),
DEVMETHOD(device_detach, iodi_detach),
DEVMETHOD(device_identify, iodi_identify),
DEVMETHOD(bus_alloc_resource, iodi_alloc_resource),
DEVMETHOD(bus_activate_resource, iodi_activate_resource),
DEVMETHOD(bus_add_child, bus_generic_add_child),
DEVMETHOD(bus_setup_intr, iodi_setup_intr),
{0, 0},
};
static driver_t iodi_driver = {
"iodi",
iodi_methods,
1 /* no softc */
};
static devclass_t iodi_devclass;
DRIVER_MODULE(iodi, nexus, iodi_driver, iodi_devclass, 0, 0);

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sys/mips/rmi/iomap.h
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/*-
* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright (c) 2003-2009 RMI Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of RMI Corporation, nor the names of its contributors,
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* RMI_BSD
* $FreeBSD$
*/
#ifndef _RMI_IOMAP_H_
#define _RMI_IOMAP_H_
#include <machine/endian.h>
#define XLR_DEVICE_REGISTER_BASE 0x1EF00000
#define DEFAULT_XLR_IO_BASE 0xffffffffbef00000ULL
#define XLR_IO_SIZE 0x1000
#define XLR_IO_BRIDGE_OFFSET 0x00000
#define XLR_IO_DDR2_CHN0_OFFSET 0x01000
#define XLR_IO_DDR2_CHN1_OFFSET 0x02000
#define XLR_IO_DDR2_CHN2_OFFSET 0x03000
#define XLR_IO_DDR2_CHN3_OFFSET 0x04000
#define XLR_IO_RLD2_CHN0_OFFSET 0x05000
#define XLR_IO_RLD2_CHN1_OFFSET 0x06000
#define XLR_IO_SRAM_OFFSET 0x07000
#define XLR_IO_PIC_OFFSET 0x08000
#define XLR_IO_PCIX_OFFSET 0x09000
#define XLR_IO_HT_OFFSET 0x0A000
#define XLR_IO_SECURITY_OFFSET 0x0B000
#define XLR_IO_GMAC_0_OFFSET 0x0C000
#define XLR_IO_GMAC_1_OFFSET 0x0D000
#define XLR_IO_GMAC_2_OFFSET 0x0E000
#define XLR_IO_GMAC_3_OFFSET 0x0F000
#define XLR_IO_SPI4_0_OFFSET 0x10000
#define XLR_IO_XGMAC_0_OFFSET 0x11000
#define XLR_IO_SPI4_1_OFFSET 0x12000
#define XLR_IO_XGMAC_1_OFFSET 0x13000
#define XLR_IO_UART_0_OFFSET 0x14000
#define XLR_IO_UART_1_OFFSET 0x15000
#define XLR_UART0ADDR (XLR_IO_UART_0_OFFSET+XLR_DEVICE_REGISTER_BASE)
#define XLR_IO_I2C_0_OFFSET 0x16000
#define XLR_IO_I2C_1_OFFSET 0x17000
#define XLR_IO_GPIO_OFFSET 0x18000
#define XLR_IO_FLASH_OFFSET 0x19000
#define XLR_IO_TB_OFFSET 0x1C000
#define XLR_IO_GMAC_4_OFFSET 0x20000
#define XLR_IO_GMAC_5_OFFSET 0x21000
#define XLR_IO_GMAC_6_OFFSET 0x22000
#define XLR_IO_GMAC_7_OFFSET 0x23000
#define XLR_IO_PCIE_0_OFFSET 0x1E000
#define XLR_IO_PCIE_1_OFFSET 0x1F000
#define XLR_IO_USB_0_OFFSET 0x24000
#define XLR_IO_USB_1_OFFSET 0x25000
#define XLR_IO_COMP_OFFSET 0x1d000
/* Base Address (Virtual) of the PCI Config address space
* For now, choose 256M phys in kseg1 = 0xA0000000 + (1<<28)
* Config space spans 256 (num of buses) * 256 (num functions) * 256 bytes
* ie 1<<24 = 16M
*/
#define DEFAULT_PCI_CONFIG_BASE 0x18000000
#define DEFAULT_HT_TYPE0_CFG_BASE 0x16000000
#define DEFAULT_HT_TYPE1_CFG_BASE 0x17000000
typedef volatile __uint32_t xlr_reg_t;
extern unsigned long xlr_io_base;
#define xlr_io_mmio(offset) ((xlr_reg_t *)(xlr_io_base+(offset)))
#define xlr_read_reg(base, offset) (__ntohl((base)[(offset)]))
#define xlr_write_reg(base, offset, value) ((base)[(offset)] = __htonl((value)))
extern void on_chip_init(void);
#endif /* _RMI_IOMAP_H_ */

68
sys/mips/rmi/mpwait.S
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@ -1,68 +0,0 @@
/*-
* Copyright (c) 2010 RMI Technologies Ltd.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#include <machine/asm.h>
#include <machine/cpu.h>
#include <machine/cpuregs.h>
#include "assym.s"
.text
.set noat
.set noreorder
/*
* On XLR the slave processors and threads will be executing boot
* loader code on startup. We need to make them run our code before
* blowing away boot loader memory.
*/
LEAF(mpwait)
PTR_LA gp, _C_LABEL(_gp)
PTR_LA t1, _C_LABEL(xlr_ap_release)
mfc0 t2, $15, 1
andi t2, 0x1f
sll t2, t2, 2
add t1, t2
1: lw t0, 0(t1)
bnez t0, 2f
nop /* We should not busy wait in core0 threads */
nop /* on bootup, this will slow the cpu0 thread */
nop /* down - TODO - wait with IPI based wakeup */
nop
nop
nop
nop
nop
j 1b
nop
2:
PTR_LA t1, _C_LABEL(mpentry)
jr t1
nop
END(mpwait)

320
sys/mips/rmi/msgring.c
View File

@ -1,320 +0,0 @@
/*-
* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright (c) 2003-2009 RMI Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of RMI Corporation, nor the names of its contributors,
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
* RMI_BSD */
/**********************************************************
* -----------------DO NOT EDIT THIS FILE------------------
* This file has been autogenerated by the build process
* from "msgring.cfg"
**********************************************************/
#include <mips/rmi/msgring.h>
struct bucket_size bucket_sizes = {
{
32, 32, 32, 32, 32, 32, 32, 32,
32, 32, 32, 32, 32, 32, 32, 32,
32, 32, 32, 32, 32, 32, 32, 32,
32, 32, 32, 32, 32, 32, 32, 32,
32, 32, 32, 32, 32, 32, 32, 32,
32, 32, 32, 32, 32, 32, 32, 32,
32, 32, 32, 32, 32, 32, 32, 32,
32, 32, 32, 32, 32, 32, 32, 32,
32, 16, 16, 16, 16, 16, 16, 16,
16, 16, 16, 16, 16, 16, 16, 0,
32, 16, 16, 16, 16, 16, 16, 16,
16, 16, 16, 16, 16, 16, 16, 0,
0, 32, 32, 32, 32, 32, 0, 32,
0, 0, 0, 0, 0, 0, 0, 0,
0, 32, 0, 32, 0, 0, 0, 0,
128, 0, 0, 0, 128, 0, 0, 0,
}
};
struct stn_cc cc_table_cpu_0 = {{
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 4, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{4, 2, 2, 2, 2, 2, 2, 2},
{2, 2, 2, 2, 2, 2, 2, 0},
{4, 2, 2, 2, 2, 2, 2, 2},
{2, 2, 2, 2, 2, 2, 2, 0},
{0, 2, 4, 4, 4, 4, 0, 2},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 2, 0, 2, 0, 0, 0, 0},
{16, 0, 0, 0, 16, 0, 0, 0},
}};
struct stn_cc cc_table_cpu_1 = {{
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{4, 2, 2, 2, 2, 2, 2, 2},
{2, 2, 2, 2, 2, 2, 2, 0},
{4, 2, 2, 2, 2, 2, 2, 2},
{2, 2, 2, 2, 2, 2, 2, 0},
{0, 2, 4, 4, 4, 4, 0, 2},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 2, 0, 2, 0, 0, 0, 0},
{16, 0, 0, 0, 16, 0, 0, 0},
}};
struct stn_cc cc_table_cpu_2 = {{
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{4, 2, 2, 2, 2, 2, 2, 2},
{2, 2, 2, 2, 2, 2, 2, 0},
{4, 2, 2, 2, 2, 2, 2, 2},
{2, 2, 2, 2, 2, 2, 2, 0},
{0, 4, 4, 4, 4, 4, 0, 4},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 4, 0, 4, 0, 0, 0, 0},
{16, 0, 0, 0, 16, 0, 0, 0},
}};
struct stn_cc cc_table_cpu_3 = {{
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{4, 2, 2, 2, 2, 2, 2, 2},
{2, 2, 2, 2, 2, 2, 2, 0},
{4, 2, 2, 2, 2, 2, 2, 2},
{2, 2, 2, 2, 2, 2, 2, 0},
{0, 4, 4, 4, 4, 4, 0, 4},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 4, 0, 4, 0, 0, 0, 0},
{16, 0, 0, 0, 16, 0, 0, 0},
}};
struct stn_cc cc_table_cpu_4 = {{
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{4, 2, 2, 2, 2, 2, 2, 2},
{2, 2, 2, 2, 2, 2, 2, 0},
{4, 2, 2, 2, 2, 2, 2, 2},
{2, 2, 2, 2, 2, 2, 2, 0},
{0, 4, 4, 4, 4, 4, 0, 4},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 4, 0, 4, 0, 0, 0, 0},
{16, 0, 0, 0, 16, 0, 0, 0},
}};
struct stn_cc cc_table_cpu_5 = {{
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{4, 2, 2, 2, 2, 2, 2, 2},
{2, 2, 2, 2, 2, 2, 2, 0},
{4, 2, 2, 2, 2, 2, 2, 2},
{2, 2, 2, 2, 2, 2, 2, 0},
{0, 4, 4, 4, 4, 4, 0, 4},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 4, 0, 4, 0, 0, 0, 0},
{16, 0, 0, 0, 16, 0, 0, 0},
}};
struct stn_cc cc_table_cpu_6 = {{
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{4, 2, 2, 2, 2, 2, 2, 2},
{2, 2, 2, 2, 2, 2, 2, 0},
{4, 2, 2, 2, 2, 2, 2, 2},
{2, 2, 2, 2, 2, 2, 2, 0},
{0, 4, 4, 4, 4, 4, 0, 4},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 4, 0, 4, 0, 0, 0, 0},
{16, 0, 0, 0, 16, 0, 0, 0},
}};
struct stn_cc cc_table_cpu_7 = {{
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{4, 2, 2, 2, 2, 2, 2, 2},
{2, 2, 2, 2, 2, 2, 2, 0},
{4, 2, 2, 2, 2, 2, 2, 2},
{2, 2, 2, 2, 2, 2, 2, 0},
{0, 4, 4, 4, 4, 4, 0, 4},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 4, 0, 4, 0, 0, 0, 0},
{16, 0, 0, 0, 16, 0, 0, 0},
}};
struct stn_cc cc_table_xgs_0 = {{
{8, 8, 8, 8, 8, 8, 8, 8},
{8, 8, 8, 8, 8, 8, 8, 8},
{8, 8, 8, 8, 8, 8, 8, 8},
{8, 8, 8, 8, 8, 8, 8, 8},
{8, 8, 8, 8, 8, 8, 8, 8},
{8, 8, 8, 8, 8, 8, 8, 8},
{8, 8, 8, 8, 8, 8, 8, 8},
{8, 8, 8, 8, 8, 8, 8, 8},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 4, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
}};
struct stn_cc cc_table_xgs_1 = {{
{8, 8, 8, 8, 8, 8, 8, 8},
{8, 8, 8, 8, 8, 8, 8, 8},
{8, 8, 8, 8, 8, 8, 8, 8},
{8, 8, 8, 8, 8, 8, 8, 8},
{8, 8, 8, 8, 8, 8, 8, 8},
{8, 8, 8, 8, 8, 8, 8, 8},
{8, 8, 8, 8, 8, 8, 8, 8},
{8, 8, 8, 8, 8, 8, 8, 8},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 4, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
}};
struct stn_cc cc_table_gmac = {{
{8, 8, 8, 8, 16, 16, 16, 16},
{8, 8, 8, 8, 16, 16, 16, 16},
{8, 8, 8, 8, 16, 16, 16, 16},
{8, 8, 8, 8, 16, 16, 16, 16},
{8, 8, 8, 8, 16, 16, 16, 16},
{8, 8, 8, 8, 16, 16, 16, 16},
{8, 8, 8, 8, 16, 16, 16, 16},
{8, 8, 8, 8, 16, 16, 16, 16},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 4, 0, 0, 0, 0, 0, 4},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
}};
struct stn_cc cc_table_dma = {{
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
}};
struct stn_cc cc_table_sec = {{
{8, 8, 8, 8, 0, 0, 0, 0},
{8, 8, 8, 4, 0, 0, 0, 0},
{8, 8, 8, 8, 0, 0, 0, 0},
{8, 8, 8, 8, 0, 0, 0, 0},
{8, 8, 8, 8, 0, 0, 0, 0},
{8, 8, 8, 8, 0, 0, 0, 0},
{8, 8, 8, 8, 0, 0, 0, 0},
{8, 8, 8, 8, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
}};

1185
sys/mips/rmi/msgring.cfg
View File

File diff suppressed because it is too large Load Diff

372
sys/mips/rmi/msgring.h
View File

@ -1,372 +0,0 @@
/*-
* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright (c) 2003-2009 RMI Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of RMI Corporation, nor the names of its contributors,
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* RMI_BSD
* $FreeBSD$
*/
#ifndef _RMI_MSGRING_H_
#define _RMI_MSGRING_H_
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/types.h>
#include <machine/cpuregs.h>
#include <machine/cpufunc.h>
#include <mips/rmi/rmi_mips_exts.h>
#define MSGRNG_TX_BUF_REG 0
#define MSGRNG_RX_BUF_REG 1
#define MSGRNG_MSG_STATUS_REG 2
#define MSGRNG_MSG_CONFIG_REG 3
#define MSGRNG_MSG_BUCKSIZE_REG 4
#define MSGRNG_CC_0_REG 16
#define MSGRNG_CC_1_REG 17
#define MSGRNG_CC_2_REG 18
#define MSGRNG_CC_3_REG 19
#define MSGRNG_CC_4_REG 20
#define MSGRNG_CC_5_REG 21
#define MSGRNG_CC_6_REG 22
#define MSGRNG_CC_7_REG 23
#define MSGRNG_CC_8_REG 24
#define MSGRNG_CC_9_REG 25
#define MSGRNG_CC_10_REG 26
#define MSGRNG_CC_11_REG 27
#define MSGRNG_CC_12_REG 28
#define MSGRNG_CC_13_REG 29
#define MSGRNG_CC_14_REG 30
#define MSGRNG_CC_15_REG 31
/* Station IDs */
#define MSGRNG_STNID_CPU0 0x00
#define MSGRNG_STNID_CPU1 0x08
#define MSGRNG_STNID_CPU2 0x10
#define MSGRNG_STNID_CPU3 0x18
#define MSGRNG_STNID_CPU4 0x20
#define MSGRNG_STNID_CPU5 0x28
#define MSGRNG_STNID_CPU6 0x30
#define MSGRNG_STNID_CPU7 0x38
#define MSGRNG_STNID_XGS0_TX 64
#define MSGRNG_STNID_XMAC0_00_TX 64
#define MSGRNG_STNID_XMAC0_01_TX 65
#define MSGRNG_STNID_XMAC0_02_TX 66
#define MSGRNG_STNID_XMAC0_03_TX 67
#define MSGRNG_STNID_XMAC0_04_TX 68
#define MSGRNG_STNID_XMAC0_05_TX 69
#define MSGRNG_STNID_XMAC0_06_TX 70
#define MSGRNG_STNID_XMAC0_07_TX 71
#define MSGRNG_STNID_XMAC0_08_TX 72
#define MSGRNG_STNID_XMAC0_09_TX 73
#define MSGRNG_STNID_XMAC0_10_TX 74
#define MSGRNG_STNID_XMAC0_11_TX 75
#define MSGRNG_STNID_XMAC0_12_TX 76
#define MSGRNG_STNID_XMAC0_13_TX 77
#define MSGRNG_STNID_XMAC0_14_TX 78
#define MSGRNG_STNID_XMAC0_15_TX 79
#define MSGRNG_STNID_XGS1_TX 80
#define MSGRNG_STNID_XMAC1_00_TX 80
#define MSGRNG_STNID_XMAC1_01_TX 81
#define MSGRNG_STNID_XMAC1_02_TX 82
#define MSGRNG_STNID_XMAC1_03_TX 83
#define MSGRNG_STNID_XMAC1_04_TX 84
#define MSGRNG_STNID_XMAC1_05_TX 85
#define MSGRNG_STNID_XMAC1_06_TX 86
#define MSGRNG_STNID_XMAC1_07_TX 87
#define MSGRNG_STNID_XMAC1_08_TX 88
#define MSGRNG_STNID_XMAC1_09_TX 89
#define MSGRNG_STNID_XMAC1_10_TX 90
#define MSGRNG_STNID_XMAC1_11_TX 91
#define MSGRNG_STNID_XMAC1_12_TX 92
#define MSGRNG_STNID_XMAC1_13_TX 93
#define MSGRNG_STNID_XMAC1_14_TX 94
#define MSGRNG_STNID_XMAC1_15_TX 95
#define MSGRNG_STNID_GMAC 96
#define MSGRNG_STNID_GMACJFR_0 96
#define MSGRNG_STNID_GMACRFR_0 97
#define MSGRNG_STNID_GMACTX0 98
#define MSGRNG_STNID_GMACTX1 99
#define MSGRNG_STNID_GMACTX2 100
#define MSGRNG_STNID_GMACTX3 101
#define MSGRNG_STNID_GMACJFR_1 102
#define MSGRNG_STNID_GMACRFR_1 103
#define MSGRNG_STNID_DMA 104
#define MSGRNG_STNID_DMA_0 104
#define MSGRNG_STNID_DMA_1 105
#define MSGRNG_STNID_DMA_2 106
#define MSGRNG_STNID_DMA_3 107
#define MSGRNG_STNID_XGS0FR 112
#define MSGRNG_STNID_XMAC0JFR 112
#define MSGRNG_STNID_XMAC0RFR 113
#define MSGRNG_STNID_XGS1FR 114
#define MSGRNG_STNID_XMAC1JFR 114
#define MSGRNG_STNID_XMAC1RFR 115
#define MSGRNG_STNID_SEC 120
#define MSGRNG_STNID_SEC0 120
#define MSGRNG_STNID_SEC1 121
#define MSGRNG_STNID_SEC2 122
#define MSGRNG_STNID_SEC3 123
#define MSGRNG_STNID_PK0 124
#define MSGRNG_STNID_SEC_RSA 124
#define MSGRNG_STNID_SEC_RSVD0 125
#define MSGRNG_STNID_SEC_RSVD1 126
#define MSGRNG_STNID_SEC_RSVD2 127
#define MSGRNG_STNID_GMAC1 80
#define MSGRNG_STNID_GMAC1_FR_0 81
#define MSGRNG_STNID_GMAC1_TX0 82
#define MSGRNG_STNID_GMAC1_TX1 83
#define MSGRNG_STNID_GMAC1_TX2 84
#define MSGRNG_STNID_GMAC1_TX3 85
#define MSGRNG_STNID_GMAC1_FR_1 87
#define MSGRNG_STNID_GMAC0 96
#define MSGRNG_STNID_GMAC0_FR_0 97
#define MSGRNG_STNID_GMAC0_TX0 98
#define MSGRNG_STNID_GMAC0_TX1 99
#define MSGRNG_STNID_GMAC0_TX2 100
#define MSGRNG_STNID_GMAC0_TX3 101
#define MSGRNG_STNID_GMAC0_FR_1 103
#define MSGRNG_STNID_CMP_0 108
#define MSGRNG_STNID_CMP_1 109
#define MSGRNG_STNID_CMP_2 110
#define MSGRNG_STNID_CMP_3 111
#define MSGRNG_STNID_PCIE_0 116
#define MSGRNG_STNID_PCIE_1 117
#define MSGRNG_STNID_PCIE_2 118
#define MSGRNG_STNID_PCIE_3 119
#define MSGRNG_STNID_XLS_PK0 121
#define MSGRNG_CODE_MAC 0
#define MSGRNG_CODE_XGMAC 2
#define MSGRNG_CODE_SEC 0
#define MSGRNG_CODE_BOOT_WAKEUP 200
#define MSGRNG_CODE_SPI4 3
#define msgrng_read_status() read_c2_register32(MSGRNG_MSG_STATUS_REG, 0)
#define msgrng_read_config() read_c2_register32(MSGRNG_MSG_CONFIG_REG, 0)
#define msgrng_write_config(v) write_c2_register32(MSGRNG_MSG_CONFIG_REG, 0, v)
#define msgrng_read_bucksize(b) read_c2_register32(MSGRNG_MSG_BUCKSIZE_REG, b)
#define msgrng_write_bucksize(b, v) write_c2_register32(MSGRNG_MSG_BUCKSIZE_REG, b, v)
#define msgrng_read_cc(r, s) read_c2_register32(r, s)
#define msgrng_write_cc(r, v, s) write_c2_register32(r, s, v)
#define msgrng_load_rx_msg0() read_c2_register64(MSGRNG_RX_BUF_REG, 0)
#define msgrng_load_rx_msg1() read_c2_register64(MSGRNG_RX_BUF_REG, 1)
#define msgrng_load_rx_msg2() read_c2_register64(MSGRNG_RX_BUF_REG, 2)
#define msgrng_load_rx_msg3() read_c2_register64(MSGRNG_RX_BUF_REG, 3)
#define msgrng_load_tx_msg0(v) write_c2_register64(MSGRNG_TX_BUF_REG, 0, v)
#define msgrng_load_tx_msg1(v) write_c2_register64(MSGRNG_TX_BUF_REG, 1, v)
#define msgrng_load_tx_msg2(v) write_c2_register64(MSGRNG_TX_BUF_REG, 2, v)
#define msgrng_load_tx_msg3(v) write_c2_register64(MSGRNG_TX_BUF_REG, 3, v)
static __inline void
msgrng_send(unsigned int stid)
{
__asm__ volatile (
".set push\n"
".set noreorder\n"
"move $8, %0\n"
"c2 0x80001\n" /* msgsnd $8 */
".set pop\n"
:: "r" (stid): "$8"
);
}
static __inline void
msgrng_receive(unsigned int pri)
{
__asm__ volatile (
".set push\n"
".set noreorder\n"
"move $8, %0\n"
"c2 0x80002\n" /* msgld $8 */
".set pop\n"
:: "r" (pri): "$8"
);
}
static __inline void
msgrng_wait(unsigned int mask)
{
__asm__ volatile (
".set push\n"
".set noreorder\n"
"move $8, %0\n"
"c2 0x80003\n" /* msgwait $8 */
".set pop\n"
:: "r" (mask): "$8"
);
}
static __inline uint32_t
msgrng_access_enable(void)
{
uint32_t sr = mips_rd_status();
mips_wr_status((sr & ~MIPS_SR_INT_IE) | MIPS_SR_COP_2_BIT);
return (sr);
}
static __inline void
msgrng_restore(uint32_t sr)
{
mips_wr_status(sr);
}
struct msgrng_msg {
uint64_t msg0;
uint64_t msg1;
uint64_t msg2;
uint64_t msg3;
};
static __inline int
message_send(unsigned int size, unsigned int code,
unsigned int stid, struct msgrng_msg *msg)
{
unsigned int dest = 0;
unsigned long long status = 0;
int i = 0;
/*
* Make sure that all the writes pending at the cpu are flushed.
* Any writes pending on CPU will not be see by devices. L1/L2
* caches are coherent with IO, so no cache flush needed.
*/
__asm __volatile ("sync");
/* Load TX message buffers */
msgrng_load_tx_msg0(msg->msg0);
msgrng_load_tx_msg1(msg->msg1);
msgrng_load_tx_msg2(msg->msg2);
msgrng_load_tx_msg3(msg->msg3);
dest = ((size - 1) << 16) | (code << 8) | stid;
/*
* Retry a few times on credit fail, this should be a
* transient condition, unless there is a configuration
* failure, or the receiver is stuck.
*/
for (i = 0; i < 8; i++) {
msgrng_send(dest);
status = msgrng_read_status();
KASSERT((status & 0x2) == 0, ("Send pending fail!"));
if ((status & 0x4) == 0)
return (0);
}
/* If there is a credit failure, return error */
return (status & 0x06);
}
static __inline int
message_receive(int bucket, int *size, int *code, int *stid,
struct msgrng_msg *msg)
{
uint32_t status = 0, tmp = 0;
msgrng_receive(bucket);
/* wait for load pending to clear */
do {
status = msgrng_read_status();
} while ((status & 0x08) != 0);
/* receive error bits */
tmp = status & 0x30;
if (tmp != 0)
return (tmp);
*size = ((status & 0xc0) >> 6) + 1;
*code = (status & 0xff00) >> 8;
*stid = (status & 0x7f0000) >> 16;
msg->msg0 = msgrng_load_rx_msg0();
msg->msg1 = msgrng_load_rx_msg1();
msg->msg2 = msgrng_load_rx_msg2();
msg->msg3 = msgrng_load_rx_msg3();
return (0);
}
#define MSGRNG_STN_RX_QSIZE 256
#define MSGRNG_NSTATIONS 128
#define MSGRNG_CORE_NBUCKETS 8
struct stn_cc {
unsigned short counters[16][8];
};
struct bucket_size {
unsigned short bucket[MSGRNG_NSTATIONS];
};
extern struct bucket_size bucket_sizes;
extern struct stn_cc cc_table_cpu_0;
extern struct stn_cc cc_table_cpu_1;
extern struct stn_cc cc_table_cpu_2;
extern struct stn_cc cc_table_cpu_3;
extern struct stn_cc cc_table_cpu_4;
extern struct stn_cc cc_table_cpu_5;
extern struct stn_cc cc_table_cpu_6;
extern struct stn_cc cc_table_cpu_7;
extern struct stn_cc cc_table_xgs_0;
extern struct stn_cc cc_table_xgs_1;
extern struct stn_cc cc_table_gmac;
extern struct stn_cc cc_table_dma;
extern struct stn_cc cc_table_sec;
extern struct bucket_size xls_bucket_sizes;
extern struct stn_cc xls_cc_table_cpu_0;
extern struct stn_cc xls_cc_table_cpu_1;
extern struct stn_cc xls_cc_table_cpu_2;
extern struct stn_cc xls_cc_table_cpu_3;
extern struct stn_cc xls_cc_table_gmac0;
extern struct stn_cc xls_cc_table_gmac1;
extern struct stn_cc xls_cc_table_cmp;
extern struct stn_cc xls_cc_table_pcie;
extern struct stn_cc xls_cc_table_dma;
extern struct stn_cc xls_cc_table_sec;
typedef void (*msgring_handler)(int, int, int, int, struct msgrng_msg *, void *);
int register_msgring_handler(int startb, int endb, msgring_handler action,
void *arg);
uint32_t xlr_msgring_handler(uint8_t bucket_mask, uint32_t max_messages);
void xlr_msgring_cpu_init(void);
void xlr_msgring_config(void);
#endif

217
sys/mips/rmi/msgring_xls.c
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@ -1,217 +0,0 @@
/**********************************************************
* -----------------DO NOT EDIT THIS FILE------------------
* This file has been autogenerated by the build process
* from "msgring_xls.cfg"
**********************************************************/
#include <mips/rmi/msgring.h>
struct bucket_size xls_bucket_sizes = {
{32, 32, 32, 32, 32, 32, 32, 32,
32, 32, 32, 32, 32, 32, 32, 32,
32, 32, 32, 32, 32, 32, 32, 32,
32, 32, 32, 32, 32, 32, 32, 32,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 32, 32, 32, 32, 32, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 32, 32, 32, 32, 32, 0, 0,
64, 64, 64, 64, 32, 32, 32, 32,
0, 0, 0, 0, 0, 0, 0, 0,
128, 128, 0, 0, 0, 0, 0, 0,
}
};
struct stn_cc xls_cc_table_cpu_0 = {{
{1, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 8, 0, 0, 0, 0},
{0, 0, 0, 8, 0, 0, 0, 0},
{0, 0, 0, 8, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 4, 8, 8, 8, 8, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 4, 8, 8, 8, 8, 0, 0},
{16, 16, 16, 16, 16, 16, 16, 16},
{0, 0, 0, 0, 0, 0, 0, 0},
{32, 32, 0, 0, 0, 0, 0, 0},
}};
struct stn_cc xls_cc_table_cpu_1 = {{
{1, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 4, 8, 8, 8, 8, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 4, 8, 8, 8, 8, 0, 0},
{16, 16, 16, 16, 16, 16, 16, 16},
{0, 0, 0, 0, 0, 0, 0, 0},
{32, 32, 0, 0, 0, 0, 0, 0},
}};
struct stn_cc xls_cc_table_cpu_2 = {{
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 4, 8, 8, 8, 8, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 4, 8, 8, 8, 8, 0, 0},
{16, 16, 16, 16, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{32, 32, 0, 0, 0, 0, 0, 0},
}};
struct stn_cc xls_cc_table_cpu_3 = {{
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 4, 8, 8, 8, 8, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 4, 8, 8, 8, 8, 0, 0},
{16, 16, 16, 16, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{32, 32, 0, 0, 0, 0, 0, 0},
}};
struct stn_cc xls_cc_table_gmac0 = {{
{8, 8, 8, 8, 8, 8, 8, 8},
{8, 8, 8, 8, 8, 8, 8, 8},
{8, 8, 8, 8, 8, 8, 8, 8},
{8, 8, 8, 8, 8, 8, 8, 8},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 8, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 8, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
}};
struct stn_cc xls_cc_table_gmac1 = {{
{8, 8, 8, 8, 8, 8, 8, 8},
{8, 8, 8, 8, 8, 8, 8, 8},
{8, 8, 8, 8, 8, 8, 8, 8},
{8, 8, 8, 8, 8, 8, 8, 8},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 8, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 8, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
}};
struct stn_cc xls_cc_table_dma = {{
{4, 4, 4, 4, 4, 4, 4, 4},
{4, 4, 4, 2, 4, 4, 4, 4},
{4, 4, 4, 2, 4, 4, 4, 4},
{4, 4, 4, 2, 4, 4, 4, 4},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
}};
struct stn_cc xls_cc_table_cmp = {{
{4, 4, 4, 4, 4, 4, 4, 4},
{4, 4, 4, 2, 4, 4, 4, 4},
{4, 4, 4, 2, 4, 4, 4, 4},
{4, 4, 4, 2, 4, 4, 4, 4},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
}};
struct stn_cc xls_cc_table_pcie = {{
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
}};
struct stn_cc xls_cc_table_sec = {{
{6, 8, 8, 8, 0, 0, 0, 0},
{8, 8, 8, 4, 0, 0, 0, 0},
{8, 8, 8, 4, 0, 0, 0, 0},
{8, 8, 8, 4, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0},
}};

563
sys/mips/rmi/msgring_xls.cfg
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@ -1,563 +0,0 @@
/*********************************************************************
*
* Copyright 2003-2006 Raza Microelectronics, Inc. (RMI). All rights
* reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
*
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
*
* THIS SOFTWARE IS PROVIDED BY Raza Microelectronics, Inc. ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL RMI OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES, LOSS OF USE, DATA, OR PROFITS, OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
* THE POSSIBILITY OF SUCH DAMAGE.
*
* *****************************RMI_2**********************************/
/*
* This file defines the message ring configuration for XLS two core. It tries to allow
* many different point-point communications between the message stations on the message ring
* and as result is _not_ the best configuration for performance
*
* The message ring on phoenix family of processors connects the cpus, gmacs, xgmac/spi4,
* security engine and the general purpose DMA engines. It provides a high bandwidth,
* low latency communication links. On traditional processors, this communication goes through
* which inherently does not scale very well with increasing number of cpus.
*
* Message ring has an in-built flow control mechanism. Every agent/station on the ring has to
* have software configured credits to send messages to any agent. Every receiving agent on the
* ring has a 256 entry FIFO that can divided into "buckets". All addressing on the ring is
* in terms of buckets. There are a total 128 buckets on the ring. The total number of credits
* across all sending agents should not exceed the bucket size.
*
* Below are the receiving agents and the max number of buckets they can have
* CPU 0 : 8 buckets
* CPU 1 : 8 buckets
*
* GMAC : 8 buckets
*
* SEC : 8 buckets
*
* DMA : 8 buckets
*
* CMP : Currently disabled.
*
* The bucket size of a bucket should be aligned to the bucket's starting index in that
* receiving station's FIFO. For example, if sizes of bucket0 and bucket1 of a station
* are 32 and 32, bucket2's size has to be 64. bucket size 0 is valid.
*
* The format of the file is pretty straight forward. Each bucket definition has the size
* and the list of sending agents to that bucket with the number of credits to send.
*
* Undefined buckets have a size of 0 and Tx stations have 0 credits to send to that bucket.
*
* Following are the currently supported bucket names
* cpu_0_0
* cpu_0_1
* cpu_0_2
* cpu_0_3
* cpu_0_4
* cpu_0_5
* cpu_0_6
* cpu_0_7
*
* cpu_1_0
* cpu_1_1
* cpu_1_2
* cpu_1_3
* cpu_1_4
* cpu_1_5
* cpu_1_6
* cpu_1_7
*
* enabled only for xls-b0
* cpu_2_0
* cpu_2_1
* cpu_2_2
* cpu_2_3
* cpu_2_4
* cpu_2_5
* cpu_2_6
* cpu_2_7
*
* enabled only for xls-b0
* cpu_3_0
* cpu_3_1
* cpu_3_2
* cpu_3_3
* cpu_3_4
* cpu_3_5
* cpu_3_6
* cpu_3_7
*
* gmac0_rfr
* gmac0_tx_0
* gmac0_tx_1
* gmac0_tx_2
* gmac0_tx_3
*
* gmac1_rfr
* gmac1_tx_0
* gmac1_tx_1
* gmac1_tx_2
* gmac1_tx_3
*
* sec_pipe_0
* sec_rsa
*
* Following are the currently supported Tx Agent/Station names
*
* tx_stn_cpu_0
* tx_stn_cpu_1
*
* tx_stn_gmac0
* tx_stn_gmac1
*
* tx_stn_dma
*
* tx_stn_sec
*
*
*/
/*************************************************************/
// CPU_0 Message Station
bucket "cpu_0_0" {
size 32;
"tx_stn_gmac0" 8;
"tx_stn_gmac1" 8;
"tx_stn_sec" 6;
"tx_stn_dma" 4;
"tx_stn_cmp" 4;
"tx_stn_cpu_0" 1;
"tx_stn_cpu_1" 1; /* NEEDED BY RMIOS IPSEC */
}
bucket "cpu_0_1" {
size 32;
"tx_stn_gmac0" 8;
"tx_stn_gmac1" 8;
"tx_stn_sec" 8;
"tx_stn_dma" 4;
"tx_stn_cmp" 4;
}
bucket "cpu_0_2" {
size 32;
"tx_stn_gmac0" 8;
"tx_stn_gmac1" 8;
"tx_stn_sec" 8;
"tx_stn_dma" 4;
"tx_stn_cmp" 4;
}
bucket "cpu_0_3" {
size 32;
"tx_stn_gmac0" 8;
"tx_stn_gmac1" 8;
"tx_stn_sec" 8;
"tx_stn_dma" 4;
"tx_stn_cmp" 4;
}
bucket "cpu_0_4" {
size 32;
"tx_stn_gmac0" 8;
"tx_stn_gmac1" 8;
"tx_stn_dma" 4;
"tx_stn_cmp" 4;
}
bucket "cpu_0_5" {
size 32;
"tx_stn_gmac0" 8;
"tx_stn_gmac1" 8;
"tx_stn_dma" 4;
"tx_stn_cmp" 4;
}
bucket "cpu_0_6" {
size 32;
"tx_stn_gmac0" 8;
"tx_stn_gmac1" 8;
"tx_stn_dma" 4;
"tx_stn_cmp" 4;
}
bucket "cpu_0_7" {
size 32;
"tx_stn_gmac0" 8;
"tx_stn_gmac1" 8;
"tx_stn_dma" 4;
"tx_stn_cmp" 4;
}
/*************************************************************/
// CPU_1 Message Station
bucket "cpu_1_0" {
size 32;
"tx_stn_gmac0" 8;
"tx_stn_gmac1" 8;
"tx_stn_sec" 8;
"tx_stn_dma" 4;
"tx_stn_cmp" 4;
}
bucket "cpu_1_1" {
size 32;
"tx_stn_gmac0" 8;
"tx_stn_gmac1" 8;
"tx_stn_sec" 8;
"tx_stn_dma" 4;
"tx_stn_cmp" 4;
}
bucket "cpu_1_2" {
size 32;
"tx_stn_gmac0" 8;
"tx_stn_gmac1" 8;
"tx_stn_sec" 8;
"tx_stn_dma" 4;
"tx_stn_cmp" 4;
}
bucket "cpu_1_3" {
size 32;
"tx_stn_gmac0" 8;
"tx_stn_gmac1" 8;
"tx_stn_sec" 4;
"tx_stn_cpu_0" 8; /* NEEDED BY RMIOS IPSEC */
"tx_stn_dma" 2;
"tx_stn_cmp" 2;
}
bucket "cpu_1_4" {
size 32;
"tx_stn_gmac0" 8;
"tx_stn_gmac1" 8;
"tx_stn_dma" 4;
"tx_stn_cmp" 4;
}
bucket "cpu_1_5" {
size 32;
"tx_stn_gmac0" 8;
"tx_stn_gmac1" 8;
"tx_stn_dma" 4;
"tx_stn_cmp" 4;
}
bucket "cpu_1_6" {
size 32;
"tx_stn_gmac0" 8;
"tx_stn_gmac1" 8;
"tx_stn_dma" 4;
"tx_stn_cmp" 4;
}
bucket "cpu_1_7" {
size 32;
"tx_stn_gmac0" 8;
"tx_stn_gmac1" 8;
"tx_stn_dma" 4;
"tx_stn_cmp" 4;
}
/*************************************************************/
// CPU_2 Message Station
bucket "cpu_2_0" {
size 32;
"tx_stn_gmac0" 8;
"tx_stn_gmac1" 8;
"tx_stn_sec" 8;
"tx_stn_dma" 4;
"tx_stn_cmp" 4;
}
bucket "cpu_2_1" {
size 32;
"tx_stn_gmac0" 8;
"tx_stn_gmac1" 8;
"tx_stn_sec" 8;
"tx_stn_dma" 4;
"tx_stn_cmp" 4;
}
bucket "cpu_2_2" {
size 32;
"tx_stn_gmac0" 8;
"tx_stn_gmac1" 8;
"tx_stn_sec" 8;
"tx_stn_dma" 4;
"tx_stn_cmp" 4;
}
bucket "cpu_2_3" {
size 32;
"tx_stn_gmac0" 8;
"tx_stn_gmac1" 8;
"tx_stn_sec" 4;
"tx_stn_cpu_0" 8; /* NEEDED BY RMIOS IPSEC */
"tx_stn_dma" 2;
"tx_stn_cmp" 2;
}
bucket "cpu_2_4" {
size 32;
"tx_stn_gmac0" 8;
"tx_stn_gmac1" 8;
"tx_stn_dma" 4;
"tx_stn_cmp" 4;
}
bucket "cpu_2_5" {
size 32;
"tx_stn_gmac0" 8;
"tx_stn_gmac1" 8;
"tx_stn_dma" 4;
"tx_stn_cmp" 4;
}
bucket "cpu_2_6" {
size 32;
"tx_stn_gmac0" 8;
"tx_stn_gmac1" 8;
"tx_stn_dma" 4;
"tx_stn_cmp" 4;
}
bucket "cpu_2_7" {
size 32;
"tx_stn_gmac0" 8;
"tx_stn_gmac1" 8;
"tx_stn_dma" 4;
"tx_stn_cmp" 4;
}
/*************************************************************/
// CPU_3 Message Station
bucket "cpu_3_0" {
size 32;
"tx_stn_gmac0" 8;
"tx_stn_gmac1" 8;
"tx_stn_sec" 8;
"tx_stn_dma" 4;
"tx_stn_cmp" 4;
}
bucket "cpu_3_1" {
size 32;
"tx_stn_gmac0" 8;
"tx_stn_gmac1" 8;
"tx_stn_sec" 8;
"tx_stn_dma" 4;
"tx_stn_cmp" 4;
}
bucket "cpu_3_2" {
size 32;
"tx_stn_gmac0" 8;
"tx_stn_gmac1" 8;
"tx_stn_sec" 8;
"tx_stn_dma" 4;
"tx_stn_cmp" 4;
}
bucket "cpu_3_3" {
size 32;
"tx_stn_gmac0" 8;
"tx_stn_gmac1" 8;
"tx_stn_sec" 4;
"tx_stn_cpu_0" 8; /* NEEDED BY RMIOS IPSEC */
"tx_stn_dma" 2;
"tx_stn_cmp" 2;
}
bucket "cpu_3_4" {
size 32;
"tx_stn_gmac0" 8;
"tx_stn_gmac1" 8;
"tx_stn_dma" 4;
"tx_stn_cmp" 4;
}
bucket "cpu_3_5" {
size 32;
"tx_stn_gmac0" 8;
"tx_stn_gmac1" 8;
"tx_stn_dma" 4;
"tx_stn_cmp" 4;
}
bucket "cpu_3_6" {
size 32;
"tx_stn_gmac0" 8;
"tx_stn_gmac1" 8;
"tx_stn_dma" 4;
"tx_stn_cmp" 4;
}
bucket "cpu_3_7" {
size 32;
"tx_stn_gmac0" 8;
"tx_stn_gmac1" 8;
"tx_stn_dma" 4;
"tx_stn_cmp" 4;
}
/*************************************************************/
// GMAC Message Station
bucket "gmac0_rfr" {
size 32;
"tx_stn_cpu_0" 4;
"tx_stn_cpu_1" 4;
"tx_stn_cpu_2" 4;
"tx_stn_cpu_3" 4;
"tx_stn_gmac0" 8;
"tx_stn_gmac1" 8;
}
bucket "gmac0_tx_0" {
size 32;
"tx_stn_cpu_0" 8;
"tx_stn_cpu_1" 8;
"tx_stn_cpu_2" 8;
"tx_stn_cpu_3" 8;
}
bucket "gmac0_tx_1" {
size 32;
"tx_stn_cpu_0" 8;
"tx_stn_cpu_1" 8;
"tx_stn_cpu_2" 8;
"tx_stn_cpu_3" 8;
}
bucket "gmac0_tx_2" {
size 32;
"tx_stn_cpu_0" 8;
"tx_stn_cpu_1" 8;
"tx_stn_cpu_2" 8;
"tx_stn_cpu_3" 8;
}
bucket "gmac0_tx_3" {
size 32;
"tx_stn_cpu_0" 8;
"tx_stn_cpu_1" 8;
"tx_stn_cpu_2" 8;
"tx_stn_cpu_3" 8;
}
bucket "gmac1_rfr" {
size 32;
"tx_stn_cpu_0" 4;
"tx_stn_cpu_1" 4;
"tx_stn_cpu_2" 4;
"tx_stn_cpu_3" 4;
"tx_stn_gmac0" 8;
"tx_stn_gmac1" 8;
}
bucket "gmac1_tx_0" {
size 32;
"tx_stn_cpu_0" 8;
"tx_stn_cpu_1" 8;
"tx_stn_cpu_2" 8;
"tx_stn_cpu_3" 8;
}
bucket "gmac1_tx_1" {
size 32;
"tx_stn_cpu_0" 8;
"tx_stn_cpu_1" 8;
"tx_stn_cpu_2" 8;
"tx_stn_cpu_3" 8;
}
bucket "gmac1_tx_2" {
size 32;
"tx_stn_cpu_0" 8;
"tx_stn_cpu_1" 8;
"tx_stn_cpu_2" 8;
"tx_stn_cpu_3" 8;
}
bucket "gmac1_tx_3" {
size 32;
"tx_stn_cpu_0" 8;
"tx_stn_cpu_1" 8;
"tx_stn_cpu_2" 8;
"tx_stn_cpu_3" 8;
}
/*************************************************************/
// Security Message Station
bucket "sec_pipe_0" {
size 128;
"tx_stn_cpu_0" 32;
"tx_stn_cpu_1" 32;
"tx_stn_cpu_2" 32;
"tx_stn_cpu_3" 32;
}
bucket "sec_rsa_ecc" {
size 128;
"tx_stn_cpu_0" 32;
"tx_stn_cpu_1" 32;
"tx_stn_cpu_2" 32;
"tx_stn_cpu_3" 32;
}
bucket "dma_rsvd_0" {
size 64;
"tx_stn_cpu_0" 16;
"tx_stn_cpu_1" 16;
"tx_stn_cpu_2" 16;
"tx_stn_cpu_3" 16;
}
bucket "dma_rsvd_1" {
size 64;
"tx_stn_cpu_0" 16;
"tx_stn_cpu_1" 16;
"tx_stn_cpu_2" 16;
"tx_stn_cpu_3" 16;
}
bucket "dma_rsvd_2" {
size 64;
"tx_stn_cpu_0" 16;
"tx_stn_cpu_1" 16;
"tx_stn_cpu_2" 16;
"tx_stn_cpu_3" 16;
}
bucket "dma_rsvd_3" {
size 64;
"tx_stn_cpu_0" 16;
"tx_stn_cpu_1" 16;
"tx_stn_cpu_2" 16;
"tx_stn_cpu_3" 16;
}
/*************************************************************/
// Compression Message Station
bucket "cmp_0" {
size 32;
"tx_stn_cpu_0" 16;
"tx_stn_cpu_1" 16;
}
bucket "cmp_1" {
size 32;
"tx_stn_cpu_0" 16;
"tx_stn_cpu_1" 16;
}
bucket "cmp_2" {
size 32;
"tx_stn_cpu_0" 16;
"tx_stn_cpu_1" 16;
}
bucket "cmp_3" {
size 32;
"tx_stn_cpu_0" 16;
"tx_stn_cpu_1" 16;
}

37
sys/mips/rmi/pcibus.h
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@ -1,37 +0,0 @@
/*-
* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
*
* Copyright (c) 1998 Doug Rabson
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $FreeBSD$
*/
#define DEFAULT_PCI_CONFIG_BASE 0x18000000
#define MSI_MIPS_ADDR_BASE 0xfee00000
#define PCIE_LINK0_MSI_STATUS 0x90
#define PCIE_LINK1_MSI_STATUS 0x94
#define PCIE_LINK2_MSI_STATUS 0x190
#define PCIE_LINK3_MSI_STATUS 0x194

274
sys/mips/rmi/pic.h
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@ -1,274 +0,0 @@
/*-
* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright (c) 2003-2009 RMI Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of RMI Corporation, nor the names of its contributors,
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* RMI_BSD
* $FreeBSD$
*/
#ifndef _RMI_PIC_H_
#define _RMI_PIC_H_
#include <sys/cdefs.h>
#include <sys/lock.h>
#include <sys/mutex.h>
#include <mips/rmi/iomap.h>
#define PIC_IRT_WD_INDEX 0
#define PIC_IRT_TIMER_INDEX(i) (1 + (i))
#define PIC_IRT_UART_0_INDEX 9
#define PIC_IRT_UART_1_INDEX 10
#define PIC_IRT_I2C_0_INDEX 11
#define PIC_IRT_I2C_1_INDEX 12
#define PIC_IRT_PCMCIA_INDEX 13
#define PIC_IRT_GPIO_INDEX 14
#define PIC_IRT_HYPER_INDEX 15
#define PIC_IRT_PCIX_INDEX 16
#define PIC_IRT_GMAC0_INDEX 17
#define PIC_IRT_GMAC1_INDEX 18
#define PIC_IRT_GMAC2_INDEX 19
#define PIC_IRT_GMAC3_INDEX 20
#define PIC_IRT_XGS0_INDEX 21
#define PIC_IRT_XGS1_INDEX 22
#define PIC_IRT_HYPER_FATAL_INDEX 23
#define PIC_IRT_PCIX_FATAL_INDEX 24
#define PIC_IRT_BRIDGE_AERR_INDEX 25
#define PIC_IRT_BRIDGE_BERR_INDEX 26
#define PIC_IRT_BRIDGE_TB_INDEX 27
#define PIC_IRT_BRIDGE_AERR_NMI_INDEX 28
/* numbering for XLS */
#define PIC_IRT_BRIDGE_ERR_INDEX 25
#define PIC_IRT_PCIE_LINK0_INDEX 26
#define PIC_IRT_PCIE_LINK1_INDEX 27
#define PIC_IRT_PCIE_LINK2_INDEX 23
#define PIC_IRT_PCIE_LINK3_INDEX 24
#define PIC_IRT_PCIE_B0_LINK2_INDEX 28
#define PIC_IRT_PCIE_B0_LINK3_INDEX 29
#define PIC_IRT_PCIE_INT_INDEX 28
#define PIC_IRT_PCIE_FATAL_INDEX 29
#define PIC_IRT_GPIO_B_INDEX 30
#define PIC_IRT_USB_INDEX 31
#define PIC_NUM_IRTS 32
#define PIC_CLOCK_TIMER 7
#define PIC_CTRL 0x00
#define PIC_IPI 0x04
#define PIC_INT_ACK 0x06
#define WD_MAX_VAL_0 0x08
#define WD_MAX_VAL_1 0x09
#define WD_MASK_0 0x0a
#define WD_MASK_1 0x0b
#define WD_HEARBEAT_0 0x0c
#define WD_HEARBEAT_1 0x0d
#define PIC_IRT_0_BASE 0x40
#define PIC_IRT_1_BASE 0x80
#define PIC_TIMER_MAXVAL_0_BASE 0x100
#define PIC_TIMER_MAXVAL_1_BASE 0x110
#define PIC_TIMER_COUNT_0_BASE 0x120
#define PIC_TIMER_COUNT_1_BASE 0x130
#define PIC_IRT_0(picintr) (PIC_IRT_0_BASE + (picintr))
#define PIC_IRT_1(picintr) (PIC_IRT_1_BASE + (picintr))
#define PIC_TIMER_MAXVAL_0(i) (PIC_TIMER_MAXVAL_0_BASE + (i))
#define PIC_TIMER_MAXVAL_1(i) (PIC_TIMER_MAXVAL_1_BASE + (i))
#define PIC_TIMER_COUNT_0(i) (PIC_TIMER_COUNT_0_BASE + (i))
#define PIC_TIMER_COUNT_1(i) (PIC_TIMER_COUNT_0_BASE + (i))
#define PIC_TIMER_HZ 66000000U
/*
* We use a simple mapping form PIC interrupts to CPU IRQs.
* The PIC interrupts 0-31 are mapped to CPU irq's 8-39.
* this leaves the lower 0-7 for the cpu interrupts (like
* count/compare, msgrng) and 40-63 for IPIs
*/
#define PIC_IRQ_BASE 8
#define PIC_INTR_TO_IRQ(i) (PIC_IRQ_BASE + (i))
#define PIC_IRQ_TO_INTR(i) ((i) - PIC_IRQ_BASE)
#define PIC_WD_IRQ (PIC_IRQ_BASE + PIC_IRT_WD_INDEX)
#define PIC_TIMER_IRQ(i) (PIC_IRQ_BASE + PIC_IRT_TIMER_INDEX(i))
#define PIC_CLOCK_IRQ PIC_TIMER_IRQ(PIC_CLOCK_TIMER)
#define PIC_UART_0_IRQ (PIC_IRQ_BASE + PIC_IRT_UART_0_INDEX)
#define PIC_UART_1_IRQ (PIC_IRQ_BASE + PIC_IRT_UART_1_INDEX)
#define PIC_I2C_0_IRQ (PIC_IRQ_BASE + PIC_IRT_I2C_0_INDEX)
#define PIC_I2C_1_IRQ (PIC_IRQ_BASE + PIC_IRT_I2C_1_INDEX)
#define PIC_PCMCIA_IRQ (PIC_IRQ_BASE + PIC_IRT_PCMCIA_INDEX)
#define PIC_GPIO_IRQ (PIC_IRQ_BASE + PIC_IRT_GPIO_INDEX)
#define PIC_HYPER_IRQ (PIC_IRQ_BASE + PIC_IRT_HYPER_INDEX)
#define PIC_PCIX_IRQ (PIC_IRQ_BASE + PIC_IRT_PCIX_INDEX)
#define PIC_GMAC_0_IRQ (PIC_IRQ_BASE + PIC_IRT_GMAC0_INDEX)
#define PIC_GMAC_1_IRQ (PIC_IRQ_BASE + PIC_IRT_GMAC1_INDEX)
#define PIC_GMAC_2_IRQ (PIC_IRQ_BASE + PIC_IRT_GMAC2_INDEX)
#define PIC_GMAC_3_IRQ (PIC_IRQ_BASE + PIC_IRT_GMAC3_INDEX)
#define PIC_XGS_0_IRQ (PIC_IRQ_BASE + PIC_IRT_XGS0_INDEX)
#define PIC_XGS_1_IRQ (PIC_IRQ_BASE + PIC_IRT_XGS1_INDEX)
#define PIC_HYPER_FATAL_IRQ (PIC_IRQ_BASE + PIC_IRT_HYPER_FATAL_INDEX)
#define PIC_PCIX_FATAL_IRQ (PIC_IRQ_BASE + PIC_IRT_PCIX_FATAL_INDEX)
#define PIC_BRIDGE_AERR_IRQ (PIC_IRQ_BASE + PIC_IRT_BRIDGE_AERR_INDEX)
#define PIC_BRIDGE_BERR_IRQ (PIC_IRQ_BASE + PIC_IRT_BRIDGE_BERR_INDEX)
#define PIC_BRIDGE_TB_IRQ (PIC_IRQ_BASE + PIC_IRT_BRIDGE_TB_INDEX)
#define PIC_BRIDGE_AERR_NMI_IRQ (PIC_IRQ_BASE + PIC_IRT_BRIDGE_AERR_NMI_INDEX)
#define PIC_BRIDGE_ERR_IRQ (PIC_IRQ_BASE + PIC_IRT_BRIDGE_ERR_INDEX)
#define PIC_PCIE_LINK0_IRQ (PIC_IRQ_BASE + PIC_IRT_PCIE_LINK0_INDEX)
#define PIC_PCIE_LINK1_IRQ (PIC_IRQ_BASE + PIC_IRT_PCIE_LINK1_INDEX)
#define PIC_PCIE_LINK2_IRQ (PIC_IRQ_BASE + PIC_IRT_PCIE_LINK2_INDEX)
#define PIC_PCIE_LINK3_IRQ (PIC_IRQ_BASE + PIC_IRT_PCIE_LINK3_INDEX)
#define PIC_PCIE_B0_LINK2_IRQ (PIC_IRQ_BASE + PIC_IRT_PCIE_B0_LINK2_INDEX)
#define PIC_PCIE_B0_LINK3_IRQ (PIC_IRQ_BASE + PIC_IRT_PCIE_B0_LINK3_INDEX)
#define PIC_PCIE_INT_IRQ (PIC_IRQ_BASE + PIC_IRT_PCIE_INT_INDEX)
#define PIC_PCIE_FATAL_IRQ (PIC_IRQ_BASE + PIC_IRT_PCIE_FATAL_INDEX)
#define PIC_GPIO_B_IRQ (PIC_IRQ_BASE + PIC_IRT_GPIO_B_INDEX)
#define PIC_USB_IRQ (PIC_IRQ_BASE + PIC_IRT_USB_INDEX)
#define PIC_IRQ_IS_PICINTR(irq) ((irq) >= PIC_IRQ_BASE && \
(irq) < PIC_IRQ_BASE + PIC_NUM_IRTS)
#define PIC_IS_EDGE_TRIGGERED(i) ((i) >= PIC_IRT_TIMER_INDEX(0) && \
(i) <= PIC_IRT_TIMER_INDEX(7))
extern struct mtx xlr_pic_lock;
static __inline uint32_t
pic_read_control(void)
{
xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
uint32_t reg;
mtx_lock_spin(&xlr_pic_lock);
reg = xlr_read_reg(mmio, PIC_CTRL);
mtx_unlock_spin(&xlr_pic_lock);
return (reg);
}
static __inline void
pic_write_control(uint32_t control)
{
xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
mtx_lock_spin(&xlr_pic_lock);
xlr_write_reg(mmio, PIC_CTRL, control);
mtx_unlock_spin(&xlr_pic_lock);
}
static __inline void
pic_update_control(uint32_t control)
{
xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
mtx_lock_spin(&xlr_pic_lock);
xlr_write_reg(mmio, PIC_CTRL, (control | xlr_read_reg(mmio, PIC_CTRL)));
mtx_unlock_spin(&xlr_pic_lock);
}
static __inline void
pic_ack(int picintr)
{
xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
xlr_write_reg(mmio, PIC_INT_ACK, 1U << picintr);
}
static __inline
void pic_send_ipi(int cpu, int ipi)
{
xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
int tid, pid;
tid = cpu & 0x3;
pid = (cpu >> 2) & 0x7;
xlr_write_reg(mmio, PIC_IPI, (pid << 20) | (tid << 16) | ipi);
}
static __inline
void pic_setup_intr(int picintr, int irq, uint32_t cpumask, int level)
{
xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
mtx_lock_spin(&xlr_pic_lock);
xlr_write_reg(mmio, PIC_IRT_0(picintr), cpumask);
xlr_write_reg(mmio, PIC_IRT_1(picintr), ((1U << 31) | (level << 30) |
(1 << 6) | irq));
mtx_unlock_spin(&xlr_pic_lock);
}
static __inline void
pic_init_timer(int timer)
{
xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
uint32_t val;
mtx_lock_spin(&xlr_pic_lock);
val = xlr_read_reg(mmio, PIC_CTRL);
val |= (1 << (8 + timer));
xlr_write_reg(mmio, PIC_CTRL, val);
mtx_unlock_spin(&xlr_pic_lock);
}
static __inline void
pic_set_timer(int timer, uint64_t maxval)
{
xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
xlr_write_reg(mmio, PIC_TIMER_MAXVAL_0(timer),
(maxval & 0xffffffff));
xlr_write_reg(mmio, PIC_TIMER_MAXVAL_1(timer),
(maxval >> 32) & 0xffffffff);
}
static __inline uint32_t
pic_timer_count32(int timer)
{
xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
return (xlr_read_reg(mmio, PIC_TIMER_COUNT_0(timer)));
}
/*
* The timer can wrap 32 bits between the two reads, so we
* need additional logic to detect that.
*/
static __inline uint64_t
pic_timer_count(int timer)
{
xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
uint32_t tu1, tu2, tl;
tu1 = xlr_read_reg(mmio, PIC_TIMER_COUNT_1(timer));
tl = xlr_read_reg(mmio, PIC_TIMER_COUNT_0(timer));
tu2 = xlr_read_reg(mmio, PIC_TIMER_COUNT_1(timer));
if (tu2 != tu1)
tl = xlr_read_reg(mmio, PIC_TIMER_COUNT_0(timer));
return (((uint64_t)tu2 << 32) | tl);
}
#endif /* _RMI_PIC_H_ */

111
sys/mips/rmi/rmi_boot_info.h
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@ -1,111 +0,0 @@
/*-
* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright (c) 2003-2009 RMI Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of RMI Corporation, nor the names of its contributors,
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* RMI_BSD
* $FreeBSD$
*/
#ifndef _SHARED_STRUCTS_H
#define _SHARED_STRUCTS_H
#define BOOT1_INFO_VERSION 0x0001
struct boot1_info {
uint64_t boot_level;
uint64_t io_base;
uint64_t output_device;
uint64_t uart_print;
uint64_t led_output;
uint64_t init;
uint64_t exit;
uint64_t warm_reset;
uint64_t wakeup;
uint64_t cpu_online_map;
uint64_t master_reentry_sp;
uint64_t master_reentry_gp;
uint64_t master_reentry_fn;
uint64_t slave_reentry_fn;
uint64_t magic_dword;
uint64_t uart_putchar;
uint64_t size;
uint64_t uart_getchar;
uint64_t nmi_handler;
uint64_t psb_version;
uint64_t mac_addr;
uint64_t cpu_frequency;
uint64_t board_version;
uint64_t malloc;
uint64_t free;
uint64_t alloc_pbuf;
uint64_t free_pbuf;
uint64_t psb_os_cpu_map;
uint64_t userapp_cpu_map;
uint64_t wakeup_os;
uint64_t psb_mem_map;
uint64_t board_major_version;
uint64_t board_minor_version;
uint64_t board_manf_revision;
uint64_t board_serial_number;
uint64_t psb_physaddr_map;
};
extern struct boot1_info xlr_boot1_info;
/* This structure is passed to all applications launched from the linux
loader through K0 register
*/
#define XLR_LOADER_INFO_MAGIC 0x600ddeed
struct xlr_loader_info {
uint32_t magic;
/* xlr_loader_shared_struct_t for CPU 0 will start here */
unsigned long sh_mem_start;
/* Size of the shared memory b/w linux apps and rmios apps */
uint32_t app_sh_mem_size;
};
/* Boot loader uses the linux mips convention */
#define BOOT1_MEMMAP_MAX 32
enum xlr_phys_memmap_t {
BOOT1_MEM_RAM = 1, BOOT1_MEM_ROM_DATA, BOOT1_MEM_RESERVED
};
struct xlr_boot1_mem_map {
uint32_t num_entries;
struct {
uint64_t addr;
uint64_t size;
uint32_t type;
uint32_t pad;
} physmem_map[BOOT1_MEMMAP_MAX];
};
#endif

581
sys/mips/rmi/rmi_mips_exts.h
View File

@ -1,581 +0,0 @@
/*-
* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright (c) 2003-2009 RMI Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of RMI Corporation, nor the names of its contributors,
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* RMI_BSD
* $FreeBSD$
*/
#ifndef __MIPS_EXTS_H__
#define __MIPS_EXTS_H__
#define CPU_BLOCKID_IFU 0
#define CPU_BLOCKID_ICU 1
#define CPU_BLOCKID_IEU 2
#define CPU_BLOCKID_LSU 3
#define CPU_BLOCKID_MMU 4
#define CPU_BLOCKID_PRF 5
#define LSU_CERRLOG_REGID 9
#if defined(__mips_n64) || defined(__mips_n32)
static __inline uint64_t
read_xlr_ctrl_register(int block, int reg)
{
uint64_t res;
__asm__ __volatile__(
".set push\n\t"
".set noreorder\n\t"
"move $9, %1\n\t"
".word 0x71280018\n\t" /* mfcr $8, $9 */
"move %0, $8\n\t"
".set pop\n"
: "=r" (res) : "r"((block << 8) | reg)
: "$8", "$9"
);
return (res);
}
static __inline void
write_xlr_ctrl_register(int block, int reg, uint64_t value)
{
__asm__ __volatile__(
".set push\n\t"
".set noreorder\n\t"
"move $8, %0\n"
"move $9, %1\n"
".word 0x71280019\n" /* mtcr $8, $9 */
".set pop\n"
:
: "r" (value), "r" ((block << 8) | reg)
: "$8", "$9"
);
}
#else /* !(defined(__mips_n64) || defined(__mips_n32)) */
static __inline uint64_t
read_xlr_ctrl_register(int block, int reg)
{
uint32_t high, low;
__asm__ __volatile__(
".set push\n\t"
".set noreorder\n\t"
".set mips64\n\t"
"move $9, %2\n"
".word 0x71280018\n" /* "mfcr $8, $9\n" */
"dsra32 %0, $8, 0\n\t"
"sll %1, $8, 0\n\t"
".set pop"
: "=r" (high), "=r"(low)
: "r" ((block << 8) | reg)
: "$8", "$9");
return ( (((uint64_t)high) << 32) | low);
}
static __inline void
write_xlr_ctrl_register(int block, int reg, uint64_t value)
{
uint32_t low, high;
high = value >> 32;
low = value & 0xffffffff;
__asm__ __volatile__(
".set push\n\t"
".set noreorder\n\t"
".set mips64\n\t"
"dsll32 $9, %0, 0\n\t"
"dsll32 $8, %1, 0\n\t"
"dsrl32 $8, $8, 0\n\t"
"or $8, $9, $8\n\t"
"move $9, %2\n\t"
".word 0x71280019\n\t" /* mtcr $8, $9 */
".set pop\n"
: /* No outputs */
: "r" (high), "r" (low), "r"((block << 8) | reg)
: "$8", "$9");
}
#endif /* defined(__mips_n64) || defined(__mips_n32) */
/*
* 32 bit read write for c0
*/
#define read_c0_register32(reg, sel) \
({ \
uint32_t __rv; \
__asm__ __volatile__( \
".set push\n\t" \
".set mips32\n\t" \
"mfc0 %0, $%1, %2\n\t" \
".set pop\n" \
: "=r" (__rv) : "i" (reg), "i" (sel) ); \
__rv; \
})
#define write_c0_register32(reg, sel, value) \
__asm__ __volatile__( \
".set push\n\t" \
".set mips32\n\t" \
"mtc0 %0, $%1, %2\n\t" \
".set pop\n" \
: : "r" (value), "i" (reg), "i" (sel) );
#define read_c2_register32(reg, sel) \
({ \
uint32_t __rv; \
__asm__ __volatile__( \
".set push\n\t" \
".set mips32\n\t" \
"mfc2 %0, $%1, %2\n\t" \
".set pop\n" \
: "=r" (__rv) : "i" (reg), "i" (sel) ); \
__rv; \
})
#define write_c2_register32(reg, sel, value) \
__asm__ __volatile__( \
".set push\n\t" \
".set mips32\n\t" \
"mtc2 %0, $%1, %2\n\t" \
".set pop\n" \
: : "r" (value), "i" (reg), "i" (sel) );
#if defined(__mips_n64) || defined(__mips_n32)
/*
* On 64 bit compilation, the operations are simple
*/
#define read_c0_register64(reg, sel) \
({ \
uint64_t __rv; \
__asm__ __volatile__( \
".set push\n\t" \
".set mips64\n\t" \
"dmfc0 %0, $%1, %2\n\t" \
".set pop\n" \
: "=r" (__rv) : "i" (reg), "i" (sel) ); \
__rv; \
})
#define write_c0_register64(reg, sel, value) \
__asm__ __volatile__( \
".set push\n\t" \
".set mips64\n\t" \
"dmtc0 %0, $%1, %2\n\t" \
".set pop\n" \
: : "r" (value), "i" (reg), "i" (sel) );
#define read_c2_register64(reg, sel) \
({ \
uint64_t __rv; \
__asm__ __volatile__( \
".set push\n\t" \
".set mips64\n\t" \
"dmfc2 %0, $%1, %2\n\t" \
".set pop\n" \
: "=r" (__rv) : "i" (reg), "i" (sel) ); \
__rv; \
})
#define write_c2_register64(reg, sel, value) \
__asm__ __volatile__( \
".set push\n\t" \
".set mips64\n\t" \
"dmtc2 %0, $%1, %2\n\t" \
".set pop\n" \
: : "r" (value), "i" (reg), "i" (sel) );
#else /* ! (defined(__mips_n64) || defined(__mips_n32)) */
/*
* 32 bit compilation, 64 bit values has to split
*/
#define read_c0_register64(reg, sel) \
({ \
uint32_t __high, __low; \
__asm__ __volatile__( \
".set push\n\t" \
".set noreorder\n\t" \
".set mips64\n\t" \
"dmfc0 $8, $%2, %3\n\t" \
"dsra32 %0, $8, 0\n\t" \
"sll %1, $8, 0\n\t" \
".set pop\n" \
: "=r"(__high), "=r"(__low): "i"(reg), "i"(sel) \
: "$8"); \
((uint64_t)__high << 32) | __low; \
})
#define write_c0_register64(reg, sel, value) \
do { \
uint32_t __high = value >> 32; \
uint32_t __low = value & 0xffffffff; \
__asm__ __volatile__( \
".set push\n\t" \
".set noreorder\n\t" \
".set mips64\n\t" \
"dsll32 $8, %1, 0\n\t" \
"dsll32 $9, %0, 0\n\t" \
"dsrl32 $8, $8, 0\n\t" \
"or $8, $8, $9\n\t" \
"dmtc0 $8, $%2, %3\n\t" \
".set pop" \
:: "r"(__high), "r"(__low), "i"(reg), "i"(sel) \
:"$8", "$9"); \
} while(0)
#define read_c2_register64(reg, sel) \
({ \
uint32_t __high, __low; \
__asm__ __volatile__( \
".set push\n\t" \
".set noreorder\n\t" \
".set mips64\n\t" \
"dmfc2 $8, $%2, %3\n\t" \
"dsra32 %0, $8, 0\n\t" \
"sll %1, $8, 0\n\t" \
".set pop\n" \
: "=r"(__high), "=r"(__low): "i"(reg), "i"(sel) \
: "$8"); \
((uint64_t)__high << 32) | __low; \
})
#define write_c2_register64(reg, sel, value) \
do { \
uint32_t __high = value >> 32; \
uint32_t __low = value & 0xffffffff; \
__asm__ __volatile__( \
".set push\n\t" \
".set noreorder\n\t" \
".set mips64\n\t" \
"dsll32 $8, %1, 0\n\t" \
"dsll32 $9, %0, 0\n\t" \
"dsrl32 $8, $8, 0\n\t" \
"or $8, $8, $9\n\t" \
"dmtc2 $8, $%2, %3\n\t" \
".set pop" \
:: "r"(__high), "r"(__low), "i"(reg), "i"(sel) \
:"$8", "$9"); \
} while(0)
#endif /* defined(__mips_n64) || defined(__mips_n32) */
static __inline int
xlr_cpu_id(void)
{
return (read_c0_register32(15, 1) & 0x1f);
}
static __inline int
xlr_core_id(void)
{
return (xlr_cpu_id() / 4);
}
static __inline int
xlr_thr_id(void)
{
return (read_c0_register32(15, 1) & 0x3);
}
/* Additional registers on the XLR */
#define MIPS_COP_0_OSSCRATCH 22
#define XLR_CACHELINE_SIZE 32
/* functions to write to and read from the extended
* cp0 registers.
* EIRR : Extended Interrupt Request Register
* cp0 register 9 sel 6
* bits 0...7 are same as cause register 8...15
* EIMR : Extended Interrupt Mask Register
* cp0 register 9 sel 7
* bits 0...7 are same as status register 8...15
*/
static __inline uint64_t
read_c0_eirr64(void)
{
return (read_c0_register64(9, 6));
}
static __inline void
write_c0_eirr64(uint64_t val)
{
write_c0_register64(9, 6, val);
}
static __inline uint64_t
read_c0_eimr64(void)
{
return (read_c0_register64(9, 7));
}
static __inline void
write_c0_eimr64(uint64_t val)
{
write_c0_register64(9, 7, val);
}
static __inline int
xlr_test_and_set(int *lock)
{
int oldval = 0;
__asm__ __volatile__(
".set push\n"
".set noreorder\n"
"move $9, %2\n"
"li $8, 1\n"
// "swapw $8, $9\n"
".word 0x71280014\n"
"move %1, $8\n"
".set pop\n"
: "+m"(*lock), "=r"(oldval)
: "r"((unsigned long)lock)
: "$8", "$9"
);
return (oldval == 0 ? 1 /* success */ : 0 /* failure */);
}
static __inline uint32_t
xlr_mfcr(uint32_t reg)
{
uint32_t val;
__asm__ __volatile__(
"move $8, %1\n"
".word 0x71090018\n"
"move %0, $9\n"
: "=r"(val)
: "r"(reg):"$8", "$9");
return val;
}
static __inline void
xlr_mtcr(uint32_t reg, uint32_t val)
{
__asm__ __volatile__(
"move $8, %1\n"
"move $9, %0\n"
".word 0x71090019\n"
:: "r"(val), "r"(reg)
: "$8", "$9");
}
/*
* Atomic increment a unsigned int
*/
static __inline unsigned int
xlr_ldaddwu(unsigned int value, unsigned int *addr)
{
__asm__ __volatile__(
".set push\n"
".set noreorder\n"
"move $8, %2\n"
"move $9, %3\n"
".word 0x71280011\n" /* ldaddwu $8, $9 */
"move %0, $8\n"
".set pop\n"
: "=&r"(value), "+m"(*addr)
: "0"(value), "r" ((unsigned long)addr)
: "$8", "$9");
return (value);
}
#if defined(__mips_n64)
static __inline uint32_t
xlr_paddr_lw(uint64_t paddr)
{
paddr |= 0x9800000000000000ULL;
return (*(uint32_t *)(uintptr_t)paddr);
}
static __inline uint64_t
xlr_paddr_ld(uint64_t paddr)
{
paddr |= 0x9800000000000000ULL;
return (*(uint64_t *)(uintptr_t)paddr);
}
#elif defined(__mips_n32)
static __inline uint32_t
xlr_paddr_lw(uint64_t paddr)
{
uint32_t val;
paddr |= 0x9800000000000000ULL;
__asm__ __volatile__(
".set push \n\t"
".set mips64 \n\t"
"lw %0, 0(%1) \n\t"
".set pop \n"
: "=r"(val)
: "r"(paddr));
return (val);
}
static __inline uint64_t
xlr_paddr_ld(uint64_t paddr)
{
uint64_t val;
paddr |= 0x9800000000000000ULL;
__asm__ __volatile__(
".set push \n\t"
".set mips64 \n\t"
"ld %0, 0(%1) \n\t"
".set pop \n"
: "=r"(val)
: "r"(paddr));
return (val);
}
#else /* o32 compilation */
static __inline uint32_t
xlr_paddr_lw(uint64_t paddr)
{
uint32_t addrh, addrl;
uint32_t val;
addrh = 0x98000000 | (paddr >> 32);
addrl = paddr & 0xffffffff;
__asm__ __volatile__(
".set push \n\t"
".set mips64 \n\t"
"dsll32 $8, %1, 0 \n\t"
"dsll32 $9, %2, 0 \n\t" /* get rid of the */
"dsrl32 $9, $9, 0 \n\t" /* sign extend */
"or $9, $8, $8 \n\t"
"lw %0, 0($9) \n\t"
".set pop \n"
: "=r"(val)
: "r"(addrh), "r"(addrl)
: "$8", "$9");
return (val);
}
static __inline uint64_t
xlr_paddr_ld(uint64_t paddr)
{
uint32_t addrh, addrl;
uint32_t valh, vall;
addrh = 0x98000000 | (paddr >> 32);
addrl = paddr & 0xffffffff;
__asm__ __volatile__(
".set push \n\t"
".set mips64 \n\t"
"dsll32 %0, %2, 0 \n\t"
"dsll32 %1, %3, 0 \n\t" /* get rid of the */
"dsrl32 %1, %1, 0 \n\t" /* sign extend */
"or %0, %0, %1 \n\t"
"lw %1, 4(%0) \n\t"
"lw %0, 0(%0) \n\t"
".set pop \n"
: "=&r"(valh), "=&r"(vall)
: "r"(addrh), "r"(addrl));
return (((uint64_t)valh << 32) | vall);
}
#endif
/*
* XXX: Not really needed in n32 or n64, retain for now
*/
#if defined(__mips_n64) || defined(__mips_n32)
static __inline uint32_t
xlr_enable_kx(void)
{
return (0);
}
static __inline void
xlr_restore_kx(uint32_t sr)
{
}
#else /* !defined(__mips_n64) && !defined(__mips_n32) */
/*
* o32 compilation, we will disable interrupts and enable
* the KX bit so that we can use XKPHYS to access any 40bit
* physical address
*/
static __inline uint32_t
xlr_enable_kx(void)
{
uint32_t sr = mips_rd_status();
mips_wr_status((sr & ~MIPS_SR_INT_IE) | MIPS_SR_KX);
return (sr);
}
static __inline void
xlr_restore_kx(uint32_t sr)
{
mips_wr_status(sr);
}
#endif /* defined(__mips_n64) || defined(__mips_n32) */
/*
* XLR/XLS processors have maximum 8 cores, and maximum 4 threads
* per core
*/
#define XLR_MAX_CORES 8
#define XLR_NTHREADS 4
/*
* FreeBSD can be started with few threads and cores turned off,
* so have a hardware thread id to FreeBSD cpuid mapping.
*/
extern int xlr_ncores;
extern int xlr_threads_per_core;
extern uint32_t xlr_hw_thread_mask;
extern int xlr_cpuid_to_hwtid[];
extern int xlr_hwtid_to_cpuid[];
#endif

669
sys/mips/rmi/rootfs_list.txt
View File

@ -1,669 +0,0 @@
# $FreeBSD$
#
# This is the list of files that
# should be in your rootfs (copy it from
# the build world nfsmount dir. When the rge0
# driver gets fixed we should be able to start
# using nfs mount... for now we need to use MD_ROOT
./.cshrc
./.profile
./COPYRIGHT
./bin
./bin/cat
./bin/chflags
./bin/chio
./bin/chmod
./bin/cp
./bin/csh
./bin/tcsh
./bin/date
./bin/dd
./bin/df
./bin/domainname
./bin/echo
./bin/ed
./bin/red
./bin/expr
./bin/getfacl
./bin/hostname
./bin/kenv
./bin/kill
./bin/ln
./bin/link
./bin/ls
./bin/mkdir
./bin/mv
./bin/pax
./bin/pkill
./bin/pgrep
./bin/ps
./bin/pwd
./bin/rcp
./bin/realpath
./bin/rm
./bin/unlink
./bin/rmail
./bin/rmdir
./bin/setfacl
./bin/sh
./bin/sleep
./bin/stty
./bin/sync
./bin/test
./bin/[
./bin/uuidgen
./etc
./etc/bluetooth
./etc/bluetooth/hcsecd.conf
./etc/bluetooth/hosts
./etc/bluetooth/protocols
./etc/defaults
./etc/defaults/bluetooth.device.conf
./etc/defaults/devfs.rules
./etc/defaults/periodic.conf
./etc/defaults/rc.conf
./etc/devd
./etc/devd/asus.conf
./etc/gss
./etc/gss/mech
./etc/gss/qop
./etc/mail
./etc/mail/mailer.conf
./etc/mail/freebsd.mc
./etc/mail/freebsd.cf
./etc/mail/freebsd.submit.mc
./etc/mail/freebsd.submit.cf
./etc/mail/helpfile
./etc/mail/sendmail.cf
./etc/mail/submit.cf
./etc/mail/Makefile
./etc/mail/README
./etc/mail/access.sample
./etc/mail/virtusertable.sample
./etc/mail/mailertable.sample
./etc/mail/aliases
./etc/mtree
./etc/mtree/BSD.include.dist
./etc/mtree/BSD.root.dist
./etc/mtree/BSD.usr.dist
./etc/mtree/BSD.var.dist
./etc/mtree/BSD.sendmail.dist
./etc/mtree/BIND.chroot.dist
./etc/pam.d
./etc/pam.d/README
./etc/pam.d/atrun
./etc/pam.d/cron
./etc/pam.d/ftpd
./etc/pam.d/imap
./etc/pam.d/kde
./etc/pam.d/login
./etc/pam.d/other
./etc/pam.d/passwd
./etc/pam.d/pop3
./etc/pam.d/rsh
./etc/pam.d/sshd
./etc/pam.d/su
./etc/pam.d/system
./etc/pam.d/telnetd
./etc/pam.d/xdm
./etc/pam.d/ftp
./etc/periodic
./etc/periodic/daily
./etc/periodic/daily/100.clean-disks
./etc/periodic/daily/110.clean-tmps
./etc/periodic/daily/120.clean-preserve
./etc/periodic/daily/200.backup-passwd
./etc/periodic/daily/330.news
./etc/periodic/daily/400.status-disks
./etc/periodic/daily/404.status-zfs
./etc/periodic/daily/405.status-ata-raid
./etc/periodic/daily/406.status-gmirror
./etc/periodic/daily/407.status-graid3
./etc/periodic/daily/408.status-gstripe
./etc/periodic/daily/409.status-gconcat
./etc/periodic/daily/420.status-network
./etc/periodic/daily/450.status-security
./etc/periodic/daily/999.local
./etc/periodic/daily/310.accounting
./etc/periodic/daily/470.status-named
./etc/periodic/daily/300.calendar
./etc/periodic/daily/130.clean-msgs
./etc/periodic/daily/480.status-ntpd
./etc/periodic/daily/140.clean-rwho
./etc/periodic/daily/430.status-rwho
./etc/periodic/daily/150.clean-hoststat
./etc/periodic/daily/210.backup-aliases
./etc/periodic/daily/440.status-mailq
./etc/periodic/daily/460.status-mail-rejects
./etc/periodic/daily/500.queuerun
./etc/periodic/monthly
./etc/periodic/monthly/999.local
./etc/periodic/monthly/200.accounting
./etc/periodic/security
./etc/periodic/security/100.chksetuid
./etc/periodic/security/200.chkmounts
./etc/periodic/security/300.chkuid0
./etc/periodic/security/400.passwdless
./etc/periodic/security/410.logincheck
./etc/periodic/security/700.kernelmsg
./etc/periodic/security/800.loginfail
./etc/periodic/security/900.tcpwrap
./etc/periodic/security/security.functions
./etc/periodic/security/510.ipfdenied
./etc/periodic/security/500.ipfwdenied
./etc/periodic/security/550.ipfwlimit
./etc/periodic/security/520.pfdenied
./etc/periodic/weekly
./etc/periodic/weekly/340.noid
./etc/periodic/weekly/999.local
./etc/periodic/weekly/310.locate
./etc/periodic/weekly/320.whatis
./etc/periodic/weekly/400.status-pkg
./etc/ppp
./etc/ppp/ppp.conf
./etc/rc.d
./etc/rc.d/DAEMON
./etc/rc.d/FILESYSTEMS
./etc/rc.d/LOGIN
./etc/rc.d/NETWORKING
./etc/rc.d/SERVERS
./etc/rc.d/abi
./etc/rc.d/accounting
./etc/rc.d/addswap
./etc/rc.d/adjkerntz
./etc/rc.d/amd
./etc/rc.d/apm
./etc/rc.d/apmd
./etc/rc.d/archdep
./etc/rc.d/atm1
./etc/rc.d/atm2
./etc/rc.d/atm3
./etc/rc.d/auditd
./etc/rc.d/bgfsck
./etc/rc.d/bluetooth
./etc/rc.d/bootparams
./etc/rc.d/bridge
./etc/rc.d/bthidd
./etc/rc.d/ccd
./etc/rc.d/cleanvar
./etc/rc.d/cleartmp
./etc/rc.d/cron
./etc/rc.d/ddb
./etc/rc.d/defaultroute
./etc/rc.d/devd
./etc/rc.d/devfs
./etc/rc.d/dhclient
./etc/rc.d/dmesg
./etc/rc.d/dumpon
./etc/rc.d/encswap
./etc/rc.d/fsck
./etc/rc.d/ftp-proxy
./etc/rc.d/ftpd
./etc/rc.d/gbde
./etc/rc.d/geli
./etc/rc.d/geli2
./etc/rc.d/gssd
./etc/rc.d/hcsecd
./etc/rc.d/hostapd
./etc/rc.d/hostid
./etc/rc.d/hostid_save
./etc/rc.d/hostname
./etc/rc.d/inetd
./etc/rc.d/initrandom
./etc/rc.d/ip6addrctl
./etc/rc.d/ip6fw
./etc/rc.d/ipfilter
./etc/rc.d/ipfs
./etc/rc.d/ipfw
./etc/rc.d/ipmon
./etc/rc.d/ipnat
./etc/rc.d/ipsec
./etc/rc.d/jail
./etc/rc.d/kadmind
./etc/rc.d/kerberos
./etc/rc.d/keyserv
./etc/rc.d/kldxref
./etc/rc.d/kpasswdd
./etc/rc.d/ldconfig
./etc/rc.d/local
./etc/rc.d/localpkg
./etc/rc.d/lockd
./etc/rc.d/lpd
./etc/rc.d/mixer
./etc/rc.d/motd
./etc/rc.d/mountcritlocal
./etc/rc.d/mountcritremote
./etc/rc.d/mountlate
./etc/rc.d/mdconfig
./etc/rc.d/mdconfig2
./etc/rc.d/mountd
./etc/rc.d/moused
./etc/rc.d/mroute6d
./etc/rc.d/mrouted
./etc/rc.d/msgs
./etc/rc.d/named
./etc/rc.d/natd
./etc/rc.d/netif
./etc/rc.d/netoptions
./etc/rc.d/newsyslog
./etc/rc.d/pf
./etc/rc.d/nfscbd
./etc/rc.d/nfsclient
./etc/rc.d/nfsd
./etc/rc.d/nfsserver
./etc/rc.d/nfsuserd
./etc/rc.d/nisdomain
./etc/rc.d/nsswitch
./etc/rc.d/ntpd
./etc/rc.d/ntpdate
./etc/rc.d/othermta
./etc/rc.d/pflog
./etc/rc.d/pfsync
./etc/rc.d/powerd
./etc/rc.d/power_profile
./etc/rc.d/ppp
./etc/rc.d/pppoed
./etc/rc.d/pwcheck
./etc/rc.d/quota
./etc/rc.d/random
./etc/rc.d/rarpd
./etc/rc.d/resolv
./etc/rc.d/rfcomm_pppd_server
./etc/rc.d/root
./etc/rc.d/route6d
./etc/rc.d/routed
./etc/rc.d/routing
./etc/rc.d/rpcbind
./etc/rc.d/rtadvd
./etc/rc.d/rwho
./etc/rc.d/savecore
./etc/rc.d/sdpd
./etc/rc.d/securelevel
./etc/rc.d/sendmail
./etc/rc.d/serial
./etc/rc.d/sppp
./etc/rc.d/statd
./etc/rc.d/static_arp
./etc/rc.d/stf
./etc/rc.d/swap1
./etc/rc.d/syscons
./etc/rc.d/sysctl
./etc/rc.d/syslogd
./etc/rc.d/timed
./etc/rc.d/tmp
./etc/rc.d/ugidfw
./etc/rc.d/var
./etc/rc.d/virecover
./etc/rc.d/watchdogd
./etc/rc.d/wpa_supplicant
./etc/rc.d/ypbind
./etc/rc.d/yppasswdd
./etc/rc.d/ypserv
./etc/rc.d/ypset
./etc/rc.d/ypupdated
./etc/rc.d/ypxfrd
./etc/rc.d/zfs
./etc/rc.d/zvol
./etc/rc.d/sshd
./etc/rc.d/nscd
./etc/security
./etc/security/audit_class
./etc/security/audit_event
./etc/security/audit_control
./etc/security/audit_user
./etc/security/audit_warn
./etc/ssh
./etc/ssh/ssh_config
./etc/ssh/sshd_config
./etc/ssh/moduli
./etc/ssl
./etc/ssl/openssl.cnf
./etc/crontab
./etc/devd.conf
./etc/devfs.conf
./etc/ddb.conf
./etc/dhclient.conf
./etc/disktab
./etc/fbtab
./etc/ftpusers
./etc/gettytab
./etc/group
./etc/hosts
./etc/hosts.allow
./etc/hosts.equiv
./etc/inetd.conf
./etc/libalias.conf
./etc/login.access
./etc/login.conf
./etc/mac.conf
./etc/motd
./etc/netconfig
./etc/network.subr
./etc/networks
./etc/newsyslog.conf
./etc/nsswitch.conf
./etc/phones
./etc/profile
./etc/protocols
./etc/rc
./etc/rc.bsdextended
./etc/rc.firewall
./etc/rc.firewall6
./etc/rc.initdiskless
./etc/rc.sendmail
./etc/rc.shutdown
./etc/rc.subr
./etc/remote
./etc/rpc
./etc/services
./etc/shells
./etc/sysctl.conf
./etc/syslog.conf
./etc/ttys
./etc/amd.map
./etc/apmd.conf
./etc/freebsd-update.conf
./etc/locate.rc
./etc/hosts.lpd
./etc/printcap
./etc/mail.rc
./etc/manpath.config
./etc/ntp.conf
./etc/nscd.conf
./etc/portsnap.conf
./etc/pf.os
./etc/csh.cshrc
./etc/csh.login
./etc/csh.logout
./etc/regdomain.xml
./etc/login.conf.db
./etc/pwd.db
./etc/netstart
./etc/pccard_ether
./etc/rc.suspend
./etc/rc.resume
./etc/master.passwd
./etc/nsmb.conf
./etc/opieaccess
./etc/spwd.db
./etc/passwd
./etc/dumpdates
./etc/fstab
./etc/rc.conf
./etc/resolv.conf
./etc/termcap
./lib
./lib/geom
./lib/geom/geom_cache.so
./lib/geom/geom_concat.so
./lib/geom/geom_eli.so
./lib/geom/geom_journal.so
./lib/geom/geom_label.so
./lib/geom/geom_mirror.so
./lib/geom/geom_multipath.so
./lib/geom/geom_nop.so
./lib/geom/geom_part.so
./lib/geom/geom_raid3.so
./lib/geom/geom_shsec.so
./lib/geom/geom_stripe.so
./lib/geom/geom_virstor.so
./lib/libc.so.7
./lib/libcrypt.so.5
./lib/libkvm.so.5
./lib/libm.so.5
./lib/libmd.so.5
./lib/libncurses.so.8
./lib/libncursesw.so.8
./lib/libsbuf.so.5
./lib/libutil.so.8
./lib/libalias.so.7
./lib/libalias_cuseeme.so
./lib/libalias_dummy.so
./lib/libalias_ftp.so
./lib/libalias_irc.so
./lib/libalias_nbt.so
./lib/libalias_pptp.so
./lib/libalias_skinny.so
./lib/libalias_smedia.so
./lib/libbegemot.so.4
./lib/libcam.so.5
./lib/libdevstat.so.7
./lib/libedit.so.7
./lib/libbsdxml.so.4
./lib/libgeom.so.5
./lib/libipsec.so.4
./lib/libjail.so.1
./lib/libkiconv.so.4
./lib/libpcap.so.7
./lib/libthr.so.3
./lib/libufs.so.5
./lib/libz.so.5
./lib/libgcc_s.so.1
./lib/libreadline.so.8
./lib/libssp.so.0
./lib/libcrypto.so.6
./libexec
./libexec/ld-elf.so.1
./libexec/ld-elf.so.1.old
./sbin
./sbin/adjkerntz
./sbin/atacontrol
./sbin/bsdlabel
./sbin/camcontrol
./sbin/ccdconfig
./sbin/clri
./sbin/comcontrol
./sbin/conscontrol
./sbin/devd
./sbin/devfs
./sbin/dhclient
./sbin/dhclient-script
./sbin/dmesg
./sbin/dump
./sbin/rdump
./sbin/dumpfs
./sbin/dumpon
./sbin/fdisk
./sbin/ffsinfo
./sbin/fsck
./sbin/fsck_ffs
./sbin/fsck_ufs
./sbin/fsck_4.2bsd
./sbin/fsdb
./sbin/fsirand
./sbin/gbde
./sbin/fsck_msdosfs
./sbin/geom
./sbin/gcache
./sbin/gconcat
./sbin/geli
./sbin/gjournal
./sbin/glabel
./sbin/gmirror
./sbin/gmultipath
./sbin/gnop
./sbin/gpart
./sbin/graid3
./sbin/gshsec
./sbin/gstripe
./sbin/gvirstor
./sbin/ggatec
./sbin/ggated
./sbin/ggatel
./sbin/growfs
./sbin/gvinum
./sbin/ifconfig
./sbin/init
./sbin/ipf
./sbin/ipfs
./sbin/ipfstat
./sbin/ipftest
./sbin/ipmon
./sbin/ipnat
./sbin/ippool
./sbin/md5
./sbin/ipfw
./sbin/ipresend
./sbin/iscontrol
./sbin/kldconfig
./sbin/kldload
./sbin/kldstat
./sbin/kldunload
./sbin/ldconfig
./sbin/rmd160
./sbin/sha1
./sbin/sha256
./sbin/mdconfig
./sbin/mdmfs
./sbin/mount_mfs
./sbin/mknod
./sbin/mksnap_ffs
./sbin/mount
./sbin/mount_cd9660
./sbin/mount_msdosfs
./sbin/mount_nfs
./sbin/mount_newnfs
./sbin/mount_nullfs
./sbin/mount_udf
./sbin/mount_unionfs
./sbin/natd
./sbin/ddb
./sbin/newfs
./sbin/newfs_msdos
./sbin/nfsiod
./sbin/nos-tun
./sbin/pfctl
./sbin/pflogd
./sbin/ping
./sbin/ping6
./sbin/quotacheck
./sbin/rcorder
./sbin/reboot
./sbin/nextboot
./sbin/halt
./sbin/fastboot
./sbin/fasthalt
./sbin/recoverdisk
./sbin/restore
./sbin/rrestore
./sbin/route
./sbin/routed
./sbin/rtquery
./sbin/rtsol
./sbin/savecore
./sbin/setkey
./sbin/shutdown
./sbin/spppcontrol
./sbin/swapon
./sbin/swapoff
./sbin/swapctl
./sbin/sysctl
./sbin/tunefs
./sbin/umount
./sbin/init.bak
./var
./var/crash
./var/crash/minfree
./var/db
./var/db/locate.database
./var/log
./var/log/sendmail.st
./var/named
./var/named/etc
./var/named/etc/namedb
./var/named/etc/namedb/master
./var/named/etc/namedb/master/empty.db
./var/named/etc/namedb/master/localhost-forward.db
./var/named/etc/namedb/master/localhost-reverse.db
./var/named/etc/namedb/named.conf
./var/named/etc/namedb/named.root
./var/yp
./var/yp/Makefile.dist
./var/run
./var/cron
./var/cron/tabs
./root
./root/.k5login
./root/.profile
./root/.cshrc
./root/.login
./list
./dev
./usr
./usr/sbin
./usr/sbin/newsyslog
./usr/sbin/syslogd
./usr/sbin/ip6addrctl
./usr/sbin/sendmail
./usr/sbin/cron
./usr/lib
./usr/lib/libpam.so.5
./usr/lib/libpam.so
./usr/lib/pam_opie.so.5
./usr/lib/libbsm.so.3
./usr/lib/libbsm.so
./usr/lib/pam_chroot.so.5
./usr/lib/pam_tacplus.so.5
./usr/lib/pam_ssh.so.5
./usr/lib/pam_self.so.5
./usr/lib/pam_securetty.so.5
./usr/lib/pam_rootok.so.5
./usr/lib/pam_rhosts.so.5
./usr/lib/pam_radius.so.5
./usr/lib/pam_permit.so.5
./usr/lib/pam_passwdqc.so.5
./usr/lib/libcom_err.so.5
./usr/lib/libcom_err.so
./usr/lib/pam_opieaccess.so.5
./usr/lib/pam_nologin.so.5
./usr/lib/libc.so.7
./usr/lib/pam_login_access.so.5
./usr/lib/pam_lastlog.so.5
./usr/lib/pam_ksu.so.5
./usr/lib/pam_krb5.so.5
./usr/lib/pam_guest.so.5
./usr/lib/pam_group.so.5
./usr/lib/pam_ftpusers.so.5
./usr/lib/pam_exec.so.5
./usr/lib/pam_echo.so.5
./usr/lib/pam_deny.so.5
./usr/lib/pam_unix.so.5
./usr/lib/pam_chroot.so
./usr/lib/libopie.so
./usr/lib/pam_deny.so
./usr/lib/pam_echo.so
./usr/lib/pam_exec.so
./usr/lib/pam_ftpusers.so
./usr/lib/pam_group.so
./usr/lib/pam_guest.so
./usr/lib/pam_krb5.so
./usr/lib/pam_ksu.so
./usr/lib/pam_lastlog.so
./usr/lib/pam_login_access.so
./usr/lib/pam_nologin.so
./usr/lib/pam_opie.so
./usr/lib/pam_opieaccess.so
./usr/lib/pam_passwdqc.so
./usr/lib/pam_permit.so
./usr/lib/pam_radius.so
./usr/lib/pam_rhosts.so
./usr/lib/pam_rootok.so
./usr/lib/pam_securetty.so
./usr/lib/pam_self.so
./usr/lib/pam_ssh.so
./usr/lib/pam_tacplus.so
./usr/lib/pam_unix.so
./usr/lib/libmd.so.5
./usr/lib/libbz2.so.4
./usr/lib/libgnuregex.so.5
./usr/lib/libypclnt.so.4
./usr/bin
./usr/bin/mktemp
./usr/bin/login
./usr/bin/uname
./usr/bin/awk
./usr/bin/logger
./usr/bin/grep
./usr/bin/ftp
./usr/libexec
./usr/libexec/getty

5
sys/mips/rmi/std.xlr
View File

@ -1,5 +0,0 @@
# $FreeBSD$
files "../rmi/files.xlr"
cpu CPU_RMI
option NOFPU

381
sys/mips/rmi/tick.c
View File

@ -1,381 +0,0 @@
/*-
* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
*
* Copyright (c) 2006-2007 Bruce M. Simpson.
* Copyright (c) 2003-2004 Juli Mallett.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
/*
* Simple driver for the 32-bit interval counter built in to all
* MIPS32 CPUs.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/sysctl.h>
#include <sys/bus.h>
#include <sys/kernel.h>
#include <sys/module.h>
#include <sys/rman.h>
#include <sys/power.h>
#include <sys/smp.h>
#include <sys/time.h>
#include <sys/timeet.h>
#include <sys/timetc.h>
#include <machine/hwfunc.h>
#include <machine/clock.h>
#include <machine/locore.h>
#include <machine/md_var.h>
#include <machine/intr_machdep.h>
#include <mips/rmi/interrupt.h>
uint64_t counter_freq;
struct timecounter *platform_timecounter;
static DPCPU_DEFINE(uint32_t, cycles_per_tick);
static uint32_t cycles_per_usec;
static DPCPU_DEFINE(volatile uint32_t, counter_upper);
static DPCPU_DEFINE(volatile uint32_t, counter_lower_last);
static DPCPU_DEFINE(uint32_t, compare_ticks);
static DPCPU_DEFINE(uint32_t, lost_ticks);
struct clock_softc {
int intr_rid;
struct resource *intr_res;
void *intr_handler;
struct timecounter tc;
struct eventtimer et;
};
static struct clock_softc *softc;
/*
* Device methods
*/
static int clock_probe(device_t);
static void clock_identify(driver_t *, device_t);
static int clock_attach(device_t);
static unsigned counter_get_timecount(struct timecounter *tc);
void
mips_timer_early_init(uint64_t clock_hz)
{
/* Initialize clock early so that we can use DELAY sooner */
counter_freq = clock_hz;
cycles_per_usec = (clock_hz / (1000 * 1000));
}
void
platform_initclocks(void)
{
if (platform_timecounter != NULL)
tc_init(platform_timecounter);
}
static uint64_t
tick_ticker(void)
{
uint64_t ret;
uint32_t ticktock;
uint32_t t_lower_last, t_upper;
/*
* Disable preemption because we are working with cpu specific data.
*/
critical_enter();
/*
* Note that even though preemption is disabled, interrupts are
* still enabled. In particular there is a race with clock_intr()
* reading the values of 'counter_upper' and 'counter_lower_last'.
*
* XXX this depends on clock_intr() being executed periodically
* so that 'counter_upper' and 'counter_lower_last' are not stale.
*/
do {
t_upper = DPCPU_GET(counter_upper);
t_lower_last = DPCPU_GET(counter_lower_last);
} while (t_upper != DPCPU_GET(counter_upper));
ticktock = mips_rd_count();
critical_exit();
/* COUNT register wrapped around */
if (ticktock < t_lower_last)
t_upper++;
ret = ((uint64_t)t_upper << 32) | ticktock;
return (ret);
}
void
mips_timer_init_params(uint64_t platform_counter_freq, int double_count)
{
/*
* XXX: Do not use printf here: uart code 8250 may use DELAY so this
* function should be called before cninit.
*/
counter_freq = platform_counter_freq;
/*
* XXX: Some MIPS32 cores update the Count register only every two
* pipeline cycles.
* We know this because of status registers in CP0, make it automatic.
*/
if (double_count != 0)
counter_freq /= 2;
cycles_per_usec = counter_freq / (1 * 1000 * 1000);
set_cputicker(tick_ticker, counter_freq, 1);
}
static int
sysctl_machdep_counter_freq(SYSCTL_HANDLER_ARGS)
{
int error;
uint64_t freq;
if (softc == NULL)
return (EOPNOTSUPP);
freq = counter_freq;
error = sysctl_handle_64(oidp, &freq, sizeof(freq), req);
if (error == 0 && req->newptr != NULL) {
counter_freq = freq;
softc->et.et_frequency = counter_freq;
softc->tc.tc_frequency = counter_freq;
}
return (error);
}
SYSCTL_PROC(_machdep, OID_AUTO, counter_freq, CTLTYPE_U64 | CTLFLAG_RW,
NULL, 0, sysctl_machdep_counter_freq, "QU",
"Timecounter frequency in Hz");
static unsigned
counter_get_timecount(struct timecounter *tc)
{
return (mips_rd_count());
}
/*
* Wait for about n microseconds (at least!).
*/
void
DELAY(int n)
{
uint32_t cur, last, delta, usecs;
TSENTER();
/*
* This works by polling the timer and counting the number of
* microseconds that go by.
*/
last = mips_rd_count();
delta = usecs = 0;
while (n > usecs) {
cur = mips_rd_count();
/* Check to see if the timer has wrapped around. */
if (cur < last)
delta += cur + (0xffffffff - last) + 1;
else
delta += cur - last;
last = cur;
if (delta >= cycles_per_usec) {
usecs += delta / cycles_per_usec;
delta %= cycles_per_usec;
}
}
TSEXIT();
}
static int
clock_start(struct eventtimer *et, sbintime_t first, sbintime_t period)
{
uint32_t fdiv, div, next;
if (period != 0)
div = (et->et_frequency * period) >> 32;
else
div = 0;
if (first != 0)
fdiv = (et->et_frequency * first) >> 32;
else
fdiv = div;
DPCPU_SET(cycles_per_tick, div);
next = mips_rd_count() + fdiv;
DPCPU_SET(compare_ticks, next);
mips_wr_compare(next);
return (0);
}
static int
clock_stop(struct eventtimer *et)
{
DPCPU_SET(cycles_per_tick, 0);
mips_wr_compare(0xffffffff);
return (0);
}
/*
* Device section of file below
*/
static int
clock_intr(void *arg)
{
struct clock_softc *sc = (struct clock_softc *)arg;
uint32_t cycles_per_tick;
uint32_t count, compare_last, compare_next, lost_ticks;
cycles_per_tick = DPCPU_GET(cycles_per_tick);
/*
* Set next clock edge.
*/
count = mips_rd_count();
compare_last = DPCPU_GET(compare_ticks);
if (cycles_per_tick > 0) {
compare_next = count + cycles_per_tick;
DPCPU_SET(compare_ticks, compare_next);
mips_wr_compare(compare_next);
} else /* In one-shot mode timer should be stopped after the event. */
mips_wr_compare(0xffffffff);
/* COUNT register wrapped around */
if (count < DPCPU_GET(counter_lower_last)) {
DPCPU_SET(counter_upper, DPCPU_GET(counter_upper) + 1);
}
DPCPU_SET(counter_lower_last, count);
if (cycles_per_tick > 0) {
/*
* Account for the "lost time" between when the timer interrupt
* fired and when 'clock_intr' actually started executing.
*/
lost_ticks = DPCPU_GET(lost_ticks);
lost_ticks += count - compare_last;
/*
* If the COUNT and COMPARE registers are no longer in sync
* then make up some reasonable value for the 'lost_ticks'.
*
* This could happen, for e.g., after we resume normal
* operations after exiting the debugger.
*/
if (lost_ticks > 2 * cycles_per_tick)
lost_ticks = cycles_per_tick;
while (lost_ticks >= cycles_per_tick) {
if (sc->et.et_active)
sc->et.et_event_cb(&sc->et, sc->et.et_arg);
lost_ticks -= cycles_per_tick;
}
DPCPU_SET(lost_ticks, lost_ticks);
}
if (sc->et.et_active)
sc->et.et_event_cb(&sc->et, sc->et.et_arg);
return (FILTER_HANDLED);
}
static int
clock_probe(device_t dev)
{
device_set_desc(dev, "Generic MIPS32 ticker");
return (BUS_PROBE_NOWILDCARD);
}
static void
clock_identify(driver_t * drv, device_t parent)
{
BUS_ADD_CHILD(parent, 0, "clock", 0);
}
static int
clock_attach(device_t dev)
{
struct clock_softc *sc;
if (device_get_unit(dev) != 0)
panic("can't attach more clocks");
softc = sc = device_get_softc(dev);
cpu_establish_hardintr("compare", clock_intr, NULL,
sc, IRQ_TIMER, INTR_TYPE_CLK, &sc->intr_handler);
sc->tc.tc_get_timecount = counter_get_timecount;
sc->tc.tc_counter_mask = 0xffffffff;
sc->tc.tc_frequency = counter_freq;
sc->tc.tc_name = "MIPS32";
sc->tc.tc_quality = 800;
sc->tc.tc_priv = sc;
tc_init(&sc->tc);
sc->et.et_name = "MIPS32";
sc->et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT |
ET_FLAGS_PERCPU;
sc->et.et_quality = 800;
sc->et.et_frequency = counter_freq;
sc->et.et_min_period = 0x00004000LLU; /* To be safe. */
sc->et.et_max_period = (0xfffffffeLLU << 32) / sc->et.et_frequency;
sc->et.et_start = clock_start;
sc->et.et_stop = clock_stop;
sc->et.et_priv = sc;
et_register(&sc->et);
return (0);
}
static device_method_t clock_methods[] = {
/* Device interface */
DEVMETHOD(device_probe, clock_probe),
DEVMETHOD(device_identify, clock_identify),
DEVMETHOD(device_attach, clock_attach),
DEVMETHOD(device_detach, bus_generic_detach),
DEVMETHOD(device_shutdown, bus_generic_shutdown),
{0, 0}
};
static driver_t clock_driver = {
"clock",
clock_methods,
sizeof(struct clock_softc),
};
static devclass_t clock_devclass;
DRIVER_MODULE(clock, nexus, clock_driver, clock_devclass, 0, 0);

82
sys/mips/rmi/uart_bus_xlr_iodi.c
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@ -1,82 +0,0 @@
/*-
* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
*
* Copyright (c) 2006 Raza Microelectronics
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
* IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
* INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/kernel.h>
#include <sys/module.h>
#include <sys/lock.h>
#include <sys/mutex.h>
#include <machine/bus.h>
#include <sys/rman.h>
#include <machine/resource.h>
#include <mips/rmi/iomap.h>
#include <dev/uart/uart.h>
#include <dev/uart/uart_bus.h>
#include <dev/uart/uart_cpu.h>
static int uart_iodi_probe(device_t dev);
static device_method_t uart_iodi_methods[] = {
/* Device interface */
DEVMETHOD(device_probe, uart_iodi_probe),
DEVMETHOD(device_attach, uart_bus_attach),
DEVMETHOD(device_detach, uart_bus_detach),
{0, 0}
};
static driver_t uart_iodi_driver = {
uart_driver_name,
uart_iodi_methods,
sizeof(struct uart_softc),
};
extern SLIST_HEAD(uart_devinfo_list, uart_devinfo) uart_sysdevs;
static int
uart_iodi_probe(device_t dev)
{
struct uart_softc *sc;
sc = device_get_softc(dev);
sc->sc_sysdev = SLIST_FIRST(&uart_sysdevs);
sc->sc_class = &uart_ns8250_class;
bcopy(&sc->sc_sysdev->bas, &sc->sc_bas, sizeof(sc->sc_bas));
sc->sc_sysdev->bas.bst = rmi_bus_space;
sc->sc_sysdev->bas.bsh = MIPS_PHYS_TO_KSEG1(XLR_UART0ADDR);
sc->sc_bas.bst = rmi_bus_space;
sc->sc_bas.bsh = MIPS_PHYS_TO_KSEG1(XLR_UART0ADDR);
/* regshft = 2, rclk = 66000000, rid = 0, chan = 0 */
return (uart_bus_probe(dev, 2, 0, 66000000, 0, 0));
}
DRIVER_MODULE(uart, iodi, uart_iodi_driver, uart_devclass, 0, 0);

86
sys/mips/rmi/uart_cpu_mips_xlr.c
View File

@ -1,86 +0,0 @@
/*-
* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
*
* Copyright (c) 2006 Wojciech A. Koszek <wkoszek@FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* $Id: uart_cpu_mips_xlr.c,v 1.5 2008-07-16 20:22:39 jayachandranc Exp $
*/
/*
* Skeleton of this file was based on respective code for ARM
* code written by Olivier Houchard.
*/
/*
* XLRMIPS: This file is hacked from arm/...
*/
#include "opt_uart.h"
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/bus.h>
#include <sys/cons.h>
#include <machine/bus.h>
#include <dev/uart/uart.h>
#include <dev/uart/uart_cpu.h>
#include <sys/kdb.h>
#include <sys/kernel.h>
#include <sys/lock.h>
#include <sys/mutex.h>
#include <mips/rmi/iomap.h>
bus_space_tag_t uart_bus_space_io;
bus_space_tag_t uart_bus_space_mem;
int
uart_cpu_eqres(struct uart_bas *b1, struct uart_bas *b2)
{
return ((b1->bsh == b2->bsh && b1->bst == b2->bst) ? 1 : 0);
}
int
uart_cpu_getdev(int devtype, struct uart_devinfo *di)
{
di->ops = uart_getops(&uart_ns8250_class);
di->bas.chan = 0;
di->bas.bst = rmi_bus_space;
di->bas.bsh = MIPS_PHYS_TO_KSEG1(XLR_UART0ADDR);
di->bas.regshft = 2;
/* divisor = rclk / (baudrate * 16); */
di->bas.rclk = 66000000;
di->baudrate = 0;
di->databits = 8;
di->stopbits = 1;
di->parity = UART_PARITY_NONE;
uart_bus_space_io = NULL;
uart_bus_space_mem = rmi_bus_space;
return (0);
}

217
sys/mips/rmi/xlr_csum_nocopy.S
View File

@ -1,217 +0,0 @@
#include <machine/asm.h>
/*
* a0: source address
* a1: length of the area to checksum
* a2: partial checksum
* a3: dst
*/
#define src a0
#define dst a3
#define sum v0
.text
.set noreorder
.macro CSUM_BIGCHUNK_AND_COPY offset
pref 0, (\offset+0x0)(a0)
ld t0, (\offset+0x00)(a0)
ld t1, (\offset+0x08)(a0)
.word 0x70481038 /*daddwc v0, v0, t0 */
.word 0x70491038 /*daddwc v0, v0, t1 */
ld t0, (\offset + 0x10)(a0)
ld t1, (\offset + 0x18)(a0)
.word 0x70481038 /* daddwc v0, v0, t0 */
.word 0x70491038 /*daddwc v0, v0, t1 */
.endm
small_csumcpy: /* unknown src alignment and < 8 bytes to go */
move a1, t2
andi t0, a1, 4
beqz t0, 1f
andi t0, a1, 2
ulw t1, (src) /* Still a full word to go */
daddiu src, 4
.word 0x70491038 /*daddwc v0, v0, t1 */
1: move t1, zero
beqz t0, 1f
andi t0, a1, 1
ulhu t1, (src) /* Still a halfword to go */
daddiu src, 2
1: beqz t0, 1f
sll t1, t1, 16
lbu t2, (src)
nop
#ifdef __MIPSEB__
sll t2, t2, 8
#endif
or t1, t2
1: .word 0x70491038 /*daddwc v0, v0, t1 */
.word 0x70461038 /*daddwc v0, v0, a2 */
.word 0x70401038 /*daddwc v0, v0, $0 */
/* Ideally at this point of time the status flag must be cleared */
dsll32 v1, sum, 0
.word 0x70431038 /*daddwc v0, v0, v1 */
dsrl32 sum, sum, 0
.word 0x70401038 /*daddwc v0, v0, zero */
/* fold the checksum */
sll v1, sum, 16
addu sum, v1
sltu v1, sum, v1
srl sum, sum, 16
addu sum, v1
1:
.set reorder
jr ra
.set noreorder
/* ------------------------------------------------------------------ */
.align 5
LEAF(xlr_csum_partial_nocopy)
move sum, zero
move t7, zero
sltiu t8, a1, 0x8
bnez t8, small_csumcpy /* < 8 bytes to copy */
move t2, a1
beqz a1, out
andi t7, src, 0x1 /* odd buffer? */
hword_align:
beqz t7, word_align
andi t8, src, 0x2
lbu t0, (src)
dsubu a1, a1, 0x1
.word 0x70481038 /*daddwc v0, v0, t0 */
daddu src, src, 0x1
andi t8, src, 0x2
word_align:
beqz t8, dword_align
sltiu t8, a1, 56
lhu t0, (src)
dsubu a1, a1, 0x2
.word 0x70481038 /*daddwc v0, v0, t0 */
sltiu t8, a1, 56
daddu src, src, 0x2
dword_align:
bnez t8, do_end_words
move t8, a1
andi t8, src, 0x4
beqz t8, qword_align
andi t8, src, 0x8
lw t0, 0x00(src)
dsubu a1, a1, 0x4
.word 0x70481038 /*daddwc v0, v0, t0 */
daddu src, src, 0x4
andi t8, src, 0x8
qword_align:
beqz t8, oword_align
andi t8, src, 0x10
ld t0, 0x00(src)
dsubu a1, a1, 0x8
.word 0x70481038 /*daddwc v0, v0, t0 */
daddu src, src, 0x8
andi t8, src, 0x10
oword_align:
beqz t8, begin_movement
dsrl t8, a1, 0x7
ld t3, 0x08(src)
ld t0, 0x00(src)
.word 0x704b1038 /*daddwc v0, v0, t3 */
.word 0x70481038 /*daddwc v0, v0, t0 */
dsubu a1, a1, 0x10
daddu src, src, 0x10
dsrl t8, a1, 0x7
begin_movement:
beqz t8, 1f
andi t2, a1, 0x40
move_128bytes:
pref 0, 0x20(a0)
pref 0, 0x40(a0)
pref 0, 0x60(a0)
CSUM_BIGCHUNK_AND_COPY(0x00)
CSUM_BIGCHUNK_AND_COPY(0x20)
CSUM_BIGCHUNK_AND_COPY(0x40)
CSUM_BIGCHUNK_AND_COPY(0x60)
dsubu t8, t8, 0x01
bnez t8, move_128bytes /* flag */
daddu src, src, 0x80
1:
beqz t2, 1f
andi t2, a1, 0x20
move_64bytes:
pref 0, 0x20(a0)
pref 0, 0x40(a0)
CSUM_BIGCHUNK_AND_COPY(0x00)
CSUM_BIGCHUNK_AND_COPY(0x20)
daddu src, src, 0x40
1:
beqz t2, do_end_words
andi t8, a1, 0x1c
move_32bytes:
pref 0, 0x20(a0)
CSUM_BIGCHUNK_AND_COPY(0x00)
andi t8, a1, 0x1c
daddu src, src, 0x20
do_end_words:
beqz t8, maybe_end_cruft
dsrl t8, t8, 0x2
end_words:
lw t0, (src)
dsubu t8, t8, 0x1
.word 0x70481038 /*daddwc v0, v0, t0 */
bnez t8, end_words
daddu src, src, 0x4
maybe_end_cruft:
andi t2, a1, 0x3
small_memcpy:
j small_csumcpy; move a1, t2
beqz t2, out
move a1, t2
end_bytes:
lb t0, (src)
dsubu a1, a1, 0x1
bnez a2, end_bytes
daddu src, src, 0x1
out:
jr ra
move v0, sum
END(xlr_csum_partial_nocopy)

418
sys/mips/rmi/xlr_i2c.c
View File

@ -1,418 +0,0 @@
/*-
* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright (c) 2003-2009 RMI Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of RMI Corporation, nor the names of its contributors,
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* RMI_BSD */
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
/*
* I2C driver for the Palm-BK3220 I2C Host adapter on the RMI XLR.
*/
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/lock.h>
#include <sys/module.h>
#include <sys/mutex.h>
#include <sys/bus.h>
#include <sys/rman.h>
#include <dev/iicbus/iiconf.h>
#include <dev/iicbus/iicbus.h>
#include <mips/rmi/board.h>
#include <mips/rmi/iomap.h>
#include <mips/include/resource.h>
#include "iicbus_if.h"
/* XLR I2C REGISTERS */
#define XLR_I2C_CFG 0x00
#define XLR_I2C_CLKDIV 0x01
#define XLR_I2C_DEVADDR 0x02
#define XLR_I2C_ADDR 0x03
#define XLR_I2C_DATAOUT 0x04
#define XLR_I2C_DATAIN 0x05
#define XLR_I2C_STATUS 0x06
#define XLR_I2C_STARTXFR 0x07
#define XLR_I2C_BYTECNT 0x08
#define XLR_I2C_HDSTATIM 0x09
/* XLR I2C REGISTERS FLAGS */
#define XLR_I2C_BUS_BUSY 0x01
#define XLR_I2C_SDOEMPTY 0x02
#define XLR_I2C_RXRDY 0x04
#define XLR_I2C_ACK_ERR 0x08
#define XLR_I2C_ARB_STARTERR 0x30
/* Register Programming Values!! Change as required */
#define XLR_I2C_CFG_ADDR 0xF8 /* 8-Bit dev Addr + POR Values */
#define XLR_I2C_CFG_NOADDR 0xFA /* 8-Bit reg Addr + POR Values : No dev addr */
#define XLR_I2C_STARTXFR_ND 0x02 /* No data , only addr */
#define XLR_I2C_STARTXFR_RD 0x01 /* Read */
#define XLR_I2C_STARTXFR_WR 0x00 /* Write */
#define XLR_I2C_CLKDIV_DEF 0x14A /* 0x00000052 */
#define XLR_I2C_HDSTATIM_DEF 0x107 /* 0x00000000 */
#define MAXTIME 0x10000
#define ARIZONA_I2C_BUS 1
static devclass_t xlr_i2c_devclass;
/*
* Device methods
*/
static int xlr_i2c_probe(device_t);
static int xlr_i2c_attach(device_t);
static int xlr_i2c_detach(device_t);
static int xlr_i2c_start(device_t dev, u_char slave, int timeout);
static int xlr_i2c_stop(device_t dev);
static int xlr_i2c_read(device_t dev, char *buf, int len, int *read, int last, int delay);
static int xlr_i2c_write(device_t dev, const char *buf, int len, int *sent, int timeout);
static int xlr_i2c_callback(device_t dev, int index, caddr_t data);
static int xlr_i2c_repeated_start(device_t dev, u_char slave, int timeout);
static int xlr_i2c_transfer(device_t bus, struct iic_msg *msgs, uint32_t nmsgs);
struct xlr_i2c_softc {
device_t dev; /* Self */
struct resource *mem_res; /* Memory resource */
volatile int flags;
int sc_started;
uint8_t i2cdev_addr;
xlr_reg_t *iobase_i2c_regs;
device_t iicbus;
struct mtx sc_mtx;
};
static void
set_i2c_base(device_t dev)
{
struct xlr_i2c_softc *sc;
sc = device_get_softc(dev);
if (device_get_unit(dev) == 0)
sc->iobase_i2c_regs = xlr_io_mmio(XLR_IO_I2C_0_OFFSET);
else
sc->iobase_i2c_regs = xlr_io_mmio(XLR_IO_I2C_1_OFFSET);
}
static void
xlr_i2c_dev_write(device_t dev, int reg, int value)
{
struct xlr_i2c_softc *sc;
sc = device_get_softc(dev);
xlr_write_reg(sc->iobase_i2c_regs, reg, value);
return;
}
static int
xlr_i2c_dev_read(device_t dev, int reg)
{
uint32_t val;
struct xlr_i2c_softc *sc;
sc = device_get_softc(dev);
val = xlr_read_reg(sc->iobase_i2c_regs, reg);
return ((int)val);
}
static int
xlr_i2c_probe(device_t dev)
{
device_set_desc(dev, "XLR/XLS I2C bus controller");
return (0);
}
/*
* We add all the devices which we know about.
* The generic attach routine will attach them if they are alive.
*/
static int
xlr_i2c_attach(device_t dev)
{
int rid;
struct xlr_i2c_softc *sc;
device_t tmpd;
if(device_get_unit(dev)!=ARIZONA_I2C_BUS) {
device_printf(dev, "unused iicbus instance\n");
return 0;
}
sc = device_get_softc(dev);
set_i2c_base(dev);
mtx_init(&sc->sc_mtx, "xlr_i2c", "xlr_i2c", MTX_DEF);
sc->mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
if (sc->mem_res == NULL) {
printf("not able to allocate the bus resource\n");
}
if ((sc->iicbus = device_add_child(dev, "iicbus", -1)) == NULL) {
printf("could not allocate iicbus instance\n");
return -1;
}
if(xlr_board_info.xlr_i2c_device[I2C_RTC].enabled == 1) {
tmpd = device_add_child(sc->iicbus, "ds13rtc", 0);
device_set_ivars(tmpd, &xlr_board_info.xlr_i2c_device[I2C_RTC]);
}
if(xlr_board_info.xlr_i2c_device[I2C_THERMAL].enabled == 1) {
tmpd = device_add_child(sc->iicbus, "max6657", 0);
device_set_ivars(tmpd, &xlr_board_info.xlr_i2c_device[I2C_THERMAL]);
}
if(xlr_board_info.xlr_i2c_device[I2C_EEPROM].enabled == 1) {
tmpd = device_add_child(sc->iicbus, "at24co2n", 0);
device_set_ivars(tmpd, &xlr_board_info.xlr_i2c_device[I2C_EEPROM]);
}
/*
* The old ds1374 rtc driver only handled one chip type. The new
* ds13rtc driver handles all ds13xx chips, but must be told the chip
* type via hints. XLR historically hasn't had a standard hints file,
* so set up the hint now if it isn't already there.
*/
#define HINTNAME "hint.ds13rtc.0.compatible"
if (!testenv(HINTNAME))
kern_setenv(HINTNAME, "dallas,ds1374");
bus_generic_attach(dev);
return (0);
}
static int
xlr_i2c_detach(device_t dev)
{
bus_generic_detach(dev);
return (0);
}
static int
xlr_i2c_start(device_t dev, u_char slave, int timeout)
{
int error = 0;
struct xlr_i2c_softc *sc;
sc = device_get_softc(dev);
mtx_lock(&sc->sc_mtx);
sc->sc_started = 1;
sc->i2cdev_addr = (slave >> 1);
return error;
}
static int
xlr_i2c_stop(device_t dev)
{
int error = 0;
struct xlr_i2c_softc *sc;
sc = device_get_softc(dev);
mtx_unlock(&sc->sc_mtx);
return error;
}
static int
xlr_i2c_read(device_t dev, char *buf, int len, int *read, int last,
int delay)
{
volatile uint32_t i2c_status = 0;
int pos=0;
int timeout = 0;
xlr_i2c_dev_write(dev, XLR_I2C_CFG, XLR_I2C_CFG_NOADDR);
xlr_i2c_dev_write(dev, XLR_I2C_BYTECNT, len);
retry:
xlr_i2c_dev_write(dev, XLR_I2C_STARTXFR, XLR_I2C_STARTXFR_RD);
timeout = 0;
while(1) {
if(timeout++ > MAXTIME)
return -1;
i2c_status = xlr_i2c_dev_read(dev, XLR_I2C_STATUS);
if (i2c_status & XLR_I2C_RXRDY)
buf[pos++] = (uint8_t) xlr_i2c_dev_read(dev, XLR_I2C_DATAIN);
/* ACKERR -- bail */
if (i2c_status & XLR_I2C_ACK_ERR)
return -1; /* ACK_ERROR */
/* LOST ARB or STARTERR -- repeat */
if (i2c_status & XLR_I2C_ARB_STARTERR)
goto retry;
/* Wait for busy bit to go away */
if (i2c_status & XLR_I2C_BUS_BUSY)
continue;
if (pos == len)
break;
}
*read = pos;
return 0;
}
static int
xlr_i2c_write(device_t dev, const char *buf, int len, int *sent, int timeout /* us */ )
{
volatile uint32_t i2c_status = 0x00;
uint8_t devaddr, addr;
struct xlr_i2c_softc *sc;
int pos;
sc = device_get_softc(dev);
/* the first byte of write is addr (of register in device) */
addr = buf[0];
devaddr = sc->i2cdev_addr;
xlr_i2c_dev_write(dev, XLR_I2C_ADDR, addr);
xlr_i2c_dev_write(dev, XLR_I2C_DEVADDR, devaddr);
xlr_i2c_dev_write(dev, XLR_I2C_CFG, XLR_I2C_CFG_ADDR);
xlr_i2c_dev_write(dev, XLR_I2C_BYTECNT, len - 1);
retry:
pos = 1;
if (len == 1) /* there is no data only address */
xlr_i2c_dev_write(dev, XLR_I2C_STARTXFR, XLR_I2C_STARTXFR_ND);
else {
xlr_i2c_dev_write(dev, XLR_I2C_STARTXFR, XLR_I2C_STARTXFR_WR);
xlr_i2c_dev_write(dev, XLR_I2C_DATAOUT, buf[pos]);
}
while (1) {
i2c_status = xlr_i2c_dev_read(dev, XLR_I2C_STATUS);
/* sdo empty send next byte */
if (i2c_status & XLR_I2C_SDOEMPTY) {
pos++;
xlr_i2c_dev_write(dev, XLR_I2C_DATAOUT, buf[pos]);
}
/* LOST ARB or STARTERR -- repeat */
if (i2c_status & XLR_I2C_ARB_STARTERR)
goto retry;
/* ACKERR -- bail */
if (i2c_status & XLR_I2C_ACK_ERR) {
printf("ACK ERR : exiting\n ");
return -1;
}
/* busy try again */
if (i2c_status & XLR_I2C_BUS_BUSY)
continue;
if (pos >= len)
break;
}
*sent = len - 1;
return 0;
}
static int
xlr_i2c_callback(device_t dev, int index, caddr_t data)
{
return 0;
}
static int
xlr_i2c_repeated_start(device_t dev, u_char slave, int timeout)
{
return 0;
}
/*
* I2C bus transfer for RMI boards and devices.
* Generic version of iicbus_transfer that calls the appropriate
* routines to accomplish this. See note above about acceptable
* buffer addresses.
*/
int
xlr_i2c_transfer(device_t bus, struct iic_msg *msgs, uint32_t nmsgs)
{
int i, error, lenread, lenwrote;
u_char addr;
addr = msgs[0].slave | LSB;
error = xlr_i2c_start(bus, addr, 0);
for (i = 0, error = 0; i < nmsgs && error == 0; i++) {
if (msgs[i].flags & IIC_M_RD) {
error = xlr_i2c_read((bus), msgs[i].buf, msgs[i].len, &lenread, IIC_LAST_READ, 0);
}
else {
error = xlr_i2c_write((bus), msgs[i].buf, msgs[i].len, &lenwrote, 0);
}
}
error = xlr_i2c_stop(bus);
return (error);
}
static device_method_t xlr_i2c_methods[] = {
/* device interface */
DEVMETHOD(device_probe, xlr_i2c_probe),
DEVMETHOD(device_attach, xlr_i2c_attach),
DEVMETHOD(device_detach, xlr_i2c_detach),
/* iicbus interface */
DEVMETHOD(iicbus_callback, xlr_i2c_callback),
DEVMETHOD(iicbus_repeated_start, xlr_i2c_repeated_start),
DEVMETHOD(iicbus_start, xlr_i2c_start),
DEVMETHOD(iicbus_stop, xlr_i2c_stop),
DEVMETHOD(iicbus_write, xlr_i2c_write),
DEVMETHOD(iicbus_read, xlr_i2c_read),
DEVMETHOD(iicbus_transfer, xlr_i2c_transfer),
{0, 0}
};
static driver_t xlr_i2c_driver = {
"xlr_i2c",
xlr_i2c_methods,
sizeof(struct xlr_i2c_softc),
};
DRIVER_MODULE(xlr_i2c, iodi, xlr_i2c_driver, xlr_i2c_devclass, 0, 0);
DRIVER_MODULE(iicbus, xlr_i2c, iicbus_driver, iicbus_devclass, 0, 0);

626
sys/mips/rmi/xlr_machdep.c
View File

@ -1,626 +0,0 @@
/*-
* SPDX-License-Identifier: BSD-2-Clause-FreeBSD
*
* Copyright (c) 2006-2009 RMI Corporation
* Copyright (c) 2002-2004 Juli Mallett <jmallett@FreeBSD.org>
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include "opt_ddb.h"
#include <sys/param.h>
#include <sys/bus.h>
#include <sys/conf.h>
#include <sys/rtprio.h>
#include <sys/systm.h>
#include <sys/interrupt.h>
#include <sys/limits.h>
#include <sys/lock.h>
#include <sys/malloc.h>
#include <sys/mutex.h>
#include <sys/random.h>
#include <sys/cons.h> /* cinit() */
#include <sys/kdb.h>
#include <sys/reboot.h>
#include <sys/queue.h>
#include <sys/smp.h>
#include <sys/timetc.h>
#include <vm/vm.h>
#include <vm/vm_page.h>
#include <machine/cpu.h>
#include <machine/cpufunc.h>
#include <machine/cpuinfo.h>
#include <machine/cpuregs.h>
#include <machine/frame.h>
#include <machine/hwfunc.h>
#include <machine/md_var.h>
#include <machine/asm.h>
#include <machine/pmap.h>
#include <machine/trap.h>
#include <machine/clock.h>
#include <machine/fls64.h>
#include <machine/intr_machdep.h>
#include <machine/smp.h>
#include <mips/rmi/iomap.h>
#include <mips/rmi/msgring.h>
#include <mips/rmi/interrupt.h>
#include <mips/rmi/pic.h>
#include <mips/rmi/board.h>
#include <mips/rmi/rmi_mips_exts.h>
#include <mips/rmi/rmi_boot_info.h>
void mpwait(void);
unsigned long xlr_io_base = (unsigned long)(DEFAULT_XLR_IO_BASE);
/* 4KB static data aread to keep a copy of the bootload env until
the dynamic kenv is setup */
char boot1_env[4096];
int rmi_spin_mutex_safe=0;
struct mtx xlr_pic_lock;
/*
* Parameters from boot loader
*/
struct boot1_info xlr_boot1_info;
int xlr_run_mode;
int xlr_argc;
int32_t *xlr_argv, *xlr_envp;
uint64_t cpu_mask_info;
uint32_t xlr_online_cpumask;
uint32_t xlr_core_cpu_mask = 0x1; /* Core 0 thread 0 is always there */
int xlr_shtlb_enabled;
int xlr_ncores;
int xlr_threads_per_core;
uint32_t xlr_hw_thread_mask;
int xlr_cpuid_to_hwtid[MAXCPU];
int xlr_hwtid_to_cpuid[MAXCPU];
static void
xlr_setup_mmu_split(void)
{
uint64_t mmu_setup;
int val = 0;
if (xlr_threads_per_core == 4 && xlr_shtlb_enabled == 0)
return; /* no change from boot setup */
switch (xlr_threads_per_core) {
case 1:
val = 0; break;
case 2:
val = 2; break;
case 4:
val = 3; break;
}
mmu_setup = read_xlr_ctrl_register(4, 0);
mmu_setup = mmu_setup & ~0x06;
mmu_setup |= (val << 1);
/* turn on global mode */
if (xlr_shtlb_enabled)
mmu_setup |= 0x01;
write_xlr_ctrl_register(4, 0, mmu_setup);
}
static void
xlr_parse_mmu_options(void)
{
#ifdef notyet
char *hw_env, *start, *end;
#endif
uint32_t cpu_map;
uint8_t core0_thr_mask, core_thr_mask;
int i, j, k;
/* First check for the shared TLB setup */
xlr_shtlb_enabled = 0;
#ifdef notyet
/*
* We don't support sharing TLB per core - TODO
*/
xlr_shtlb_enabled = 0;
if ((hw_env = kern_getenv("xlr.shtlb")) != NULL) {
start = hw_env;
tmp = strtoul(start, &end, 0);
if (start != end)
xlr_shtlb_enabled = (tmp != 0);
else
printf("Bad value for xlr.shtlb [%s]\n", hw_env);
freeenv(hw_env);
}
#endif
/*
* XLR supports splitting the 64 TLB entries across one, two or four
* threads (split mode). XLR also allows the 64 TLB entries to be shared
* across all threads in the core using a global flag (shared TLB mode).
* We will support 1/2/4 threads in split mode or shared mode.
*
*/
xlr_ncores = 1;
cpu_map = xlr_boot1_info.cpu_online_map;
#ifndef SMP /* Uniprocessor! */
if (cpu_map != 0x1) {
printf("WARNING: Starting uniprocessor kernel on cpumask [0x%lx]!\n"
"WARNING: Other CPUs will be unused.\n", (u_long)cpu_map);
cpu_map = 0x1;
}
#endif
core0_thr_mask = cpu_map & 0xf;
switch (core0_thr_mask) {
case 1:
xlr_threads_per_core = 1; break;
case 3:
xlr_threads_per_core = 2; break;
case 0xf:
xlr_threads_per_core = 4; break;
default:
goto unsupp;
}
/* Verify other cores CPU masks */
for (i = 1; i < XLR_MAX_CORES; i++) {
core_thr_mask = (cpu_map >> (i*4)) & 0xf;
if (core_thr_mask) {
if (core_thr_mask != core0_thr_mask)
goto unsupp;
xlr_ncores++;
}
}
xlr_hw_thread_mask = cpu_map;
/* setup hardware processor id to cpu id mapping */
for (i = 0; i< MAXCPU; i++)
xlr_cpuid_to_hwtid[i] =
xlr_hwtid_to_cpuid [i] = -1;
for (i = 0, k = 0; i < XLR_MAX_CORES; i++) {
if (((cpu_map >> (i*4)) & 0xf) == 0)
continue;
for (j = 0; j < xlr_threads_per_core; j++) {
xlr_cpuid_to_hwtid[k] = i*4 + j;
xlr_hwtid_to_cpuid[i*4 + j] = k;
k++;
}
}
/* setup for the startup core */
xlr_setup_mmu_split();
return;
unsupp:
printf("ERROR : Unsupported CPU mask [use 1,2 or 4 threads per core].\n"
"\tcore0 thread mask [%lx], boot cpu mask [%lx]\n"
"\tUsing default, 16 TLB entries per CPU, split mode\n",
(u_long)core0_thr_mask, (u_long)cpu_map);
panic("Invalid CPU mask - halting.\n");
return;
}
static void
xlr_set_boot_flags(void)
{
char *p;
p = kern_getenv("bootflags");
if (p == NULL)
p = kern_getenv("boot_flags"); /* old style */
if (p == NULL)
return;
for (; p && *p != '\0'; p++) {
switch (*p) {
case 'd':
case 'D':
boothowto |= RB_KDB;
break;
case 'g':
case 'G':
boothowto |= RB_GDB;
break;
case 'v':
case 'V':
boothowto |= RB_VERBOSE;
break;
case 's': /* single-user (default, supported for sanity) */
case 'S':
boothowto |= RB_SINGLE;
break;
default:
printf("Unrecognized boot flag '%c'.\n", *p);
break;
}
}
freeenv(p);
return;
}
extern uint32_t _end;
static void
mips_init(void)
{
init_param1();
init_param2(physmem);
mips_cpu_init();
cpuinfo.cache_coherent_dma = TRUE;
pmap_bootstrap();
#ifdef DDB
kdb_init();
if (boothowto & RB_KDB) {
kdb_enter("Boot flags requested debugger", NULL);
}
#endif
mips_proc0_init();
mutex_init();
}
u_int
platform_get_timecount(struct timecounter *tc __unused)
{
return (0xffffffffU - pic_timer_count32(PIC_CLOCK_TIMER));
}
static void
xlr_pic_init(void)
{
struct timecounter pic_timecounter = {
platform_get_timecount, /* get_timecount */
0, /* no poll_pps */
~0U, /* counter_mask */
PIC_TIMER_HZ, /* frequency */
"XLRPIC", /* name */
2000, /* quality (adjusted in code) */
};
xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_PIC_OFFSET);
int i, irq;
write_c0_eimr64(0ULL);
mtx_init(&xlr_pic_lock, "pic", NULL, MTX_SPIN);
xlr_write_reg(mmio, PIC_CTRL, 0);
/* Initialize all IRT entries */
for (i = 0; i < PIC_NUM_IRTS; i++) {
irq = PIC_INTR_TO_IRQ(i);
/*
* Disable all IRTs. Set defaults (local scheduling, high
* polarity, level * triggered, and CPU irq)
*/
xlr_write_reg(mmio, PIC_IRT_1(i), (1 << 30) | (1 << 6) | irq);
/* Bind all PIC irqs to cpu 0 */
xlr_write_reg(mmio, PIC_IRT_0(i), 0x01);
}
/* Setup timer 7 of PIC as a timestamp, no interrupts */
pic_init_timer(PIC_CLOCK_TIMER);
pic_set_timer(PIC_CLOCK_TIMER, ~UINT64_C(0));
platform_timecounter = &pic_timecounter;
}
static void
xlr_mem_init(void)
{
struct xlr_boot1_mem_map *boot_map;
vm_size_t physsz = 0;
int i, j;
/* get physical memory info from boot loader */
boot_map = (struct xlr_boot1_mem_map *)
(unsigned long)xlr_boot1_info.psb_mem_map;
for (i = 0, j = 0; i < boot_map->num_entries; i++, j += 2) {
if (boot_map->physmem_map[i].type != BOOT1_MEM_RAM)
continue;
if (j == 14) {
printf("*** ERROR *** memory map too large ***\n");
break;
}
if (j == 0) {
/* start after kernel end */
phys_avail[0] = (vm_paddr_t)
MIPS_KSEG0_TO_PHYS(&_end) + 0x20000;
/* boot loader start */
/* HACK to Use bootloaders memory region */
if (boot_map->physmem_map[0].size == 0x0c000000) {
boot_map->physmem_map[0].size = 0x0ff00000;
}
phys_avail[1] = boot_map->physmem_map[0].addr +
boot_map->physmem_map[0].size;
printf("First segment: addr:%#jx -> %#jx \n",
(uintmax_t)phys_avail[0],
(uintmax_t)phys_avail[1]);
dump_avail[0] = phys_avail[0];
dump_avail[1] = phys_avail[1];
} else {
#if !defined(__mips_n64) && !defined(__mips_n32) /* !PHYSADDR_64_BIT */
/*
* In 32 bit physical address mode we cannot use
* mem > 0xffffffff
*/
if (boot_map->physmem_map[i].addr > 0xfffff000U) {
printf("Memory: start %#jx size %#jx ignored"
"(>4GB)\n",
(intmax_t)boot_map->physmem_map[i].addr,
(intmax_t)boot_map->physmem_map[i].size);
continue;
}
if (boot_map->physmem_map[i].addr +
boot_map->physmem_map[i].size > 0xfffff000U) {
boot_map->physmem_map[i].size = 0xfffff000U -
boot_map->physmem_map[i].addr;
printf("Memory: start %#jx limited to 4GB\n",
(intmax_t)boot_map->physmem_map[i].addr);
}
#endif /* !PHYSADDR_64_BIT */
phys_avail[j] = (vm_paddr_t)
boot_map->physmem_map[i].addr;
phys_avail[j + 1] = phys_avail[j] +
boot_map->physmem_map[i].size;
printf("Next segment : addr:%#jx -> %#jx\n",
(uintmax_t)phys_avail[j],
(uintmax_t)phys_avail[j+1]);
}
dump_avail[j] = phys_avail[j];
dump_avail[j+1] = phys_avail[j+1];
physsz += boot_map->physmem_map[i].size;
}
phys_avail[j] = phys_avail[j + 1] = 0;
realmem = physmem = btoc(physsz);
}
void
platform_start(__register_t a0 __unused,
__register_t a1 __unused,
__register_t a2 __unused,
__register_t a3 __unused)
{
int i;
#ifdef SMP
uint32_t tmp;
void (*wakeup) (void *, void *, unsigned int);
#endif
/* Save boot loader and other stuff from scratch regs */
xlr_boot1_info = *(struct boot1_info *)(intptr_t)(int)read_c0_register32(MIPS_COP_0_OSSCRATCH, 0);
cpu_mask_info = read_c0_register64(MIPS_COP_0_OSSCRATCH, 1);
xlr_online_cpumask = read_c0_register32(MIPS_COP_0_OSSCRATCH, 2);
xlr_run_mode = read_c0_register32(MIPS_COP_0_OSSCRATCH, 3);
xlr_argc = read_c0_register32(MIPS_COP_0_OSSCRATCH, 4);
/*
* argv and envp are passed in array of 32bit pointers
*/
xlr_argv = (int32_t *)(intptr_t)(int)read_c0_register32(MIPS_COP_0_OSSCRATCH, 5);
xlr_envp = (int32_t *)(intptr_t)(int)read_c0_register32(MIPS_COP_0_OSSCRATCH, 6);
/* Initialize pcpu stuff */
mips_pcpu0_init();
/* initialize console so that we have printf */
boothowto |= (RB_SERIAL | RB_MULTIPLE); /* Use multiple consoles */
/* clockrate used by delay, so initialize it here */
cpu_clock = xlr_boot1_info.cpu_frequency / 1000000;
/*
* Note the time counter on CPU0 runs not at system clock speed, but
* at PIC time counter speed (which is returned by
* platform_get_frequency(). Thus we do not use
* xlr_boot1_info.cpu_frequency here.
*/
mips_timer_early_init(xlr_boot1_info.cpu_frequency);
/* Init console please */
cninit();
init_static_kenv(boot1_env, sizeof(boot1_env));
printf("Environment (from %d args):\n", xlr_argc - 1);
if (xlr_argc == 1)
printf("\tNone\n");
for (i = 1; i < xlr_argc; i++) {
char *n, *arg;
arg = (char *)(intptr_t)xlr_argv[i];
printf("\t%s\n", arg);
n = strsep(&arg, "=");
if (arg == NULL)
kern_setenv(n, "1");
else
kern_setenv(n, arg);
}
xlr_set_boot_flags();
xlr_parse_mmu_options();
xlr_mem_init();
/* Set up hz, among others. */
mips_init();
#ifdef SMP
/*
* If thread 0 of any core is not available then mark whole core as
* not available
*/
tmp = xlr_boot1_info.cpu_online_map;
for (i = 4; i < MAXCPU; i += 4) {
if ((tmp & (0xf << i)) && !(tmp & (0x1 << i))) {
/*
* Oops.. thread 0 is not available. Disable whole
* core
*/
tmp = tmp & ~(0xf << i);
printf("WARNING: Core %d is disabled because thread 0"
" of this core is not enabled.\n", i / 4);
}
}
xlr_boot1_info.cpu_online_map = tmp;
/* Wakeup Other cpus, and put them in bsd park code. */
wakeup = ((void (*) (void *, void *, unsigned int))
(unsigned long)(xlr_boot1_info.wakeup));
printf("Waking up CPUs 0x%jx.\n",
(intmax_t)xlr_boot1_info.cpu_online_map & ~(0x1U));
if (xlr_boot1_info.cpu_online_map & ~(0x1U))
wakeup(mpwait, 0,
(unsigned int)xlr_boot1_info.cpu_online_map);
#endif
/* xlr specific post initialization */
/* initialize other on chip stuff */
xlr_board_info_setup();
xlr_msgring_config();
xlr_pic_init();
xlr_msgring_cpu_init();
mips_timer_init_params(xlr_boot1_info.cpu_frequency, 0);
printf("Platform specific startup now completes\n");
}
void
platform_cpu_init()
{
}
void
platform_reset(void)
{
xlr_reg_t *mmio = xlr_io_mmio(XLR_IO_GPIO_OFFSET);
/* write 1 to GPIO software reset register */
xlr_write_reg(mmio, 8, 1);
}
#ifdef SMP
int xlr_ap_release[MAXCPU];
int
platform_start_ap(int cpuid)
{
int hwid = xlr_cpuid_to_hwtid[cpuid];
if (xlr_boot1_info.cpu_online_map & (1<<hwid)) {
/*
* other cpus are enabled by the boot loader and they will be
* already looping in mpwait, release them
*/
atomic_store_rel_int(&xlr_ap_release[hwid], 1);
return (0);
} else
return (-1);
}
void
platform_init_ap(int cpuid)
{
uint32_t stat;
/* The first thread has to setup the core MMU split */
if (xlr_thr_id() == 0)
xlr_setup_mmu_split();
/* Setup interrupts for secondary CPUs here */
stat = mips_rd_status();
KASSERT((stat & MIPS_SR_INT_IE) == 0,
("Interrupts enabled in %s!", __func__));
stat |= MIPS_SR_COP_2_BIT | MIPS_SR_COP_0_BIT;
mips_wr_status(stat);
write_c0_eimr64(0ULL);
xlr_enable_irq(IRQ_IPI);
xlr_enable_irq(IRQ_TIMER);
if (xlr_thr_id() == 0)
xlr_msgring_cpu_init();
xlr_enable_irq(IRQ_MSGRING);
return;
}
int
platform_ipi_hardintr_num(void)
{
return (IRQ_IPI);
}
int
platform_ipi_softintr_num(void)
{
return (-1);
}
void
platform_ipi_send(int cpuid)
{
pic_send_ipi(xlr_cpuid_to_hwtid[cpuid], platform_ipi_hardintr_num());
}
void
platform_ipi_clear(void)
{
}
int
platform_processor_id(void)
{
return (xlr_hwtid_to_cpuid[xlr_cpu_id()]);
}
void
platform_cpu_mask(cpuset_t *mask)
{
int i, s;
CPU_ZERO(mask);
s = xlr_ncores * xlr_threads_per_core;
for (i = 0; i < s; i++)
CPU_SET(i, mask);
}
struct cpu_group *
platform_smp_topo()
{
return (smp_topo_2level(CG_SHARE_L2, xlr_ncores, CG_SHARE_L1,
xlr_threads_per_core, CG_FLAG_THREAD));
}
#endif

659
sys/mips/rmi/xlr_pci.c
View File

@ -1,659 +0,0 @@
/*-
* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright (c) 2003-2009 RMI Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of RMI Corporation, nor the names of its contributors,
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* RMI_BSD */
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/types.h>
#include <sys/kernel.h>
#include <sys/module.h>
#include <sys/malloc.h>
#include <sys/bus.h>
#include <sys/endian.h>
#include <sys/rman.h>
#include <vm/vm.h>
#include <vm/vm_param.h>
#include <vm/pmap.h>
#include <dev/pci/pcivar.h>
#include <dev/pci/pcireg.h>
#include <machine/bus.h>
#include <machine/md_var.h>
#include <machine/intr_machdep.h>
#include <machine/cpuregs.h>
#include <mips/rmi/rmi_mips_exts.h>
#include <mips/rmi/interrupt.h>
#include <mips/rmi/iomap.h>
#include <mips/rmi/pic.h>
#include <mips/rmi/board.h>
#include <mips/rmi/pcibus.h>
#include "pcib_if.h"
#include <dev/pci/pcib_private.h>
#define pci_cfg_offset(bus,slot,devfn,where) (((bus)<<16) + ((slot) << 11)+((devfn)<<8)+(where))
#define PCIE_LINK_STATE 0x4000
#define LSU_CFG0_REGID 0
#define LSU_CERRLOG_REGID 9
#define LSU_CERROVF_REGID 10
#define LSU_CERRINT_REGID 11
/* MSI support */
#define MSI_MIPS_ADDR_DEST 0x000ff000
#define MSI_MIPS_ADDR_RH 0x00000008
#define MSI_MIPS_ADDR_RH_OFF 0x00000000
#define MSI_MIPS_ADDR_RH_ON 0x00000008
#define MSI_MIPS_ADDR_DM 0x00000004
#define MSI_MIPS_ADDR_DM_PHYSICAL 0x00000000
#define MSI_MIPS_ADDR_DM_LOGICAL 0x00000004
/* Fields in data for Intel MSI messages. */
#define MSI_MIPS_DATA_TRGRMOD 0x00008000 /* Trigger mode */
#define MSI_MIPS_DATA_TRGREDG 0x00000000 /* edge */
#define MSI_MIPS_DATA_TRGRLVL 0x00008000 /* level */
#define MSI_MIPS_DATA_LEVEL 0x00004000 /* Polarity. */
#define MSI_MIPS_DATA_DEASSERT 0x00000000
#define MSI_MIPS_DATA_ASSERT 0x00004000
#define MSI_MIPS_DATA_DELMOD 0x00000700 /* Delivery Mode */
#define MSI_MIPS_DATA_DELFIXED 0x00000000 /* fixed */
#define MSI_MIPS_DATA_DELLOPRI 0x00000100 /* lowest priority */
#define MSI_MIPS_DATA_INTVEC 0x000000ff
/*
* Build Intel MSI message and data values from a source. AMD64 systems
* seem to be compatible, so we use the same function for both.
*/
#define MIPS_MSI_ADDR(cpu) \
(MSI_MIPS_ADDR_BASE | (cpu) << 12 | \
MSI_MIPS_ADDR_RH_OFF | MSI_MIPS_ADDR_DM_PHYSICAL)
#define MIPS_MSI_DATA(irq) \
(MSI_MIPS_DATA_TRGRLVL | MSI_MIPS_DATA_DELFIXED | \
MSI_MIPS_DATA_ASSERT | (irq))
struct xlr_pcib_softc {
bus_dma_tag_t sc_pci_dmat; /* PCI DMA tag pointer */
};
static devclass_t pcib_devclass;
static void *xlr_pci_config_base;
static struct rman irq_rman, port_rman, mem_rman;
static void
xlr_pci_init_resources(void)
{
irq_rman.rm_start = 0;
irq_rman.rm_end = 255;
irq_rman.rm_type = RMAN_ARRAY;
irq_rman.rm_descr = "PCI Mapped Interrupts";
if (rman_init(&irq_rman)
|| rman_manage_region(&irq_rman, 0, 255))
panic("pci_init_resources irq_rman");
port_rman.rm_type = RMAN_ARRAY;
port_rman.rm_descr = "I/O ports";
if (rman_init(&port_rman)
|| rman_manage_region(&port_rman, 0x10000000, 0x1fffffff))
panic("pci_init_resources port_rman");
mem_rman.rm_type = RMAN_ARRAY;
mem_rman.rm_descr = "I/O memory";
if (rman_init(&mem_rman)
|| rman_manage_region(&mem_rman, 0xd0000000, 0xdfffffff))
panic("pci_init_resources mem_rman");
}
static int
xlr_pcib_probe(device_t dev)
{
if (xlr_board_info.is_xls)
device_set_desc(dev, "XLS PCIe bus");
else
device_set_desc(dev, "XLR PCI bus");
xlr_pci_init_resources();
xlr_pci_config_base = (void *)MIPS_PHYS_TO_KSEG1(DEFAULT_PCI_CONFIG_BASE);
return (0);
}
static int
xlr_pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
{
switch (which) {
case PCIB_IVAR_DOMAIN:
*result = 0;
return (0);
case PCIB_IVAR_BUS:
*result = 0;
return (0);
}
return (ENOENT);
}
static int
xlr_pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t result)
{
switch (which) {
case PCIB_IVAR_DOMAIN:
return (EINVAL);
case PCIB_IVAR_BUS:
return (EINVAL);
}
return (ENOENT);
}
static int
xlr_pcib_maxslots(device_t dev)
{
return (PCI_SLOTMAX);
}
static __inline__ void
disable_and_clear_cache_error(void)
{
uint64_t lsu_cfg0;
lsu_cfg0 = read_xlr_ctrl_register(CPU_BLOCKID_LSU, LSU_CFG0_REGID);
lsu_cfg0 = lsu_cfg0 & ~0x2e;
write_xlr_ctrl_register(CPU_BLOCKID_LSU, LSU_CFG0_REGID, lsu_cfg0);
/* Clear cache error log */
write_xlr_ctrl_register(CPU_BLOCKID_LSU, LSU_CERRLOG_REGID, 0);
}
static __inline__ void
clear_and_enable_cache_error(void)
{
uint64_t lsu_cfg0 = 0;
/* first clear the cache error logging register */
write_xlr_ctrl_register(CPU_BLOCKID_LSU, LSU_CERRLOG_REGID, 0);
write_xlr_ctrl_register(CPU_BLOCKID_LSU, LSU_CERROVF_REGID, 0);
write_xlr_ctrl_register(CPU_BLOCKID_LSU, LSU_CERRINT_REGID, 0);
lsu_cfg0 = read_xlr_ctrl_register(CPU_BLOCKID_LSU, LSU_CFG0_REGID);
lsu_cfg0 = lsu_cfg0 | 0x2e;
write_xlr_ctrl_register(CPU_BLOCKID_LSU, LSU_CFG0_REGID, lsu_cfg0);
}
static uint32_t
pci_cfg_read_32bit(uint32_t addr)
{
uint32_t temp = 0;
uint32_t *p = (uint32_t *)xlr_pci_config_base + addr / sizeof(uint32_t);
uint64_t cerr_cpu_log = 0;
disable_and_clear_cache_error();
temp = bswap32(*p);
/* Read cache err log */
cerr_cpu_log = read_xlr_ctrl_register(CPU_BLOCKID_LSU,
LSU_CERRLOG_REGID);
if (cerr_cpu_log) {
/* Device don't exist. */
temp = ~0x0;
}
clear_and_enable_cache_error();
return (temp);
}
static u_int32_t
xlr_pcib_read_config(device_t dev, u_int b, u_int s, u_int f,
u_int reg, int width)
{
uint32_t data = 0;
if ((width == 2) && (reg & 1))
return 0xFFFFFFFF;
else if ((width == 4) && (reg & 3))
return 0xFFFFFFFF;
data = pci_cfg_read_32bit(pci_cfg_offset(b, s, f, reg));
if (width == 1)
return ((data >> ((reg & 3) << 3)) & 0xff);
else if (width == 2)
return ((data >> ((reg & 3) << 3)) & 0xffff);
else
return (data);
}
static void
xlr_pcib_write_config(device_t dev, u_int b, u_int s, u_int f,
u_int reg, u_int32_t val, int width)
{
uint32_t cfgaddr = pci_cfg_offset(b, s, f, reg);
uint32_t data = 0, *p;
if ((width == 2) && (reg & 1))
return;
else if ((width == 4) && (reg & 3))
return;
if (width == 1) {
data = pci_cfg_read_32bit(cfgaddr);
data = (data & ~(0xff << ((reg & 3) << 3))) |
(val << ((reg & 3) << 3));
} else if (width == 2) {
data = pci_cfg_read_32bit(cfgaddr);
data = (data & ~(0xffff << ((reg & 3) << 3))) |
(val << ((reg & 3) << 3));
} else {
data = val;
}
p = (uint32_t *)xlr_pci_config_base + cfgaddr / sizeof(uint32_t);
*p = bswap32(data);
return;
}
static int
xlr_pcib_attach(device_t dev)
{
struct xlr_pcib_softc *sc;
sc = device_get_softc(dev);
/*
* XLR C revision chips cannot do DMA above 2G physical address
* create a parent tag with this lowaddr
*/
if (xlr_is_c_revision()) {
if (bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0,
0x7fffffff, ~0, NULL, NULL, 0x7fffffff,
0xff, 0x7fffffff, 0, NULL, NULL, &sc->sc_pci_dmat) != 0)
panic("%s: bus_dma_tag_create failed", __func__);
}
device_add_child(dev, "pci", -1);
bus_generic_attach(dev);
return (0);
}
static void
xlr_pcib_identify(driver_t * driver, device_t parent)
{
BUS_ADD_CHILD(parent, 0, "pcib", 0);
}
/*
* XLS PCIe can have upto 4 links, and each link has its on IRQ
* Find the link on which the device is on
*/
static int
xls_pcie_link(device_t pcib, device_t dev)
{
device_t parent, tmp;
/* find the lane on which the slot is connected to */
printf("xls_pcie_link : bus %s dev %s\n", device_get_nameunit(pcib),
device_get_nameunit(dev));
tmp = dev;
while (1) {
parent = device_get_parent(tmp);
if (parent == NULL || parent == pcib) {
device_printf(dev, "Cannot find parent bus\n");
return (-1);
}
if (strcmp(device_get_nameunit(parent), "pci0") == 0)
break;
tmp = parent;
}
return (pci_get_slot(tmp));
}
/*
* Find the IRQ for the link, each link has a different interrupt
* at the XLS pic
*/
static int
xls_pcie_link_irq(int link)
{
switch (link) {
case 0:
return (PIC_PCIE_LINK0_IRQ);
case 1:
return (PIC_PCIE_LINK1_IRQ);
case 2:
if (xlr_is_xls_b0())
return (PIC_PCIE_B0_LINK2_IRQ);
else
return (PIC_PCIE_LINK2_IRQ);
case 3:
if (xlr_is_xls_b0())
return (PIC_PCIE_B0_LINK3_IRQ);
else
return (PIC_PCIE_LINK3_IRQ);
}
return (-1);
}
static int
xlr_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs)
{
int i, link;
/*
* Each link has 32 MSIs that can be allocated, but for now
* we only support one device per link.
* msi_alloc() equivalent is needed when we start supporting
* bridges on the PCIe link.
*/
link = xls_pcie_link(pcib, dev);
if (link == -1)
return (ENXIO);
/*
* encode the irq so that we know it is a MSI interrupt when we
* setup interrupts
*/
for (i = 0; i < count; i++)
irqs[i] = 64 + link * 32 + i;
return (0);
}
static int
xlr_release_msi(device_t pcib, device_t dev, int count, int *irqs)
{
device_printf(dev, "%s: msi release %d\n", device_get_nameunit(pcib),
count);
return (0);
}
static int
xlr_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr,
uint32_t *data)
{
int msi;
if (irq >= 64) {
msi = irq - 64;
*addr = MIPS_MSI_ADDR(0);
*data = MIPS_MSI_DATA(msi);
return (0);
} else {
device_printf(dev, "%s: map_msi for irq %d - ignored",
device_get_nameunit(pcib), irq);
return (ENXIO);
}
}
static void
bridge_pcix_ack(int irq)
{
(void)xlr_read_reg(xlr_io_mmio(XLR_IO_PCIX_OFFSET), 0x140 >> 2);
}
static void
bridge_pcie_ack(int irq)
{
uint32_t reg;
xlr_reg_t *pcie_mmio_le = xlr_io_mmio(XLR_IO_PCIE_1_OFFSET);
switch (irq) {
case PIC_PCIE_LINK0_IRQ:
reg = PCIE_LINK0_MSI_STATUS;
break;
case PIC_PCIE_LINK1_IRQ:
reg = PCIE_LINK1_MSI_STATUS;
break;
case PIC_PCIE_LINK2_IRQ:
case PIC_PCIE_B0_LINK2_IRQ:
reg = PCIE_LINK2_MSI_STATUS;
break;
case PIC_PCIE_LINK3_IRQ:
case PIC_PCIE_B0_LINK3_IRQ:
reg = PCIE_LINK3_MSI_STATUS;
break;
default:
return;
}
xlr_write_reg(pcie_mmio_le, reg>>2, 0xffffffff);
}
static int
mips_platform_pci_setup_intr(device_t dev, device_t child,
struct resource *irq, int flags, driver_filter_t *filt,
driver_intr_t *intr, void *arg, void **cookiep)
{
int error = 0;
int xlrirq;
error = rman_activate_resource(irq);
if (error)
return error;
if (rman_get_start(irq) != rman_get_end(irq)) {
device_printf(dev, "Interrupt allocation %ju != %ju\n",
rman_get_start(irq), rman_get_end(irq));
return (EINVAL);
}
xlrirq = rman_get_start(irq);
if (strcmp(device_get_name(dev), "pcib") != 0)
return (0);
if (xlr_board_info.is_xls == 0) {
xlr_establish_intr(device_get_name(child), filt,
intr, arg, PIC_PCIX_IRQ, flags, cookiep, bridge_pcix_ack);
pic_setup_intr(PIC_IRT_PCIX_INDEX, PIC_PCIX_IRQ, 0x1, 1);
} else {
/*
* temporary hack for MSI, we support just one device per
* link, and assign the link interrupt to the device interrupt
*/
if (xlrirq >= 64) {
xlrirq -= 64;
if (xlrirq % 32 != 0)
return (0);
xlrirq = xls_pcie_link_irq(xlrirq / 32);
if (xlrirq == -1)
return (EINVAL);
}
xlr_establish_intr(device_get_name(child), filt,
intr, arg, xlrirq, flags, cookiep, bridge_pcie_ack);
pic_setup_intr(xlrirq - PIC_IRQ_BASE, xlrirq, 0x1, 1);
}
return (bus_generic_setup_intr(dev, child, irq, flags, filt, intr,
arg, cookiep));
}
static int
mips_platform_pci_teardown_intr(device_t dev, device_t child,
struct resource *irq, void *cookie)
{
if (strcmp(device_get_name(child), "pci") == 0) {
/* if needed reprogram the pic to clear pcix related entry */
device_printf(dev, "teardown intr\n");
}
return (bus_generic_teardown_intr(dev, child, irq, cookie));
}
static struct resource *
xlr_pci_alloc_resource(device_t bus, device_t child, int type, int *rid,
rman_res_t start, rman_res_t end, rman_res_t count, u_int flags)
{
struct rman *rm;
struct resource *rv;
vm_offset_t va;
int needactivate = flags & RF_ACTIVE;
switch (type) {
case SYS_RES_IRQ:
rm = &irq_rman;
break;
case SYS_RES_IOPORT:
rm = &port_rman;
break;
case SYS_RES_MEMORY:
rm = &mem_rman;
break;
default:
return (0);
}
rv = rman_reserve_resource(rm, start, end, count, flags, child);
if (rv == NULL)
return (0);
rman_set_rid(rv, *rid);
if (type == SYS_RES_MEMORY || type == SYS_RES_IOPORT) {
va = (vm_offset_t)pmap_mapdev(start, count);
rman_set_bushandle(rv, va);
/* bushandle is same as virtual addr */
rman_set_virtual(rv, (void *)va);
rman_set_bustag(rv, rmi_pci_bus_space);
}
if (needactivate) {
if (bus_activate_resource(child, type, *rid, rv)) {
rman_release_resource(rv);
return (NULL);
}
}
return (rv);
}
static int
xlr_pci_release_resource(device_t bus, device_t child, int type, int rid,
struct resource *r)
{
return (rman_release_resource(r));
}
static bus_dma_tag_t
xlr_pci_get_dma_tag(device_t bus, device_t child)
{
struct xlr_pcib_softc *sc;
sc = device_get_softc(bus);
return (sc->sc_pci_dmat);
}
static int
xlr_pci_activate_resource(device_t bus, device_t child, int type, int rid,
struct resource *r)
{
return (rman_activate_resource(r));
}
static int
xlr_pci_deactivate_resource(device_t bus, device_t child, int type, int rid,
struct resource *r)
{
return (rman_deactivate_resource(r));
}
static int
mips_pci_route_interrupt(device_t bus, device_t dev, int pin)
{
int irq, link;
/*
* Validate requested pin number.
*/
if ((pin < 1) || (pin > 4))
return (255);
if (xlr_board_info.is_xls) {
link = xls_pcie_link(bus, dev);
irq = xls_pcie_link_irq(link);
if (irq != -1)
return (irq);
} else {
if (pin == 1)
return (PIC_PCIX_IRQ);
}
return (255);
}
static device_method_t xlr_pcib_methods[] = {
/* Device interface */
DEVMETHOD(device_identify, xlr_pcib_identify),
DEVMETHOD(device_probe, xlr_pcib_probe),
DEVMETHOD(device_attach, xlr_pcib_attach),
/* Bus interface */
DEVMETHOD(bus_read_ivar, xlr_pcib_read_ivar),
DEVMETHOD(bus_write_ivar, xlr_pcib_write_ivar),
DEVMETHOD(bus_alloc_resource, xlr_pci_alloc_resource),
DEVMETHOD(bus_release_resource, xlr_pci_release_resource),
DEVMETHOD(bus_get_dma_tag, xlr_pci_get_dma_tag),
DEVMETHOD(bus_activate_resource, xlr_pci_activate_resource),
DEVMETHOD(bus_deactivate_resource, xlr_pci_deactivate_resource),
DEVMETHOD(bus_setup_intr, mips_platform_pci_setup_intr),
DEVMETHOD(bus_teardown_intr, mips_platform_pci_teardown_intr),
/* pcib interface */
DEVMETHOD(pcib_maxslots, xlr_pcib_maxslots),
DEVMETHOD(pcib_read_config, xlr_pcib_read_config),
DEVMETHOD(pcib_write_config, xlr_pcib_write_config),
DEVMETHOD(pcib_route_interrupt, mips_pci_route_interrupt),
DEVMETHOD(pcib_request_feature, pcib_request_feature_allow),
DEVMETHOD(pcib_alloc_msi, xlr_alloc_msi),
DEVMETHOD(pcib_release_msi, xlr_release_msi),
DEVMETHOD(pcib_map_msi, xlr_map_msi),
DEVMETHOD_END
};
static driver_t xlr_pcib_driver = {
"pcib",
xlr_pcib_methods,
sizeof(struct xlr_pcib_softc),
};
DRIVER_MODULE(pcib, iodi, xlr_pcib_driver, pcib_devclass, 0, 0);

151
sys/mips/rmi/xlr_pcmcia.c
View File

@ -1,151 +0,0 @@
/*-
* SPDX-License-Identifier: BSD-3-Clause
*
* Copyright (c) 2003-2009 RMI Corporation
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* 3. Neither the name of RMI Corporation, nor the names of its contributors,
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
* SUCH DAMAGE.
*
* RMI_BSD */
/*
* ATA driver for the XLR_PCMCIA Host adapter on the RMI XLR/XLS/.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include <sys/param.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/module.h>
#include <sys/bus.h>
#include <sys/rman.h>
#include <vm/uma.h>
#include <sys/ata.h>
#include <sys/sema.h>
#include <sys/taskqueue.h>
#include <sys/bus_dma.h>
#include <dev/ata/ata-all.h>
#include <mips/rmi/pic.h>
#include <mips/rmi/iomap.h>
#include <mips/include/resource.h>
#include <mips/rmi/interrupt.h>
#define XLR_PCMCIA_DATA_REG 0x1f0
#define XLR_PCMCIA_ERROR_REG 0x1f1
#define XLR_PCMCIA_SECT_CNT_REG 0x1f2
#define XLR_PCMCIA_SECT_NUM_REG 0x1f3
#define XLR_PCMCIA_CYLINDER_LOW_REG 0x1f4
#define XLR_PCMCIA_CYLINDER_HIGH_REG 0x1f5
#define XLR_PCMCIA_SECT_DRIVE_HEAD_REG 0x1f6
#define XLR_PCMCIA_CMD_STATUS_REG 0x1f7
#define XLR_PCMCIA_ALT_STATUS_REG 0x3f6
#define XLR_PCMCIA_CONTROL_REG 0x3f6
/*
* Device methods
*/
static int xlr_pcmcia_probe(device_t);
static int xlr_pcmcia_attach(device_t);
static int xlr_pcmcia_detach(device_t);
static int
xlr_pcmcia_probe(device_t dev)
{
struct ata_channel *ch = device_get_softc(dev);
ch->unit = 0;
ch->flags |= ATA_USE_16BIT | ATA_NO_SLAVE ;
device_set_desc(dev, "PCMCIA ATA controller");
return (ata_probe(dev));
}
/*
* We add all the devices which we know about.
* The generic attach routine will attach them if they are alive.
*/
static int
xlr_pcmcia_attach(device_t dev)
{
struct ata_channel *ch = device_get_softc(dev);
int i;
int rid =0;
struct resource *mem_res;
mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
for (i = 0; i < ATA_MAX_RES; i++)
ch->r_io[i].res = mem_res;
/*
* CF+ Specification.
*/
ch->r_io[ATA_DATA].offset = XLR_PCMCIA_DATA_REG;
ch->r_io[ATA_FEATURE].offset = XLR_PCMCIA_ERROR_REG;
ch->r_io[ATA_COUNT].offset = XLR_PCMCIA_SECT_CNT_REG;
ch->r_io[ATA_SECTOR].offset = XLR_PCMCIA_SECT_NUM_REG;
ch->r_io[ATA_CYL_LSB].offset = XLR_PCMCIA_CYLINDER_LOW_REG;
ch->r_io[ATA_CYL_MSB].offset = XLR_PCMCIA_CYLINDER_HIGH_REG;
ch->r_io[ATA_DRIVE].offset = XLR_PCMCIA_SECT_DRIVE_HEAD_REG;
ch->r_io[ATA_COMMAND].offset = XLR_PCMCIA_CMD_STATUS_REG;
ch->r_io[ATA_ERROR].offset = XLR_PCMCIA_ERROR_REG;
ch->r_io[ATA_IREASON].offset = XLR_PCMCIA_SECT_CNT_REG;
ch->r_io[ATA_STATUS].offset = XLR_PCMCIA_CMD_STATUS_REG;
ch->r_io[ATA_ALTSTAT].offset = XLR_PCMCIA_ALT_STATUS_REG;
ch->r_io[ATA_CONTROL].offset = XLR_PCMCIA_CONTROL_REG;
/* Should point at the base of registers. */
ch->r_io[ATA_IDX_ADDR].offset = XLR_PCMCIA_DATA_REG;
ata_generic_hw(dev);
return (ata_attach(dev));
}
static int
xlr_pcmcia_detach(device_t dev)
{
bus_generic_detach(dev);
return (0);
}
static device_method_t xlr_pcmcia_methods[] = {
/* device interface */
DEVMETHOD(device_probe, xlr_pcmcia_probe),
DEVMETHOD(device_attach, xlr_pcmcia_attach),
DEVMETHOD(device_detach, xlr_pcmcia_detach),
{ 0, 0 }
};
static driver_t xlr_pcmcia_driver = {
"ata",
xlr_pcmcia_methods,
sizeof(struct ata_channel),
};
DRIVER_MODULE(ata, iodi, xlr_pcmcia_driver, ata_devclass, 0, 0);

222
sys/mips/rmi/xls_ehci.c
View File

@ -1,222 +0,0 @@
/*-
* SPDX-License-Identifier: BSD-2-Clause-NetBSD
*
* Copyright (c) 1998 The NetBSD Foundation, Inc.
* All rights reserved.
*
* This code is derived from software contributed to The NetBSD Foundation
* by Lennart Augustsson (augustss@carlstedt.se) at
* Carlstedt Research & Technology.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* 1. Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
*
* THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
* ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
* TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <sys/cdefs.h>
__FBSDID("$FreeBSD$");
#include "opt_bus.h"
#include <sys/stdint.h>
#include <sys/stddef.h>
#include <sys/param.h>
#include <sys/queue.h>
#include <sys/types.h>
#include <sys/systm.h>
#include <sys/kernel.h>
#include <sys/bus.h>
#include <sys/module.h>
#include <sys/lock.h>
#include <sys/mutex.h>
#include <sys/condvar.h>
#include <sys/sysctl.h>
#include <sys/sx.h>
#include <sys/unistd.h>
#include <sys/callout.h>
#include <sys/malloc.h>
#include <sys/priv.h>
#include <sys/rman.h>
#include <machine/resource.h>
#include <dev/usb/usb.h>
#include <dev/usb/usbdi.h>
#include <dev/usb/usb_core.h>
#include <dev/usb/usb_busdma.h>
#include <dev/usb/usb_process.h>
#include <dev/usb/usb_util.h>
#include <dev/usb/usb_controller.h>
#include <dev/usb/usb_bus.h>
#include <dev/usb/controller/ehci.h>
#include <dev/usb/controller/ehcireg.h>
#include <mips/rmi/pic.h>
static device_attach_t ehci_xls_attach;
static device_detach_t ehci_xls_detach;
static const char *xlr_usb_dev_desc = "RMI XLR USB 2.0 controller";
static const char *xlr_vendor_desc = "RMI Corp";
static int
ehci_xls_probe(device_t self)
{
/* TODO see if usb is enabled on the board */
device_set_desc(self, xlr_usb_dev_desc);
return BUS_PROBE_DEFAULT;
}
static int
ehci_xls_attach(device_t self)
{
ehci_softc_t *sc = device_get_softc(self);
int err;
int rid;
sc->sc_bus.parent = self;
sc->sc_bus.devices = sc->sc_devices;
sc->sc_bus.devices_max = EHCI_MAX_DEVICES;
sc->sc_bus.dma_bits = 32;
/* get all DMA memory */
if (usb_bus_mem_alloc_all(&sc->sc_bus,
USB_GET_DMA_TAG(self), &ehci_iterate_hw_softc)) {
return (ENOMEM);
}
rid = 0;
sc->sc_io_res = bus_alloc_resource_any(self, SYS_RES_MEMORY, &rid,
RF_ACTIVE);
if (!sc->sc_io_res) {
device_printf(self, "Could not map memory\n");
goto error;
}
sc->sc_io_tag = rman_get_bustag(sc->sc_io_res);
sc->sc_io_hdl = rman_get_bushandle(sc->sc_io_res);
printf("IO Resource tag %lx, hdl %lx, size %lx\n",
(u_long)sc->sc_io_tag, (u_long)sc->sc_io_hdl,
(u_long)sc->sc_io_size);
rid = 0;
sc->sc_irq_res = bus_alloc_resource(self, SYS_RES_IRQ, &rid,
PIC_USB_IRQ, PIC_USB_IRQ, 1, RF_SHAREABLE | RF_ACTIVE);
if (sc->sc_irq_res == NULL) {
device_printf(self, "Could not allocate irq\n");
goto error;
}
sc->sc_bus.bdev = device_add_child(self, "usbus", -1);
if (!sc->sc_bus.bdev) {
device_printf(self, "Could not add USB device\n");
goto error;
}
device_set_ivars(sc->sc_bus.bdev, &sc->sc_bus);
device_set_desc(sc->sc_bus.bdev, xlr_usb_dev_desc);
strlcpy(sc->sc_vendor, xlr_vendor_desc, sizeof(sc->sc_vendor));
err = bus_setup_intr(self, sc->sc_irq_res,
INTR_TYPE_BIO | INTR_MPSAFE, NULL,
(driver_intr_t *) ehci_interrupt, sc, &sc->sc_intr_hdl);
if (err) {
device_printf(self, "Could not setup irq, %d\n", err);
sc->sc_intr_hdl = NULL;
goto error;
}
err = ehci_init(sc);
if (err) {
device_printf(self, "USB init failed err=%d\n", err);
goto error;
}
err = device_probe_and_attach(sc->sc_bus.bdev);
if (err) {
device_printf(self, "USB probe and attach failed err=%d\n", err);
goto error;
}
return (0);
error:
ehci_xls_detach(self);
return (ENXIO);
}
static int
ehci_xls_detach(device_t self)
{
ehci_softc_t *sc = device_get_softc(self);
int err;
/* during module unload there are lots of children leftover */
device_delete_children(self);
if (sc->sc_irq_res && sc->sc_intr_hdl) {
ehci_detach(sc);
err = bus_teardown_intr(self, sc->sc_irq_res, sc->sc_intr_hdl);
if (err)
device_printf(self, "Could not tear down irq, %d\n",
err);
sc->sc_intr_hdl = 0;
}
if (sc->sc_irq_res) {
bus_release_resource(self, SYS_RES_IRQ, 0, sc->sc_irq_res);
sc->sc_irq_res = NULL;
}
if (sc->sc_io_res) {
bus_release_resource(self, SYS_RES_MEMORY, 0,
sc->sc_io_res);
sc->sc_io_res = NULL;
sc->sc_io_tag = 0;
sc->sc_io_hdl = 0;
}
usb_bus_mem_free_all(&sc->sc_bus, &ehci_iterate_hw_softc);
return (0);
}
static device_method_t ehci_methods[] = {
/* Device interface */
DEVMETHOD(device_probe, ehci_xls_probe),
DEVMETHOD(device_attach, ehci_xls_attach),
DEVMETHOD(device_detach, ehci_xls_detach),
DEVMETHOD(device_suspend, bus_generic_suspend),
DEVMETHOD(device_resume, bus_generic_resume),
DEVMETHOD(device_shutdown, bus_generic_shutdown),
DEVMETHOD_END
};
static driver_t ehci_driver = {
.name = "ehci",
.methods = ehci_methods,
.size = sizeof(struct ehci_softc),
};
static devclass_t ehci_devclass;
DRIVER_MODULE(ehci, iodi, ehci_driver, ehci_devclass, 0, 0);
MODULE_DEPEND(ehci, usb, 1, 1, 1);