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Add support for gigabit ethernet cards based on the NatSemi DP83820
and DP83821 gigabit ethernet MAC chips and the NatSemi DP83861 10/100/1000 copper PHY. There are a whole bunch of very low cost cards available with this chipset selling for $150USD or less. This includes the SMC9462TX, D-Link DGE-500T, Asante GigaNIX 1000TA and 1000TPC, and a couple cards from Addtron. This chip supports TCP/IP checksum offload, VLAN tagging/insertion. 2048-bit multicast filter, jumbograms and has 8K TX and 32K RX FIFOs. I have not done serious performance testing with this driver. I know it works, and I want it under CVS control so I can keep tabs on it. Note that there's no serious mutex stuff in here yet either: I need to talk more with jhb to figure out the right way to do this. That said, I don't think there will be any problems. This driver should also work on the alpha. It's not turned on in GENERIC.
This commit is contained in:
Bill Paul
parent
9c4d044a0e
commit
ce4946daa5
Notes:
svn2git
2020-12-20 02:59:44 +00:00
svn path=/head/; revision=76479
@ -119,6 +119,7 @@ ie0 300 10 dyn d0000 AT&T StarLAN 10 and EN100;
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lnc0 280 10 n/a dyn Lance/PCnet cards
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(Isolan, Novell NE2100, NE32-VL,
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some PCnet-PCI cards)
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nge0 dyn dyn n/a dyn NatSemi DP83820 gigabit ethernet
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pcn0 dyn dyn n/a dyn AMD PCnet/FAST, PCnet/FAST+,
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PCnet/FAST III, PCnet/PRO, PCnet/Home,
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and HomePNA cards
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@ -126,7 +127,9 @@ rl0 dyn dyn n/a dyn RealTek 8129/8139 Fast Ethernet
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sf0 dyn dyn n/a dyn Adaptec AIC-6915 Fast Ethernet
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sis0 dyn dyn n/a dyn SiS 900/SiS 7016 Fast Ethernet
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sn0 0x300 10 n/a n/a SMC 91xx Ethernet
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sk0 dyn dyn n/a dyn SysKonnect gigabit ethernet
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ste0 dyn dyn n/a dyn Sundance ST201 Fast Ethernet
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ti0 dyn dyn n/a dyn Alteon Tigon 1 & 2 gigabit ethernet
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tl0 dyn dyn n/a dyn TI TNET100 'ThunderLAN' cards.
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tx0 dyn dyn n/a dyn SMC 9432 'Epic' Fast Ethernet
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wb0 dyn dyn n/a dyn Winbond W89C840F PCI based cards.
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@ -541,7 +544,7 @@ The following CD-ROM type systems are supported at this time:
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(acd) ATAPI IDE interface
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Unmaintained drivers, they might or might not work for your hardware:
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NatSemi DP83820 gigabit ethernet
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(mcd) Mitsumi proprietary CD-ROM interface (all models)
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4.2. Network cards
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@ -623,6 +626,13 @@ National Semiconductor DP83815 Fast Ethernet NICs including the following:
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NetGear FA311-TX
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NetGear FA312-TX
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National Semiconductor DP83820 and DP83821 Gigabit Ethernet NICs including
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the following:
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D-Link DGE-500T
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SMC EZ Card 1000 (SMC9462TX)
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Asante FriendlyNet GigaNIC 1000TA and 1000TPC
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Addtron AEG320T
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Sundance Technologies ST201 PCI Fast Ethernet NICs including
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the following:
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D-Link DFE-550TX
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@ -356,6 +356,10 @@ The wx(4) driver now supports the Intel PRO1000-F and PRO1000-T
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The labpc(4) driver has been removed due to bitrot.
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Added support for PCI Gigabit Ethernet adapters based on the National
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Semiconductor DP83820 and DP83821 gigabit ethernet controller chips,
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including the D-Link DGE-500T, SMC EZ Card 1000 (SMC9462TX),
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Asante FriendlyNet GigaNIC 1000TA and 1000TPC and Addtron AEG320T.
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1.2. SECURITY FIXES
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-------------------
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@ -1285,8 +1289,16 @@ NICs including the following:
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Silicon Integrated Systems SiS 900 and SiS 7016 PCI Fast Ethernet NICs
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National Semiconductor DP83815 Fast Ethernet NICs including the following:
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NetGear FA311-TX
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NetGear FA312-TX
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National Semiconductor DP83820 and DP83821 Gigabit Ethernet NICs including
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the following:
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D-Link DGE-500T
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SMC EZ Card 1000 (SMC9462TX)
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Asante FriendlyNet GigaNIC 1000TA and 1000TPC
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Addtron AEG320T
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Sundance Technologies ST201 PCI Fast Ethernet NICs including
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the following:
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D-Link DFE-550TX
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@ -437,6 +437,10 @@ testing.
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smbfs (CIFS) support in kernel has been added.
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Added support for PCI Gigabit Ethernet adapters based on the National
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Semiconductor DP83820 and DP83821 gigabit ethernet controller chips,
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including the D-Link DGE-500T, SMC EZ Card 1000 (SMC9462TX),
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Asante FriendlyNet GigaNIC 1000TA and 1000TPC and Addtron AEG320T.
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1.2. SECURITY FIXES
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-------------------
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@ -1470,8 +1474,16 @@ NICs including the following:
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Silicon Integrated Systems SiS 900 and SiS 7016 PCI Fast Ethernet NICs
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National Semiconductor DP83815 Fast Ethernet NICs including the following:
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NetGear FA311-TX
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NetGear FA312-TX
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National Semiconductor DP83820 and DP83821 Gigabit Ethernet NICs including
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the following:
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D-Link DGE-500T
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SMC EZ Card 1000 (SMC9462TX)
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Asante FriendlyNet GigaNIC 1000TA and 1000TPC
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Addtron AEG320T
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Sundance Technologies ST201 PCI Fast Ethernet NICs including
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the following:
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D-Link DFE-550TX
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@ -100,6 +100,7 @@ MAN= aac.4 \
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ng_tee.4 \
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ng_tty.4 \
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ng_vjc.4 \
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nge.4 \
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null.4 \
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ohci.4 \
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pass.4 \
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205
share/man/man4/nge.4
Normal file
205
share/man/man4/nge.4
Normal file
@ -0,0 +1,205 @@
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.\" Copyright (c) 2001 Wind River Syste,s
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.\" Copyright (c) 1997, 1998, 1999, 2000, 2001
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.\" Bill Paul <wpaul@bsdi.com>. All rights reserved.
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.\"
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.\" Redistribution and use in source and binary forms, with or without
|
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.\" modification, are permitted provided that the following conditions
|
||||
.\" are met:
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||||
.\" 1. Redistributions of source code must retain the above copyright
|
||||
.\" notice, this list of conditions and the following disclaimer.
|
||||
.\" 2. Redistributions in binary form must reproduce the above copyright
|
||||
.\" notice, this list of conditions and the following disclaimer in the
|
||||
.\" documentation and/or other materials provided with the distribution.
|
||||
.\" 3. All advertising materials mentioning features or use of this software
|
||||
.\" must display the following acknowledgement:
|
||||
.\" This product includes software developed by Bill Paul.
|
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.\" 4. Neither the name of the author nor the names of any co-contributors
|
||||
.\" may be used to endorse or promote products derived from this software
|
||||
.\" without specific prior written permission.
|
||||
.\"
|
||||
.\" THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
|
||||
.\" ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
.\" IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
.\" ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
|
||||
.\" BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
.\" CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
.\" SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
.\" INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
.\" CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
.\" ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||
.\" THE POSSIBILITY OF SUCH DAMAGE.
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||||
.\"
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.\" $FreeBSD$
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.\"
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.Dd July 11, 2001
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.Dt NGE 4
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.Os FreeBSD
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.Sh NAME
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.Nm nge
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.Nd "National Semiconductor PCI gigabit ethernet adapter driver"
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.Sh SYNOPSIS
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.Cd "device miibus"
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.Cd "device nge"
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.Sh DESCRIPTION
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The
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.Nm
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driver provides support for various NICs based on the National Semiconductor
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DP83820 and DP83821 gigabit ethernet controller chips, including the
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following:
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.Pp
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.Bl -bullet -offset indent -compact
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.It
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SMC EZ Card 1000 (SMC9462TX)
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.It
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D-Link DGE-500T
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.It
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Asante FriendlyNet GigaNIX 1000TA and 1000TPC
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.It
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Addrton AEG320T
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.El
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.Pp
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All of these NICs are capable of 10, 100 and 1000mbps speeds over CAT5
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copper cable. The DP83820 supports TBI (ten bit interface) and GMII
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transceivers, which means it can be used with either copper of 1000baseX
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fiber applications. The DP83820 supports TCP/IP checksum offload and
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VLAN tagging/insertion as well as a 2048-bit multicast hash filter
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and up to 4 pattern match buffers.
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.Pp
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Most cards also use the DP83861 10/100/1000 copper gigabit tranceiver
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chip, which supports autonegotiation of 10, 100 and 1000mbps modes in
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full or half duplex.
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.Pp
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The DP83820 also supports jumbo frames, which can be configured
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via the interface MTY setting.
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Selecting an MTU larger than 1500 bytes with the
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.Xr ifconfig 8
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utility configures the adapter to receive and transmit jumbo frames.
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Using jumbo frames can greatly improve performance for certain tanges,
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such as file transfers and data streaming.
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.Pp
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The
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.Nm
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driver supports the following media types:
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.Pp
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.Bl -tag -width 10baseTXUTP
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.It autoselect
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Enable autoselection of the media type and options.
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The user can manually override
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the autoselected mode by adding media options to
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.Xr rc.conf 5 .
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.It 10baseT/UTP
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Set 10Mbps operation.
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The
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.Xr ifconfig 8
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.Cm mediaopt
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option can also be used to select either
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.Sq full-duplex
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or
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.Sq half-duplex
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modes.
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.It 100baseTX
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Set 100Mbps (fast ethernet) operation.
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The
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.Xr ifconfig 8
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.Cm mediaopt
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option can also be used to select either
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.Sq full-duplex
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or
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.Sq half-duplex
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modes.
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.It 1000baseTX
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Set 1000baseTX operation over twisted pair.
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.Ar full-duplex
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and
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.Ar half-duplex
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modes are supported.
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.It 1000baseSX
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Set 1000Mbps (gigabit ethernet) operation.
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Both
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.Ar full-duplex
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and
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.Ar half-duplex
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modes are supported.
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.El
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.Pp
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The
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.Nm
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driver supports the following media options:
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.Pp
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.Bl -tag -width xxxxxxxxxxxxxxxxxxxx
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.It full-duplex
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Force full duplex operation
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.It half-duplex
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Force half duplex operation.
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.El
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.Pp
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The
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.Nm
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driver also supports one special link option for 1000baseTX cards:
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.Pp
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.Bl -tag -width xxxxxxxxx
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.It link0
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With 1000baseTX cards, establishing a link between two ports requires
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that one port be configured as a master and the other a slave.
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With autonegotiation,
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the master/slave settings will be chosen automatically.
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However when manually selecting the link state, it is necessary to
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force one side of the link to be a master and the other a slave.
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The
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.Nm
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driver configures the ports as slaves by default.
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Setting the
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.Ar link0
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flag with
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.Xr ifconfig 8
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will set a port as a master instead.
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.El
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.Pp
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For more information on configuring this device, see
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.Xr ifconfig 8 .
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.Sh DIAGNOSTICS
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.Bl -diag
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.It "nge%d: couldn't map memory"
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A fatal initialization error has occurred.
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.It "nge%d: couldn't map ports"
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A fatal initialization error has occurred.
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.It "nge%d: couldn't map interrupt"
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A fatal initialization error has occurred.
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.It "nge%d: no memory for softc struct!"
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The driver failed to allocate memory for per-device instance information
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during initialization.
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.It "nge%d: failed to enable memory mapping!"
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The driver failed to initialize PCI shared memory mapping.
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This might
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happen if the card is not in a bus-master slot.
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.It "nge%d: no memory for jumbo buffers!"
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The driver failed to allocate memory for jumbo frames during
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initialization.
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.It "nge%d: watchdog timeout"
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The device has stopped responding to the network, or there is a problem with
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the network connection (cable).
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.El
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.Sh SEE ALSO
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.Xr arp 4 ,
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.Xr netintro 4 ,
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.Xr vlan 4 ,
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.Xr ng_ether 4 ,
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.Xr ifconfig 8
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.Rs
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.%T National Semiconductor DP83820 datasheet
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.%O http://www.national.com
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.Re
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.Rs
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.%T National Semiconductor DP83861 datasheet
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.%O http://www.national.com
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.Re
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.Sh HISTORY
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The
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.Nm
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device driver first appeared in
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.Fx 5.0 .
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.Sh AUTHORS
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The
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.Nm
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driver was written by
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.An Bill Paul Aq wpaul@bsdi.com .
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@ -1634,6 +1634,10 @@ device miibus
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# DE101, DE200, DE201, DE202, DE203, DE204, DE205, DE422)
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# lnc: Lance/PCnet cards (Isolan, Novell NE2100, NE32-VL, AMD Am7990 and
|
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# Am79C960)
|
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# nge: Support for PCI gigabit ethernet adapters based on the National
|
||||
# Semiconductor DP83820 and DP83821 chipset. This includes the
|
||||
# SMC EZ Card 1000 (SMC9462TX), D-Link DGE-500T, Asante FriendlyNet
|
||||
# GigaNIX 1000TA and 1000TPC, and the Addtron AEG320T.
|
||||
# oltr: Olicom ISA token-ring adapters OC-3115, OC-3117, OC-3118 and OC-3133
|
||||
# (no hints needed).
|
||||
# Olicom PCI token-ring adapters OC-3136, OC-3137, OC-3139, OC-3140,
|
||||
@ -1803,6 +1807,7 @@ device de # DEC/Intel DC21x4x (``Tulip'')
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device vx # 3Com 3c590, 3c595 (``Vortex'')
|
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|
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# PCI Gigabit & FDDI NICs.
|
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device nge
|
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device sk
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device ti
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device wx
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|
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@ -385,6 +385,7 @@ dev/mii/mii.c optional miibus
|
||||
dev/mii/mii_physubr.c optional miibus
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dev/mii/mlphy.c optional miibus
|
||||
dev/mii/nsphy.c optional miibus
|
||||
dev/mii/nsgphy.c optional miibus
|
||||
dev/mii/pnphy.c optional miibus
|
||||
dev/mii/pnaphy.c optional miibus
|
||||
dev/mii/rlphy.c optional miibus
|
||||
@ -404,6 +405,7 @@ dev/mly/mly.c optional mly
|
||||
dev/mly/mly_cam.c optional mly
|
||||
dev/mly/mly_pci.c optional mly
|
||||
dev/musycc/musycc.c optional musycc
|
||||
dev/nge/if_nge.c optional nge
|
||||
dev/null/null.c standard
|
||||
dev/nmdm/nmdm.c optional nmdm
|
||||
dev/pccard/card_if.m optional card
|
||||
|
||||
@ -122,6 +122,8 @@ model xxLEVEL1 LXT970 0x0000 LXT970 10/100 media interface
|
||||
/* National Semiconductor PHYs */
|
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model NATSEMI DP83840 0x0000 DP83840 10/100 media interface
|
||||
model NATSEMI DP83843 0x0001 DP83843 10/100 media interface
|
||||
model NATSEMI DP83891 0x0005 DP83891 10/100/1000 media interface
|
||||
model NATSEMI DP83861 0x0006 DP83861 10/100/1000 media interface
|
||||
|
||||
/* Quality Semiconductor PHYs */
|
||||
model QUALSEMI QS6612 0x0000 QS6612 10/100 media interface
|
||||
|
||||
475
sys/dev/mii/nsgphy.c
Normal file
475
sys/dev/mii/nsgphy.c
Normal file
@ -0,0 +1,475 @@
|
||||
/*
|
||||
* Copyright (c) 2001 Wind River Systems
|
||||
* Copyright (c) 2001
|
||||
* Bill Paul <wpaul@bsdi.com>. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by Bill Paul.
|
||||
* 4. Neither the name of the author nor the names of any co-contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
/*
|
||||
* Driver for the National Semiconductor DP83891 and DP83861
|
||||
* 10/100/1000 PHYs.
|
||||
* Datasheet available at: http://www.national.com/ds/DP/DP83861.pdf
|
||||
*
|
||||
* The DP83891 is the older NatSemi gigE PHY which isn't being sold
|
||||
* anymore. The DP83861 is its replacement, which is an 'enhanced'
|
||||
* firmware driven component. The major difference between the
|
||||
* two is that the 83891 can't generate interrupts, while the
|
||||
* 83861 can. (I think it wasn't originally designed to do this, but
|
||||
* it can now thanks to firmware updates.) The 83861 also allows
|
||||
* access to its internal RAM via indirect register access.
|
||||
*/
|
||||
|
||||
#include <sys/param.h>
|
||||
#include <sys/systm.h>
|
||||
#include <sys/kernel.h>
|
||||
#include <sys/malloc.h>
|
||||
#include <sys/socket.h>
|
||||
#include <sys/bus.h>
|
||||
|
||||
#include <machine/clock.h>
|
||||
|
||||
#include <net/if.h>
|
||||
#include <net/if_media.h>
|
||||
|
||||
#include <dev/mii/mii.h>
|
||||
#include <dev/mii/miivar.h>
|
||||
#include <dev/mii/miidevs.h>
|
||||
|
||||
#include <dev/mii/nsgphyreg.h>
|
||||
|
||||
#include "miibus_if.h"
|
||||
|
||||
#if !defined(lint)
|
||||
static const char rcsid[] =
|
||||
"$FreeBSD$";
|
||||
#endif
|
||||
|
||||
static int nsgphy_probe __P((device_t));
|
||||
static int nsgphy_attach __P((device_t));
|
||||
static int nsgphy_detach __P((device_t));
|
||||
|
||||
static device_method_t nsgphy_methods[] = {
|
||||
/* device interface */
|
||||
DEVMETHOD(device_probe, nsgphy_probe),
|
||||
DEVMETHOD(device_attach, nsgphy_attach),
|
||||
DEVMETHOD(device_detach, nsgphy_detach),
|
||||
DEVMETHOD(device_shutdown, bus_generic_shutdown),
|
||||
{ 0, 0 }
|
||||
};
|
||||
|
||||
static devclass_t nsgphy_devclass;
|
||||
|
||||
static driver_t nsgphy_driver = {
|
||||
"nsgphy",
|
||||
nsgphy_methods,
|
||||
sizeof(struct mii_softc)
|
||||
};
|
||||
|
||||
DRIVER_MODULE(nsgphy, miibus, nsgphy_driver, nsgphy_devclass, 0, 0);
|
||||
|
||||
int nsgphy_service __P((struct mii_softc *, struct mii_data *, int));
|
||||
void nsgphy_status __P((struct mii_softc *));
|
||||
|
||||
static int nsgphy_mii_phy_auto __P((struct mii_softc *, int));
|
||||
extern void mii_phy_auto_timeout __P((void *));
|
||||
|
||||
static int nsgphy_probe(dev)
|
||||
device_t dev;
|
||||
{
|
||||
struct mii_attach_args *ma;
|
||||
|
||||
ma = device_get_ivars(dev);
|
||||
|
||||
if (MII_OUI(ma->mii_id1, ma->mii_id2) == MII_OUI_NATSEMI) {
|
||||
if (MII_MODEL(ma->mii_id2) == MII_MODEL_NATSEMI_DP83891) {
|
||||
device_set_desc(dev, MII_STR_NATSEMI_DP83891);
|
||||
return(0);
|
||||
}
|
||||
if (MII_MODEL(ma->mii_id2) == MII_MODEL_NATSEMI_DP83861) {
|
||||
device_set_desc(dev, MII_STR_NATSEMI_DP83861);
|
||||
return(0);
|
||||
}
|
||||
}
|
||||
|
||||
return(ENXIO);
|
||||
}
|
||||
|
||||
static int nsgphy_attach(dev)
|
||||
device_t dev;
|
||||
{
|
||||
struct mii_softc *sc;
|
||||
struct mii_attach_args *ma;
|
||||
struct mii_data *mii;
|
||||
const char *sep = "";
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
ma = device_get_ivars(dev);
|
||||
sc->mii_dev = device_get_parent(dev);
|
||||
mii = device_get_softc(sc->mii_dev);
|
||||
LIST_INSERT_HEAD(&mii->mii_phys, sc, mii_list);
|
||||
|
||||
sc->mii_inst = mii->mii_instance;
|
||||
sc->mii_phy = ma->mii_phyno;
|
||||
sc->mii_service = nsgphy_service;
|
||||
sc->mii_pdata = mii;
|
||||
|
||||
sc->mii_flags |= MIIF_NOISOLATE;
|
||||
mii->mii_instance++;
|
||||
|
||||
#define ADD(m, c) ifmedia_add(&mii->mii_media, (m), (c), NULL)
|
||||
#define PRINT(s) printf("%s%s", sep, s); sep = ", "
|
||||
|
||||
ADD(IFM_MAKEWORD(IFM_ETHER, IFM_NONE, 0, sc->mii_inst),
|
||||
BMCR_ISO);
|
||||
#if 0
|
||||
ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_LOOP, sc->mii_inst),
|
||||
BMCR_LOOP|BMCR_S100);
|
||||
#endif
|
||||
|
||||
mii_phy_reset(sc);
|
||||
|
||||
device_printf(dev, " ");
|
||||
ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_TX, IFM_FDX, sc->mii_inst),
|
||||
NSGPHY_S1000|NSGPHY_BMCR_FDX);
|
||||
PRINT("1000baseTX-FDX");
|
||||
ADD(IFM_MAKEWORD(IFM_ETHER, IFM_1000_TX, 0, sc->mii_inst),
|
||||
NSGPHY_S1000);
|
||||
PRINT("1000baseTX");
|
||||
sc->mii_capabilities =
|
||||
(PHY_READ(sc, MII_BMSR) |
|
||||
(BMSR_10TFDX|BMSR_10THDX)) & ma->mii_capmask;
|
||||
ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, IFM_FDX, sc->mii_inst),
|
||||
NSGPHY_S100|NSGPHY_BMCR_FDX);
|
||||
PRINT("100baseTX-FDX");
|
||||
ADD(IFM_MAKEWORD(IFM_ETHER, IFM_100_TX, 0, sc->mii_inst), NSGPHY_S100);
|
||||
PRINT("100baseTX");
|
||||
ADD(IFM_MAKEWORD(IFM_ETHER, IFM_10_T, IFM_FDX, sc->mii_inst),
|
||||
NSGPHY_S10|NSGPHY_BMCR_FDX);
|
||||
PRINT("10baseT-FDX");
|
||||
ADD(IFM_MAKEWORD(IFM_ETHER, IFM_10_T, 0, sc->mii_inst), NSGPHY_S10);
|
||||
PRINT("10baseT");
|
||||
ADD(IFM_MAKEWORD(IFM_ETHER, IFM_AUTO, 0, sc->mii_inst), 0);
|
||||
PRINT("auto");
|
||||
printf("\n");
|
||||
#undef ADD
|
||||
#undef PRINT
|
||||
|
||||
MIIBUS_MEDIAINIT(sc->mii_dev);
|
||||
return(0);
|
||||
}
|
||||
|
||||
static int nsgphy_detach(dev)
|
||||
device_t dev;
|
||||
{
|
||||
struct mii_softc *sc;
|
||||
struct mii_data *mii;
|
||||
|
||||
sc = device_get_softc(dev);
|
||||
mii = device_get_softc(device_get_parent(dev));
|
||||
if (sc->mii_flags & MIIF_DOINGAUTO)
|
||||
untimeout(mii_phy_auto_timeout, sc, sc->mii_auto_ch);
|
||||
sc->mii_dev = NULL;
|
||||
LIST_REMOVE(sc, mii_list);
|
||||
|
||||
return(0);
|
||||
}
|
||||
int
|
||||
nsgphy_service(sc, mii, cmd)
|
||||
struct mii_softc *sc;
|
||||
struct mii_data *mii;
|
||||
int cmd;
|
||||
{
|
||||
struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
|
||||
int reg;
|
||||
|
||||
switch (cmd) {
|
||||
case MII_POLLSTAT:
|
||||
/*
|
||||
* If we're not polling our PHY instance, just return.
|
||||
*/
|
||||
if (IFM_INST(ife->ifm_media) != sc->mii_inst)
|
||||
return (0);
|
||||
break;
|
||||
|
||||
case MII_MEDIACHG:
|
||||
/*
|
||||
* If the media indicates a different PHY instance,
|
||||
* isolate ourselves.
|
||||
*/
|
||||
if (IFM_INST(ife->ifm_media) != sc->mii_inst) {
|
||||
reg = PHY_READ(sc, MII_BMCR);
|
||||
PHY_WRITE(sc, MII_BMCR, reg | BMCR_ISO);
|
||||
return (0);
|
||||
}
|
||||
|
||||
/*
|
||||
* If the interface is not up, don't do anything.
|
||||
*/
|
||||
if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
|
||||
break;
|
||||
|
||||
|
||||
switch (IFM_SUBTYPE(ife->ifm_media)) {
|
||||
case IFM_AUTO:
|
||||
#ifdef foo
|
||||
/*
|
||||
* If we're already in auto mode, just return.
|
||||
*/
|
||||
if (PHY_READ(sc, NSGPHY_MII_BMCR) & NSGPHY_BMCR_AUTOEN)
|
||||
return (0);
|
||||
#endif
|
||||
(void) nsgphy_mii_phy_auto(sc, 0);
|
||||
break;
|
||||
case IFM_1000_TX:
|
||||
if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) {
|
||||
PHY_WRITE(sc, NSGPHY_MII_BMCR,
|
||||
NSGPHY_BMCR_FDX|NSGPHY_BMCR_SPD1);
|
||||
} else {
|
||||
PHY_WRITE(sc, NSGPHY_MII_BMCR,
|
||||
NSGPHY_BMCR_SPD1);
|
||||
}
|
||||
PHY_WRITE(sc, NSGPHY_MII_ANAR, NSGPHY_SEL_TYPE);
|
||||
|
||||
/*
|
||||
* When setting the link manually, one side must
|
||||
* be the master and the other the slave. However
|
||||
* ifmedia doesn't give us a good way to specify
|
||||
* this, so we fake it by using one of the LINK
|
||||
* flags. If LINK0 is set, we program the PHY to
|
||||
* be a master, otherwise it's a slave.
|
||||
*/
|
||||
if ((mii->mii_ifp->if_flags & IFF_LINK0)) {
|
||||
PHY_WRITE(sc, NSGPHY_MII_1000CTL,
|
||||
NSGPHY_1000CTL_MSE|NSGPHY_1000CTL_MSC);
|
||||
} else {
|
||||
PHY_WRITE(sc, NSGPHY_MII_1000CTL,
|
||||
NSGPHY_1000CTL_MSE);
|
||||
}
|
||||
break;
|
||||
case IFM_100_T4:
|
||||
/*
|
||||
* XXX Not supported as a manual setting right now.
|
||||
*/
|
||||
return (EINVAL);
|
||||
case IFM_NONE:
|
||||
PHY_WRITE(sc, MII_BMCR, BMCR_ISO|BMCR_PDOWN);
|
||||
break;
|
||||
default:
|
||||
/*
|
||||
* BMCR data is stored in the ifmedia entry.
|
||||
*/
|
||||
PHY_WRITE(sc, MII_ANAR,
|
||||
mii_anar(ife->ifm_media));
|
||||
PHY_WRITE(sc, MII_BMCR, ife->ifm_data);
|
||||
break;
|
||||
}
|
||||
break;
|
||||
|
||||
case MII_TICK:
|
||||
/*
|
||||
* If we're not currently selected, just return.
|
||||
*/
|
||||
if (IFM_INST(ife->ifm_media) != sc->mii_inst)
|
||||
return (0);
|
||||
|
||||
/*
|
||||
* Only used for autonegotiation.
|
||||
*/
|
||||
if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO)
|
||||
return (0);
|
||||
|
||||
/*
|
||||
* Is the interface even up?
|
||||
*/
|
||||
if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
|
||||
return (0);
|
||||
|
||||
/*
|
||||
* Only retry autonegotiation every 5 seconds.
|
||||
* Actually, for gigE PHYs, we should wait longer, since
|
||||
* 5 seconds is the mimimum time the documentation
|
||||
* says to wait for a 1000mbps link to be established.
|
||||
*/
|
||||
if (++sc->mii_ticks != 10)
|
||||
return (0);
|
||||
|
||||
sc->mii_ticks = 0;
|
||||
|
||||
/*
|
||||
* Check to see if we have link.
|
||||
*/
|
||||
reg = PHY_READ(sc, NSGPHY_MII_PHYSUP);
|
||||
if (reg & NSGPHY_PHYSUP_LNKSTS)
|
||||
break;
|
||||
|
||||
mii_phy_reset(sc);
|
||||
if (nsgphy_mii_phy_auto(sc, 0) == EJUSTRETURN)
|
||||
return(0);
|
||||
break;
|
||||
}
|
||||
|
||||
/* Update the media status. */
|
||||
nsgphy_status(sc);
|
||||
|
||||
/* Callback if something changed. */
|
||||
if (sc->mii_active != mii->mii_media_active || cmd == MII_MEDIACHG) {
|
||||
MIIBUS_STATCHG(sc->mii_dev);
|
||||
sc->mii_active = mii->mii_media_active;
|
||||
}
|
||||
return (0);
|
||||
}
|
||||
|
||||
void
|
||||
nsgphy_status(sc)
|
||||
struct mii_softc *sc;
|
||||
{
|
||||
struct mii_data *mii = sc->mii_pdata;
|
||||
int bmsr, bmcr, physup, anlpar, gstat;
|
||||
|
||||
mii->mii_media_status = IFM_AVALID;
|
||||
mii->mii_media_active = IFM_ETHER;
|
||||
|
||||
bmsr = PHY_READ(sc, NSGPHY_MII_BMSR);
|
||||
physup = PHY_READ(sc, NSGPHY_MII_PHYSUP);
|
||||
if (physup & NSGPHY_PHYSUP_LNKSTS)
|
||||
mii->mii_media_status |= IFM_ACTIVE;
|
||||
|
||||
bmcr = PHY_READ(sc, NSGPHY_MII_BMCR);
|
||||
|
||||
if (bmcr & NSGPHY_BMCR_LOOP)
|
||||
mii->mii_media_active |= IFM_LOOP;
|
||||
|
||||
if (bmcr & NSGPHY_BMCR_AUTOEN) {
|
||||
if ((bmsr & NSGPHY_BMSR_ACOMP) == 0) {
|
||||
/* Erg, still trying, I guess... */
|
||||
mii->mii_media_active |= IFM_NONE;
|
||||
return;
|
||||
}
|
||||
anlpar = PHY_READ(sc, NSGPHY_MII_ANLPAR);
|
||||
gstat = PHY_READ(sc, NSGPHY_MII_1000STS);
|
||||
if (gstat & NSGPHY_1000STS_LPFD)
|
||||
mii->mii_media_active |= IFM_1000_TX|IFM_FDX;
|
||||
else if (gstat & NSGPHY_1000STS_LPHD)
|
||||
mii->mii_media_active |= IFM_1000_TX|IFM_HDX;
|
||||
else if (anlpar & NSGPHY_ANLPAR_100T4)
|
||||
mii->mii_media_active |= IFM_100_T4;
|
||||
else if (anlpar & NSGPHY_ANLPAR_100FDX)
|
||||
mii->mii_media_active |= IFM_100_TX|IFM_FDX;
|
||||
else if (anlpar & NSGPHY_ANLPAR_100HDX)
|
||||
mii->mii_media_active |= IFM_100_TX;
|
||||
else if (anlpar & NSGPHY_ANLPAR_10FDX)
|
||||
mii->mii_media_active |= IFM_10_T|IFM_FDX;
|
||||
else if (anlpar & NSGPHY_ANLPAR_10HDX)
|
||||
mii->mii_media_active |= IFM_10_T|IFM_HDX;
|
||||
else
|
||||
mii->mii_media_active |= IFM_NONE;
|
||||
return;
|
||||
}
|
||||
|
||||
switch(bmcr & (NSGPHY_BMCR_SPD1|NSGPHY_BMCR_SPD0)) {
|
||||
case NSGPHY_S1000:
|
||||
mii->mii_media_active |= IFM_1000_TX;
|
||||
break;
|
||||
case NSGPHY_S100:
|
||||
mii->mii_media_active |= IFM_100_TX;
|
||||
break;
|
||||
case NSGPHY_S10:
|
||||
mii->mii_media_active |= IFM_10_T;
|
||||
break;
|
||||
default:
|
||||
break;
|
||||
}
|
||||
|
||||
if (bmcr & NSGPHY_BMCR_FDX)
|
||||
mii->mii_media_active |= IFM_FDX;
|
||||
else
|
||||
mii->mii_media_active |= IFM_HDX;
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
static int
|
||||
nsgphy_mii_phy_auto(mii, waitfor)
|
||||
struct mii_softc *mii;
|
||||
int waitfor;
|
||||
{
|
||||
int bmsr, ktcr = 0, i;
|
||||
|
||||
if ((mii->mii_flags & MIIF_DOINGAUTO) == 0) {
|
||||
mii_phy_reset(mii);
|
||||
PHY_WRITE(mii, NSGPHY_MII_BMCR, 0);
|
||||
DELAY(1000);
|
||||
ktcr = PHY_READ(mii, NSGPHY_MII_1000CTL);
|
||||
PHY_WRITE(mii, NSGPHY_MII_1000CTL, ktcr |
|
||||
(NSGPHY_1000CTL_AFD|NSGPHY_1000CTL_AHD));
|
||||
ktcr = PHY_READ(mii, NSGPHY_MII_1000CTL);
|
||||
DELAY(1000);
|
||||
PHY_WRITE(mii, NSGPHY_MII_ANAR,
|
||||
BMSR_MEDIA_TO_ANAR(mii->mii_capabilities) | ANAR_CSMA);
|
||||
DELAY(1000);
|
||||
PHY_WRITE(mii, NSGPHY_MII_BMCR,
|
||||
NSGPHY_BMCR_AUTOEN | NSGPHY_BMCR_STARTNEG);
|
||||
}
|
||||
|
||||
if (waitfor) {
|
||||
/* Wait 500ms for it to complete. */
|
||||
for (i = 0; i < 500; i++) {
|
||||
if ((bmsr = PHY_READ(mii, NSGPHY_MII_BMSR)) &
|
||||
NSGPHY_BMSR_ACOMP)
|
||||
return (0);
|
||||
DELAY(1000);
|
||||
#if 0
|
||||
if ((bmsr & BMSR_ACOMP) == 0)
|
||||
printf("%s: autonegotiation failed to complete\n",
|
||||
mii->mii_dev.dv_xname);
|
||||
#endif
|
||||
}
|
||||
|
||||
/*
|
||||
* Don't need to worry about clearing MIIF_DOINGAUTO.
|
||||
* If that's set, a timeout is pending, and it will
|
||||
* clear the flag.
|
||||
*/
|
||||
return (EIO);
|
||||
}
|
||||
|
||||
/*
|
||||
* Just let it finish asynchronously. This is for the benefit of
|
||||
* the tick handler driving autonegotiation. Don't want 500ms
|
||||
* delays all the time while the system is running!
|
||||
*/
|
||||
if ((mii->mii_flags & MIIF_DOINGAUTO) == 0) {
|
||||
mii->mii_flags |= MIIF_DOINGAUTO;
|
||||
mii->mii_auto_ch = timeout(mii_phy_auto_timeout, mii, hz >> 1);
|
||||
}
|
||||
return (EJUSTRETURN);
|
||||
}
|
||||
168
sys/dev/mii/nsgphyreg.h
Normal file
168
sys/dev/mii/nsgphyreg.h
Normal file
@ -0,0 +1,168 @@
|
||||
/*
|
||||
* Copyright (c) 2001 Wind River Systems
|
||||
* Copyright (c) 2001
|
||||
* Bill Paul <wpaul@bsdi.com>. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by Bill Paul.
|
||||
* 4. Neither the name of the author nor the names of any co-contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
#ifndef _DEV_MII_NSGPHYREG_H_
|
||||
#define _DEV_MII_NSGPHYREG_H_
|
||||
|
||||
/*
|
||||
* NatSemi DP83891 registers
|
||||
*/
|
||||
|
||||
#define NSGPHY_MII_BMCR 0x00
|
||||
#define NSGPHY_BMCR_RESET 0x8000
|
||||
#define NSGPHY_BMCR_LOOP 0x4000
|
||||
#define NSGPHY_BMCR_SPD0 0x2000 /* speed select, lower bit */
|
||||
#define NSGPHY_BMCR_AUTOEN 0x1000 /* Autoneg enabled */
|
||||
#define NSGPHY_BMCR_PDOWN 0x0800 /* Power down */
|
||||
#define NSGPHY_BMCR_ISO 0x0400 /* Isolate */
|
||||
#define NSGPHY_BMCR_STARTNEG 0x0200 /* Restart autoneg */
|
||||
#define NSGPHY_BMCR_FDX 0x0100 /* Duplex mode */
|
||||
#define NSGPHY_BMCR_CTEST 0x0080 /* Collision test enable */
|
||||
#define NSGPHY_BMCR_SPD1 0x0040 /* Speed select, upper bit */
|
||||
|
||||
#define NSGPHY_S1000 NSGPHY_BMCR_SPD1 /* 1000mbps */
|
||||
#define NSGPHY_S100 NSGPHY_BMCR_SPD0 /* 100mpbs */
|
||||
#define NSGPHY_S10 0 /* 10mbps */
|
||||
|
||||
#define NSGPHY_MII_BMSR 0x01
|
||||
#define NSGPHY_BMSR_100BT4 0x8000 /* 100baseT4 support */
|
||||
#define NSGPHY_BMSR_100FDX 0x4000 /* 100baseTX full duplex */
|
||||
#define NSGPHY_BMSR_100HDX 0x2000 /* 100baseTX half duplex */
|
||||
#define NSGPHY_BMSR_10FDX 0x1000 /* 10baseT full duplex */
|
||||
#define NSGPHY_BMSR_10HDX 0x0800 /* 10baseT half duplex */
|
||||
#define NSGPHY_BMSR_100T2FDX 0x0400 /* 100baseT2 full duplex */
|
||||
#define NSGPHY_BMSR_100T2HDX 0x0200 /* 100baseT2 full duplex */
|
||||
#define NSGPHY_BMSR_EXTSTS 0x0100 /* 1000baseT Extended status present */
|
||||
#define NSGPHY_BMSR_PRESUB 0x0040 /* Preamble surpression */
|
||||
#define NSGPHY_BMSR_ACOMP 0x0020 /* Autoneg complete */
|
||||
#define NSGPHY_BMSR_RFAULT 0x0010 /* Remote fault condition occured */
|
||||
#define NSGPHY_BMSR_ANEG 0x0008 /* Autoneg capable */
|
||||
#define NSGPHY_BMSR_LINK 0x0004 /* Link status */
|
||||
#define NSGPHY_BMSR_JABBER 0x0002 /* Jabber detected */
|
||||
#define NSGPHY_BMSR_EXT 0x0001 /* Extended capability */
|
||||
|
||||
#define NSGPHY_MII_ANAR 0x04
|
||||
#define NSGPHY_ANAR_NP 0x8000 /* Next page */
|
||||
#define NSGPHY_ANAR_RF 0x2000 /* Remote fault */
|
||||
#define NSGPHY_ANAR_ASP 0x0800 /* Asymetric Pause */
|
||||
#define NSGPHY_ANAR_PC 0x0400 /* Pause capable */
|
||||
#define NSGPHY_ANAR_100T4 0x0200 /* 100baseT4 support */
|
||||
#define NSGPHY_ANAR_100FDX 0x0100 /* 100baseTX full duplex support */
|
||||
#define NSGPHY_ANAR_100HDX 0x0080 /* 100baseTX half duplex support */
|
||||
#define NSGPHY_ANAR_10FDX 0x0040 /* 10baseT full duplex support */
|
||||
#define NSGPHY_ANAR_10HDX 0x0020 /* 10baseT half duplex support */
|
||||
#define NSGPHY_ANAR_SEL 0x001F /* selector field, 00001=Ethernet */
|
||||
|
||||
#define NSGPHY_MII_ANLPAR 0x05
|
||||
#define NSGPHY_ANLPAR_NP 0x8000 /* Next page */
|
||||
#define NSGPHY_ANLPAR_RF 0x2000 /* Remote fault */
|
||||
#define NSGPHY_ANLPAR_ASP 0x0800 /* Asymetric Pause */
|
||||
#define NSGPHY_ANLPAR_PC 0x0400 /* Pause capable */
|
||||
#define NSGPHY_ANLPAR_100T4 0x0200 /* 100baseT4 support */
|
||||
#define NSGPHY_ANLPAR_100FDX 0x0100 /* 100baseTX full duplex support */
|
||||
#define NSGPHY_ANLPAR_100HDX 0x0080 /* 100baseTX half duplex support */
|
||||
#define NSGPHY_ANLPAR_10FDX 0x0040 /* 10baseT full duplex support */
|
||||
#define NSGPHY_ANLPAR_10HDX 0x0020 /* 10baseT half duplex support */
|
||||
#define NSGPHY_ANLPAR_SEL 0x001F /* selector field, 00001=Ethernet */
|
||||
|
||||
#define NSGPHY_SEL_TYPE 0x0001 /* ethernet */
|
||||
|
||||
#define NSGPHY_MII_ANER 0x06
|
||||
#define NSGPHY_ANER_PDF 0x0010 /* Parallel detection fault */
|
||||
#define NSGPHY_ANER_LPNP 0x0008 /* Link partner can next page */
|
||||
#define NSGPHY_ANER_NP 0x0004 /* Local PHY can next page */
|
||||
#define NSGPHY_ANER_RX 0x0002 /* Next page received */
|
||||
#define NSGPHY_ANER_LPAN 0x0001 /* Link partner autoneg capable */
|
||||
|
||||
#define NSGPHY_MII_NEXTP 0x07 /* Next page */
|
||||
#define NSGPHY_NEXTP_NP 0x8000 /* Next page indication */
|
||||
#define NSGPHY_NEXTP_MP 0x2000 /* Message page */
|
||||
#define NSGPHY_NEXTP_ACK2 0x1000 /* Acknowledge 2 */
|
||||
#define NSGPHY_NEXTP_TOGGLE 0x0800 /* Toggle */
|
||||
#define NSGPHY_NEXTP_CODE 0x07FF /* Code field */
|
||||
|
||||
#define NSGPHY_MII_NEXTP_LP 0x08 /* Next page of link partner */
|
||||
#define NSGPHY_NEXTPLP_NP 0x8000 /* Next page indication */
|
||||
#define NSGPHY_NEXTPLP_MP 0x2000 /* Message page */
|
||||
#define NSGPHY_NEXTPLP_ACK2 0x1000 /* Acknowledge 2 */
|
||||
#define NSGPHY_NEXTPLP_TOGGLE 0x0800 /* Toggle */
|
||||
#define NSGPHY_NEXTPLP_CODE 0x07FF /* Code field */
|
||||
|
||||
#define NSGPHY_MII_1000CTL 0x09 /* 1000baseT control */
|
||||
#define NSGPHY_1000CTL_TST 0xE000 /* test modes */
|
||||
#define NSGPHY_1000CTL_MSE 0x1000 /* Master/Slave config enable */
|
||||
#define NSGPHY_1000CTL_MSC 0x0800 /* Master/Slave setting */
|
||||
#define NSGPHY_1000CTL_RD 0x0400 /* Port type: Repeater/DTE */
|
||||
#define NSGPHY_1000CTL_AFD 0x0200 /* Advertise full duplex */
|
||||
#define NSGPHY_1000CTL_AHD 0x0100 /* Advertise half duplex */
|
||||
|
||||
#define NSGPHY_MII_1000STS 0x0A /* 1000baseT status */
|
||||
#define NSGPHY_1000STS_MSF 0x8000 /* Master/slave fault */
|
||||
#define NSGPHY_1000STS_MSR 0x4000 /* Master/slave result */
|
||||
#define NSGPHY_1000STS_LRS 0x2000 /* Local receiver status */
|
||||
#define NSGPHY_1000STS_RRS 0x1000 /* Remote receiver status */
|
||||
#define NSGPHY_1000STS_LPFD 0x0800 /* Link partner can FD */
|
||||
#define NSGPHY_1000STS_LPHD 0x0400 /* Link partner can HD */
|
||||
#define NSGPHY_1000STS_ASM_DIR 0x0200 /* Asymetric pause capable */
|
||||
#define NSGPHY_1000STS_IEC 0x00FF /* Idle error count */
|
||||
|
||||
#define NSGPHY_MII_EXTSTS 0x0F /* Extended status */
|
||||
#define NSGPHY_EXTSTS_X_FD_CAP 0x8000 /* 1000base-X FD capable */
|
||||
#define NSGPHY_EXTSTS_X_HD_CAP 0x4000 /* 1000base-X HD capable */
|
||||
#define NSGPHY_EXTSTS_T_FD_CAP 0x2000 /* 1000base-T FD capable */
|
||||
#define NSGPHY_EXTSTS_T_HD_CAP 0x1000 /* 1000base-T HD capable */
|
||||
|
||||
#define NSGPHY_MII_STRAPOPT 0x10 /* Strap options */
|
||||
#define NSGPHY_STRAPOPT_PHYADDR 0xF800 /* PHY address */
|
||||
#define NSGPHY_STRAPOPT_COMPAT 0x0400 /* Broadcom compat mode */
|
||||
#define NSGPHY_STRAPOPT_MMSE 0x0200 /* Manual master/slave enable */
|
||||
#define NSGPHY_STRAPOPT_ANEG 0x0100 /* Autoneg enable */
|
||||
#define NSGPHY_STRAPOPT_MMSV 0x0080 /* Manual master/slave setting */
|
||||
#define NSGPHY_STRAPOPT_1000HDX 0x0010 /* Advertise 1000 half-duplex */
|
||||
#define NSGPHY_STRAPOPT_1000FDX 0x0008 /* Advertise 1000 full-duplex */
|
||||
#define NSGPHY_STRAPOPT_100_ADV 0x0004 /* Advertise 100 full/half-duplex */
|
||||
#define NSGPHY_STRAPOPT_SPDSEL 0x0003 /* speed selection */
|
||||
|
||||
#define NSGPHY_MII_PHYSUP 0x11 /* PHY support/current status */
|
||||
#define NSGPHY_PHYSUP_SPDSTS 0x0018 /* speed status */
|
||||
#define NSGPHY_PHYSUP_LNKSTS 0x0004 /* link status */
|
||||
#define NSGPHY_PHYSUP_DUPSTS 0x0002 /* duplex status 1 == full */
|
||||
#define NSGPHY_PHYSUP_10BT 0x0001 /* 10baseT resolved */
|
||||
|
||||
#define NSGPHY_SPDSTS_1000 0x0010
|
||||
#define NSGPHY_SPDSTS_100 0x0008
|
||||
#define NSGPHY_SPDSTS_10 0x0000
|
||||
|
||||
#endif /* _DEV_NSGPHY_MIIREG_H_ */
|
||||
2006
sys/dev/nge/if_nge.c
Normal file
2006
sys/dev/nge/if_nge.c
Normal file
File diff suppressed because it is too large
Load Diff
706
sys/dev/nge/if_ngereg.h
Normal file
706
sys/dev/nge/if_ngereg.h
Normal file
@ -0,0 +1,706 @@
|
||||
/*
|
||||
* Copyright (c) 2001 Wind River Systems
|
||||
* Copyright (c) 1997, 1998, 1999, 2000, 2001
|
||||
* Bill Paul <wpaul@bsdi.com>. All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions
|
||||
* are met:
|
||||
* 1. Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* 3. All advertising materials mentioning features or use of this software
|
||||
* must display the following acknowledgement:
|
||||
* This product includes software developed by Bill Paul.
|
||||
* 4. Neither the name of the author nor the names of any co-contributors
|
||||
* may be used to endorse or promote products derived from this software
|
||||
* without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
|
||||
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
|
||||
* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||
* THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
||||
#define NGE_CSR 0x00
|
||||
#define NGE_CFG 0x04
|
||||
#define NGE_MEAR 0x08
|
||||
#define NGE_PCITST 0x0C
|
||||
#define NGE_ISR 0x10
|
||||
#define NGE_IMR 0x14
|
||||
#define NGE_IER 0x18
|
||||
#define NGE_IHR 0x1C
|
||||
#define NGE_TX_LISTPTR_LO 0x20
|
||||
#define NGE_TX_LISTPTR_HI 0x24
|
||||
#define NGE_TX_LISTPTR NGE_TX_LISTPTR_LO
|
||||
#define NGE_TX_CFG 0x28
|
||||
#define NGE_GPIO 0x2C
|
||||
#define NGE_RX_LISTPTR_LO 0x30
|
||||
#define NGE_RX_LISTPTR_HI 0x34
|
||||
#define NGE_RX_LISTPTR NGE_RX_LISTPTR_LO
|
||||
#define NGE_RX_CFG 0x38
|
||||
#define NGE_PRIOQCTL 0x3C
|
||||
#define NGE_WOLCSR 0x40
|
||||
#define NGE_PAUSECSR 0x44
|
||||
#define NGE_RXFILT_CTL 0x48
|
||||
#define NGE_RXFILT_DATA 0x4C
|
||||
#define NGE_BOOTROM_ADDR 0x50
|
||||
#define NGE_BOOTROM_DATA 0x54
|
||||
#define NGE_SILICONREV 0x58
|
||||
#define NGE_MIBCTL 0x5C
|
||||
#define NGE_MIB_RXERRPKT 0x60
|
||||
#define NGE_MIB_RXERRFCS 0x64
|
||||
#define NGE_MIB_RXERRMISSEDPKT 0x68
|
||||
#define NGE_MIB_RXERRALIGN 0x6C
|
||||
#define NGE_MIB_RXERRSYM 0x70
|
||||
#define NGE_MIB_RXERRGIANT 0x74
|
||||
#define NGE_MIB_RXERRRANGLEN 0x78
|
||||
#define NGE_MIB_RXBADOPCODE 0x7C
|
||||
#define NGE_MIB_RXPAUSEPKTS 0x80
|
||||
#define NGE_MIB_TXPAUSEPKTS 0x84
|
||||
#define NGE_MIB_TXERRSQE 0x88
|
||||
#define NGE_TXPRIOQ_PTR1 0xA0
|
||||
#define NGE_TXPRIOQ_PTR2 0xA4
|
||||
#define NGE_TXPRIOQ_PTR3 0xA8
|
||||
#define NGE_RXPRIOQ_PTR1 0xB0
|
||||
#define NGE_RXPRIOQ_PTR2 0xB4
|
||||
#define NGE_RXPRIOQ_PTR3 0xB8
|
||||
#define NGE_VLAN_IP_RXCTL 0xBC
|
||||
#define NGE_VLAN_IP_TXCTL 0xC0
|
||||
#define NGE_VLAN_DATA 0xC4
|
||||
#define NGE_CLKRUN 0xCC
|
||||
#define NGE_TBI_BMCR 0xE0
|
||||
#define NGE_TBI_BMSR 0xE4
|
||||
#define NGE_TBI_ANAR 0xE8
|
||||
#define NGE_TBI_ANLPAR 0xEC
|
||||
#define NGE_TBI_ANER 0xF0
|
||||
#define NGE_TBI_ESR 0xF4
|
||||
|
||||
/* Control/status register */
|
||||
#define NGE_CSR_TX_ENABLE 0x00000001
|
||||
#define NGE_CSR_TX_DISABLE 0x00000002
|
||||
#define NGE_CSR_RX_ENABLE 0x00000004
|
||||
#define NGE_CSR_RX_DISABLE 0x00000008
|
||||
#define NGE_CSR_TX_RESET 0x00000010
|
||||
#define NGE_CSR_RX_RESET 0x00000020
|
||||
#define NGE_CSR_SOFTINTR 0x00000080
|
||||
#define NGE_CSR_RESET 0x00000100
|
||||
#define NGE_CSR_TX_PRIOQ_ENB0 0x00000200
|
||||
#define NGE_CSR_TX_PRIOQ_ENB1 0x00000400
|
||||
#define NGE_CSR_TX_PRIOQ_ENB2 0x00000800
|
||||
#define NGE_CSR_TX_PRIOQ_ENB3 0x00001000
|
||||
#define NGE_CSR_RX_PRIOQ_ENB0 0x00002000
|
||||
#define NGE_CSR_RX_PRIOQ_ENB1 0x00004000
|
||||
#define NGE_CSR_RX_PRIOQ_ENB2 0x00008000
|
||||
#define NGE_CSR_RX_PRIOQ_ENB3 0x00010000
|
||||
|
||||
/* Configuration register */
|
||||
#define NGE_CFG_BIGENDIAN 0x00000001
|
||||
#define NGE_CFG_EXT_125MHZ 0x00000002
|
||||
#define NGE_CFG_BOOTROM_DIS 0x00000004
|
||||
#define NGE_CFG_PERR_DETECT 0x00000008
|
||||
#define NGE_CFG_DEFER_DISABLE 0x00000010
|
||||
#define NGE_CFG_OUTOFWIN_TIMER 0x00000020
|
||||
#define NGE_CFG_SINGLE_BACKOFF 0x00000040
|
||||
#define NGE_CFG_PCIREQ_ALG 0x00000080
|
||||
#define NGE_CFG_EXTSTS_ENB 0x00000100
|
||||
#define NGE_CFG_PHY_DIS 0x00000200
|
||||
#define NGE_CFG_PHY_RST 0x00000400
|
||||
#define NGE_CFG_64BIT_ADDR_ENB 0x00000800
|
||||
#define NGE_CFG_64BIT_DATA_ENB 0x00001000
|
||||
#define NGE_CFG_64BIT_PCI_DET 0x00002000
|
||||
#define NGE_CFG_64BIT_TARG 0x00004000
|
||||
#define NGE_CFG_MWI_DIS 0x00008000
|
||||
#define NGE_CFG_MRM_DIS 0x00010000
|
||||
#define NGE_CFG_TMRTST 0x00020000
|
||||
#define NGE_CFG_PHYINTR_SPD 0x00040000
|
||||
#define NGE_CFG_PHYINTR_LNK 0x00080000
|
||||
#define NGE_CFG_PHYINTR_DUP 0x00100000
|
||||
#define NGE_CFG_MODE_1000 0x00400000
|
||||
#define NGE_CFG_DUPLEX_STS 0x10000000
|
||||
#define NGE_CFG_SPEED_STS 0x60000000
|
||||
#define NGE_CFG_LINK_STS 0x80000000
|
||||
|
||||
/* MII/EEPROM control register */
|
||||
#define NGE_MEAR_EE_DIN 0x00000001
|
||||
#define NGE_MEAR_EE_DOUT 0x00000002
|
||||
#define NGE_MEAR_EE_CLK 0x00000004
|
||||
#define NGE_MEAR_EE_CSEL 0x00000008
|
||||
#define NGE_MEAR_MII_DATA 0x00000010
|
||||
#define NGE_MEAR_MII_DIR 0x00000020
|
||||
#define NGE_MEAR_MII_CLK 0x00000040
|
||||
|
||||
#define NGE_EECMD_WRITE 0x140
|
||||
#define NGE_EECMD_READ 0x180
|
||||
#define NGE_EECMD_ERASE 0x1c0
|
||||
|
||||
#define NGE_EE_NODEADDR 0xA
|
||||
|
||||
/* PCI control register */
|
||||
#define NGE_PCICTL_SRAMADDR 0x0000001F
|
||||
#define NGE_PCICTL_RAMTSTENB 0x00000020
|
||||
#define NGE_PCICTL_TXTSTENB 0x00000040
|
||||
#define NGE_PCICTL_RXTSTENB 0x00000080
|
||||
#define NGE_PCICTL_BMTSTENB 0x00000200
|
||||
#define NGE_PCICTL_RAMADDR 0x001F0000
|
||||
#define NGE_PCICTL_ROMTIME 0x0F000000
|
||||
#define NGE_PCICTL_DISCTEST 0x40000000
|
||||
|
||||
/* Interrupt/status register */
|
||||
#define NGE_ISR_RX_OK 0x00000001
|
||||
#define NGE_ISR_RX_DESC_OK 0x00000002
|
||||
#define NGE_ISR_RX_ERR 0x00000004
|
||||
#define NGE_ISR_RX_EARLY 0x00000008
|
||||
#define NGE_ISR_RX_IDLE 0x00000010
|
||||
#define NGE_ISR_RX_OFLOW 0x00000020
|
||||
#define NGE_ISR_TX_OK 0x00000040
|
||||
#define NGE_ISR_TX_DESC_OK 0x00000080
|
||||
#define NGE_ISR_TX_ERR 0x00000100
|
||||
#define NGE_ISR_TX_IDLE 0x00000200
|
||||
#define NGE_ISR_TX_UFLOW 0x00000400
|
||||
#define NGE_ISR_MIB_SERVICE 0x00000800
|
||||
#define NGE_ISR_SOFTINTR 0x00001000
|
||||
#define NGE_ISR_PME_EVENT 0x00002000
|
||||
#define NGE_ISR_PHY_INTR 0x00004000
|
||||
#define NGE_ISR_HIBITS 0x00008000
|
||||
#define NGE_ISR_RX_FIFO_OFLOW 0x00010000
|
||||
#define NGE_ISR_TGT_ABRT 0x00020000
|
||||
#define NGE_ISR_BM_ABRT 0x00040000
|
||||
#define NGE_ISR_SYSERR 0x00080000
|
||||
#define NGE_ISR_PARITY_ERR 0x00100000
|
||||
#define NGE_ISR_RX_RESET_DONE 0x00200000
|
||||
#define NGE_ISR_TX_RESET_DONE 0x00400000
|
||||
#define NGE_ISR_RX_PRIOQ_DESC0 0x00800000
|
||||
#define NGE_ISR_RX_PRIOQ_DESC1 0x01000000
|
||||
#define NGE_ISR_RX_PRIOQ_DESC2 0x02000000
|
||||
#define NGE_ISR_RX_PRIOQ_DESC3 0x04000000
|
||||
#define NGE_ISR_TX_PRIOQ_DESC0 0x08000000
|
||||
#define NGE_ISR_TX_PRIOQ_DESC1 0x10000000
|
||||
#define NGE_ISR_TX_PRIOQ_DESC2 0x20000000
|
||||
#define NGE_ISR_TX_PRIOQ_DESC3 0x40000000
|
||||
|
||||
/* Interrupt mask register */
|
||||
#define NGE_IMR_RX_OK 0x00000001
|
||||
#define NGE_IMR_RX_DESC_OK 0x00000002
|
||||
#define NGE_IMR_RX_ERR 0x00000004
|
||||
#define NGE_IMR_RX_EARLY 0x00000008
|
||||
#define NGE_IMR_RX_IDLE 0x00000010
|
||||
#define NGE_IMR_RX_OFLOW 0x00000020
|
||||
#define NGE_IMR_TX_OK 0x00000040
|
||||
#define NGE_IMR_TX_DESC_OK 0x00000080
|
||||
#define NGE_IMR_TX_ERR 0x00000100
|
||||
#define NGE_IMR_TX_IDLE 0x00000200
|
||||
#define NGE_IMR_TX_UFLOW 0x00000400
|
||||
#define NGE_IMR_MIB_SERVICE 0x00000800
|
||||
#define NGE_IMR_SOFTINTR 0x00001000
|
||||
#define NGE_IMR_PME_EVENT 0x00002000
|
||||
#define NGE_IMR_PHY_INTR 0x00004000
|
||||
#define NGE_IMR_HIBITS 0x00008000
|
||||
#define NGE_IMR_RX_FIFO_OFLOW 0x00010000
|
||||
#define NGE_IMR_TGT_ABRT 0x00020000
|
||||
#define NGE_IMR_BM_ABRT 0x00040000
|
||||
#define NGE_IMR_SYSERR 0x00080000
|
||||
#define NGE_IMR_PARITY_ERR 0x00100000
|
||||
#define NGE_IMR_RX_RESET_DONE 0x00200000
|
||||
#define NGE_IMR_TX_RESET_DONE 0x00400000
|
||||
#define NGE_IMR_RX_PRIOQ_DESC0 0x00800000
|
||||
#define NGE_IMR_RX_PRIOQ_DESC1 0x01000000
|
||||
#define NGE_IMR_RX_PRIOQ_DESC2 0x02000000
|
||||
#define NGE_IMR_RX_PRIOQ_DESC3 0x04000000
|
||||
#define NGE_IMR_TX_PRIOQ_DESC0 0x08000000
|
||||
#define NGE_IMR_TX_PRIOQ_DESC1 0x10000000
|
||||
#define NGE_IMR_TX_PRIOQ_DESC2 0x20000000
|
||||
#define NGE_IMR_TX_PRIOQ_DESC3 0x40000000
|
||||
|
||||
#define NGE_INTRS \
|
||||
(NGE_IMR_RX_OFLOW|NGE_IMR_TX_UFLOW|NGE_IMR_TX_OK|\
|
||||
NGE_IMR_TX_IDLE|NGE_IMR_RX_OK|NGE_IMR_RX_ERR|\
|
||||
NGE_IMR_SYSERR|NGE_IMR_PHY_INTR)
|
||||
|
||||
/* Interrupt enable register */
|
||||
#define NGE_IER_INTRENB 0x00000001
|
||||
|
||||
/* Interrupt moderation timer register */
|
||||
#define NGE_IHR_HOLDOFF 0x000000FF
|
||||
#define NGE_IHR_HOLDCTL 0x00000100
|
||||
|
||||
/* Transmit configuration register */
|
||||
#define NGE_TXCFG_DRAIN_THRESH 0x000000FF /* 32-byte units */
|
||||
#define NGE_TXCFG_FILL_THRESH 0x0000FF00 /* 32-byte units */
|
||||
#define NGE_1000MB_BURST_DIS 0x00080000
|
||||
#define NGE_TXCFG_DMABURST 0x00700000
|
||||
#define NGE_TXCFG_ECRETRY 0x00800000
|
||||
#define NGE_TXCFG_AUTOPAD 0x10000000
|
||||
#define NGE_TXCFG_LOOPBK 0x20000000
|
||||
#define NGE_TXCFG_IGN_HBEAT 0x40000000
|
||||
#define NGE_TXCFG_IGN_CARR 0x80000000
|
||||
|
||||
#define NGE_TXCFG_DRAIN(x) (((x) >> 5) & NGE_TXCFG_DRAIN_THRESH)
|
||||
#define NGE_TXCFG_FILL(x) ((((x) >> 5) << 8) & NGE_TXCFG_FILL_THRESH)
|
||||
|
||||
#define NGE_TXDMA_1024BYTES 0x00000000
|
||||
#define NGE_TXDMA_8BYTES 0x00100000
|
||||
#define NGE_TXDMA_16BYTES 0x00200000
|
||||
#define NGE_TXDMA_32BYTES 0x00300000
|
||||
#define NGE_TXDMA_64BYTES 0x00400000
|
||||
#define NGE_TXDMA_128BYTES 0x00500000
|
||||
#define NGE_TXDMA_256BYTES 0x00600000
|
||||
#define NGE_TXDMA_512BYTES 0x00700000
|
||||
|
||||
#define NGE_TXCFG_100 \
|
||||
(NGE_TXDMA_64BYTES|NGE_TXCFG_AUTOPAD|\
|
||||
NGE_TXCFG_FILL(64)|NGE_TXCFG_DRAIN(1536))
|
||||
|
||||
#define NGE_TXCFG_10 \
|
||||
(NGE_TXDMA_32BYTES|NGE_TXCFG_AUTOPAD|\
|
||||
NGE_TXCFG_FILL(64)|NGE_TXCFG_DRAIN(1536))
|
||||
|
||||
#define NGE_TXCFG \
|
||||
(NGE_TXDMA_512BYTES|NGE_TXCFG_AUTOPAD|\
|
||||
NGE_TXCFG_FILL(64)|NGE_TXCFG_DRAIN(6400))
|
||||
|
||||
/* GPIO register */
|
||||
#define NGE_GPIO_GP1_OUT 0x00000001
|
||||
#define NGE_GPIO_GP2_OUT 0x00000002
|
||||
#define NGE_GPIO_GP3_OUT 0x00000004
|
||||
#define NGE_GPIO_GP4_OUT 0x00000008
|
||||
#define NGE_GPIO_GP5_OUT 0x00000010
|
||||
#define NGE_GPIO_GP1_OUTENB 0x00000020
|
||||
#define NGE_GPIO_GP2_OUTENB 0x00000040
|
||||
#define NGE_GPIO_GP3_OUTENB 0x00000080
|
||||
#define NGE_GPIO_GP4_OUTENB 0x00000100
|
||||
#define NGE_GPIO_GP5_OUTENB 0x00000200
|
||||
#define NGE_GPIO_GP1_IN 0x00000400
|
||||
#define NGE_GPIO_GP2_IN 0x00000800
|
||||
#define NGE_GPIO_GP3_IN 0x00001000
|
||||
#define NGE_GPIO_GP4_IN 0x00002000
|
||||
#define NGE_GPIO_GP5_IN 0x00004000
|
||||
|
||||
/* Receive configuration register */
|
||||
#define NGE_RXCFG_DRAIN_THRESH 0x0000003E /* 8-byte units */
|
||||
#define NGE_RXCFG_DMABURST 0x00700000
|
||||
#define NGE_RXCFG_RX_RANGEERR 0x04000000 /* accept in-range err frames */
|
||||
#define NGE_RXCFG_RX_GIANTS 0x08000000 /* accept packets > 1518 bytes */
|
||||
#define NGE_RXCFG_RX_FDX 0x10000000 /* full duplex receive */
|
||||
#define NGE_RXCFG_RX_NOCRC 0x20000000 /* strip CRC */
|
||||
#define NGE_RXCFG_RX_RUNT 0x40000000 /* accept short frames */
|
||||
#define NGE_RXCFG_RX_BADPKTS 0x80000000 /* accept error frames */
|
||||
|
||||
#define NGE_RXCFG_DRAIN(x) ((((x) >> 3) << 1) & NGE_RXCFG_DRAIN_THRESH)
|
||||
|
||||
#define NGE_RXDMA_1024BYTES 0x00000000
|
||||
#define NGE_RXDMA_8BYTES 0x00100000
|
||||
#define NGE_RXDMA_16BYTES 0x00200000
|
||||
#define NGE_RXDMA_32YTES 0x00300000
|
||||
#define NGE_RXDMA_64BYTES 0x00400000
|
||||
#define NGE_RXDMA_128BYTES 0x00500000
|
||||
#define NGE_RXDMA_256BYTES 0x00600000
|
||||
#define NGE_RXDMA_512BYTES 0x00700000
|
||||
|
||||
#define NGE_RXCFG \
|
||||
(NGE_RXCFG_DRAIN(64)|NGE_RXDMA_256BYTES|\
|
||||
NGE_RXCFG_RX_GIANTS|NGE_RXCFG_RX_NOCRC)
|
||||
|
||||
/* Priority queue control */
|
||||
#define NGE_PRIOQCTL_TXPRIO_ENB 0x00000001
|
||||
#define NGE_PRIOQCTL_TXFAIR_ENB 0x00000002
|
||||
#define NGE_PRIOQCTL_RXPRIO 0x0000000C
|
||||
|
||||
#define NGE_RXPRIOQ_DISABLED 0x00000000
|
||||
#define NGE_RXPRIOQ_TWOQS 0x00000004
|
||||
#define NGE_RXPRIOQ_THREEQS 0x00000008
|
||||
#define NGE_RXPRIOQ_FOURQS 0x0000000C
|
||||
|
||||
/* Wake On LAN command/status register */
|
||||
#define NGE_WOLCSR_WAKE_ON_PHYINTR 0x00000001
|
||||
#define NGE_WOLCSR_WAKE_ON_UNICAST 0x00000002
|
||||
#define NGE_WOLCSR_WAKE_ON_MULTICAST 0x00000004
|
||||
#define NGR_WOLCSR_WAKE_ON_BROADCAST 0x00000008
|
||||
#define NGE_WOLCSR_WAKE_ON_ARP 0x00000010
|
||||
#define NGE_WOLCSR_WAKE_ON_PAT0_MATCH 0x00000020
|
||||
#define NGE_WOLCSR_WAKE_ON_PAT1_MATCH 0x00000040
|
||||
#define NGE_WOLCSR_WAKE_ON_PAT2_MATCH 0x00000080
|
||||
#define NGE_WOLCSR_WAKE_ON_PAT3_MATCH 0x00000100
|
||||
#define NGE_WOLCSR_SECUREON_ENB 0x00000200
|
||||
#define NGE_WOLCSR_SECUREON_HACK 0x00200000
|
||||
#define NGE_WOLCSR_PHYINTR 0x00400000
|
||||
#define NGE_WOLCSR_UNICAST 0x00800000
|
||||
#define NGE_WOLCSR_MULTICAST 0x01000000
|
||||
#define NGE_WOLCSR_BROADCAST 0x02000000
|
||||
#define NGE_WOLCSR_ARP_RCVD 0x04000000
|
||||
#define NGE_WOLCSR_PAT0_MATCH 0x08000000
|
||||
#define NGE_WOLCSR_PAT1_MATCH 0x10000000
|
||||
#define NGE_WOLCSR_PAT2_MATCH 0x20000000
|
||||
#define NGE_WOLCSR_PAT3_MATCH 0x40000000
|
||||
#define NGE_WOLCSR_MAGICPKT 0x80000000
|
||||
|
||||
/* Pause control/status register */
|
||||
#define NGE_PAUSECSR_CNT 0x0000FFFF
|
||||
#define NGE_PAUSECSR_PFRAME_SENT 0x00020000
|
||||
#define NGE_PAUSECSR_RX_DATAFIFO_THR_LO 0x000C0000
|
||||
#define NGE_PAUSECSR_RX_DATAFIFO_THR_HI 0x00300000
|
||||
#define NGE_PAUSECSR_RX_STATFIFO_THR_LO 0x00C00000
|
||||
#define NGE_PAUSECSR_RX_STATFIFO_THR_HI 0x03000000
|
||||
#define NGE_PAUSECSR_PFRAME_RCVD 0x08000000
|
||||
#define NGE_PAUSECSR_PAUSE_ACTIVE 0x10000000
|
||||
#define NGE_PAUSECSR_PAUSE_ON_DA 0x20000000 /* pause on direct addr */
|
||||
#define NGE_PAUSECSR_PAUSE_ON_MCAST 0x40000000 /* pause on mcast */
|
||||
#define NGE_PAUSECSR_PAUSE_ENB 0x80000000
|
||||
|
||||
/* Receive filter/match control message */
|
||||
#define MGE_RXFILTCTL_ADDR 0x000003FF
|
||||
#define NGE_RXFILTCTL_ULMASK 0x00080000
|
||||
#define NGE_RXFILTCTL_UCHASH 0x00100000
|
||||
#define NGE_RXFILTCTL_MCHASH 0x00200000
|
||||
#define NGE_RXFILTCTL_ARP 0x00400000
|
||||
#define NGE_RXFILTCTL_PMATCH0 0x00800000
|
||||
#define NGE_RXFILTCTL_PMATCH1 0x01000000
|
||||
#define NGE_RXFILTCTL_PMATCH2 0x02000000
|
||||
#define NGE_RXFILTCTL_PMATCH3 0x04000000
|
||||
#define NGE_RXFILTCTL_PERFECT 0x08000000
|
||||
#define NGE_RXFILTCTL_ALLPHYS 0x10000000
|
||||
#define NGE_RXFILTCTL_ALLMULTI 0x20000000
|
||||
#define NGE_RXFILTCTL_BROAD 0x40000000
|
||||
#define NGE_RXFILTCTL_ENABLE 0x80000000
|
||||
|
||||
|
||||
#define NGE_FILTADDR_PAR0 0x00000000
|
||||
#define NGE_FILTADDR_PAR1 0x00000002
|
||||
#define NGE_FILTADDR_PAR2 0x00000004
|
||||
#define NGE_FILTADDR_PMATCH0 0x00000006
|
||||
#define NGE_FILTADDR_PMATCH1 0x00000008
|
||||
#define NGE_FILTADDR_SOPASS0 0x0000000A
|
||||
#define NGE_FILTADDR_SOPASS1 0x0000000C
|
||||
#define NGE_FILTADDR_SOPASS2 0x0000000E
|
||||
#define NGE_FILTADDR_FMEM_LO 0x00000100
|
||||
#define NGE_FILTADDR_FMEM_HI 0x000003FE
|
||||
#define NGE_FILTADDR_MCAST_LO 0x00000100 /* start of multicast filter */
|
||||
#define NGE_FILTADDR_MCAST_HI 0x000001FE /* end of multicast filter */
|
||||
#define NGE_MCAST_FILTER_LEN 256 /* bytes */
|
||||
#define NGE_FILTADDR_PBUF0 0x00000200 /* pattern buffer 0 */
|
||||
#define NGE_FILTADDR_PBUF1 0x00000280 /* pattern buffer 1 */
|
||||
#define NGE_FILTADDR_PBUF2 0x00000300 /* pattern buffer 2 */
|
||||
#define NGE_FILTADDR_PBUF3 0x00000380 /* pattern buffer 3 */
|
||||
|
||||
/* MIB control register */
|
||||
#define NGE_MIBCTL_WARNTEST 0x00000001
|
||||
#define NGE_MIBCTL_FREEZE_CNT 0x00000002
|
||||
#define NGE_MIBCTL_CLEAR_CNT 0x00000004
|
||||
#define NGE_MIBCTL_STROBE_CNT 0x00000008
|
||||
|
||||
/* VLAN/IP RX control register */
|
||||
#define NGE_VIPRXCTL_TAG_DETECT_ENB 0x00000001
|
||||
#define NGE_VIPRXCTL_TAG_STRIP_ENB 0x00000002
|
||||
#define NGE_VIPRXCTL_DROP_TAGGEDPKTS 0x00000004
|
||||
#define NGE_VIPRXCTL_DROP_UNTAGGEDPKTS 0x00000008
|
||||
#define NGE_VIPRXCTL_IPCSUM_ENB 0x00000010
|
||||
#define NGE_VIPRXCTL_REJECT_BADIPCSUM 0x00000020
|
||||
#define NGE_VIPRXCTL_REJECT_BADTCPCSUM 0x00000040
|
||||
#define NGE_VIPRXCTL_REJECT_BADUDPCSUM 0x00000080
|
||||
|
||||
/* VLAN/IP TX control register */
|
||||
#define NGE_VIPTXCTL_TAG_ALL 0x00000001
|
||||
#define NGE_VIPTXCTL_TAG_PER_PKT 0x00000002
|
||||
#define NGE_VIPTXCTL_CSUM_ALL 0x00000004
|
||||
#define NGE_VIPTXCTL_CSUM_PER_PKT 0x00000008
|
||||
|
||||
/* VLAN data register */
|
||||
#define NGE_VLANDATA_VTYPE 0x0000FFFF
|
||||
#define NGE_VLANDATA_VTCI 0xFFFF0000
|
||||
|
||||
/* Clockrun register */
|
||||
#define NGE_CLKRUN_PMESTS 0x00008000
|
||||
#define NGE_CLKRUN_PMEENB 0x00000100
|
||||
#define NGE_CLNRUN_CLKRUN_ENB 0x00000001
|
||||
|
||||
|
||||
/* TBI BMCR */
|
||||
#define NGE_TBIBMCR_RESTART_ANEG 0x00000200
|
||||
#define NGE_TBIBMCR_ENABLE_ANEG 0x00001000
|
||||
#define NGE_TBIBMCR_LOOPBACK 0x00004000
|
||||
|
||||
/* TBI BMSR */
|
||||
#define NGE_TBIBMSR_ANEG_DONE 0x00000004
|
||||
#define NGE_TBIBMSR_LINKSTAT 0x00000020
|
||||
|
||||
/* TBI ANAR */
|
||||
#define NGE_TBIANAR_HDX 0x00000020
|
||||
#define NGE_TBIANAR_FDX 0x00000040
|
||||
#define NGE_TBIANAR_PCAP 0x00000180
|
||||
#define NGE_TBIANAR_REMFAULT 0x00003000
|
||||
#define NGE_TBIANAR_NEXTPAGE 0x00008000
|
||||
|
||||
/* TBI ANLPAR */
|
||||
#define NGE_TBIANLPAR_HDX 0x00000020
|
||||
#define NGE_TBIANLPAR_FDX 0x00000040
|
||||
#define NGE_TBIANLPAR_PCAP 0x00000180
|
||||
#define NGE_TBIANLPAR_REMFAULT 0x00003000
|
||||
#define NGE_TBIANLPAR_NEXTPAGE 0x00008000
|
||||
|
||||
/* TBI ANER */
|
||||
#define NGE_TBIANER_PAGERCVD 0x00000002
|
||||
#define NGE_TBIANER_NEXTPGABLE 0x00000004
|
||||
|
||||
/* TBI EXTSTS */
|
||||
#define NGE_TBIEXTSTS_HXD 0x00004000
|
||||
#define NGE_TBIEXTSTS_FXD 0x00008000
|
||||
|
||||
/*
|
||||
* DMA descriptor structures. The RX and TX descriptor formats are
|
||||
* deliberately designed to be similar to facilitate passing them between
|
||||
* RX and TX queues on multiple controllers, in the case where you have
|
||||
* multiple MACs in a switching configuration. With the 83820, the pointer
|
||||
* values can be either 64 bits or 32 bits depending on how the chip is
|
||||
* configured. For the 83821, the fields are always 32-bits. There is
|
||||
* also an optional extended status field for VLAN and TCP/IP checksum
|
||||
* functions. We use the checksum feature so we enable the use of this
|
||||
* field. Descriptors must be 64-bit aligned.
|
||||
* After this, we include some additional structure members for
|
||||
* use by the driver. Note that for this structure will be a different
|
||||
* size on the alpha, but that's okay as long as it's a multiple of 4
|
||||
* bytes in size.
|
||||
*
|
||||
*/
|
||||
struct nge_desc_64 {
|
||||
/* Hardware descriptor section */
|
||||
u_int32_t nge_next_lo;
|
||||
u_int32_t nge_next_hi;
|
||||
u_int32_t nge_ptr_lo;
|
||||
u_int32_t nge_ptr_hi;
|
||||
u_int32_t nge_cmdsts;
|
||||
#define nge_rxstat nge_cmdsts
|
||||
#define nge_txstat nge_cmdsts
|
||||
#define nge_ctl nge_cmdsts
|
||||
u_int32_t nge_extsts;
|
||||
/* Driver software section */
|
||||
struct mbuf *nge_mbuf;
|
||||
struct nge_desc_64 *nge_nextdesc;
|
||||
};
|
||||
|
||||
struct nge_desc_32 {
|
||||
/* Hardware descriptor section */
|
||||
u_int32_t nge_next;
|
||||
u_int32_t nge_ptr;
|
||||
u_int32_t nge_cmdsts;
|
||||
#define nge_rxstat nge_cmdsts
|
||||
#define nge_txstat nge_cmdsts
|
||||
#define nge_ctl nge_cmdsts
|
||||
u_int32_t nge_extsts;
|
||||
/* Driver software section */
|
||||
struct mbuf *nge_mbuf;
|
||||
struct nge_desc_32 *nge_nextdesc;
|
||||
};
|
||||
|
||||
#define nge_desc nge_desc_32
|
||||
|
||||
#define NGE_CMDSTS_BUFLEN 0x0000FFFF
|
||||
#define NGE_CMDSTS_PKT_OK 0x08000000
|
||||
#define NGE_CMDSTS_CRC 0x10000000
|
||||
#define NGE_CMDSTS_INTR 0x20000000
|
||||
#define NGE_CMDSTS_MORE 0x40000000
|
||||
#define NGE_CMDSTS_OWN 0x80000000
|
||||
|
||||
#define NGE_LASTDESC(x) (!((x)->nge_ctl & NGE_CMDSTS_MORE)))
|
||||
#define NGE_OWNDESC(x) ((x)->nge_ctl & NGE_CMDSTS_OWN)
|
||||
#define NGE_INC(x, y) (x) = (x + 1) % y
|
||||
#define NGE_RXBYTES(x) ((x)->nge_ctl & NGE_CMDSTS_BUFLEN)
|
||||
|
||||
#define NGE_RXSTAT_RANGELENERR 0x00010000
|
||||
#define NGE_RXSTAT_LOOPBK 0x00020000
|
||||
#define NGE_RXSTAT_ALIGNERR 0x00040000
|
||||
#define NGE_RXSTAT_CRCERR 0x00080000
|
||||
#define NGE_RXSTAT_SYMBOLERR 0x00100000
|
||||
#define NGE_RXSTAT_RUNT 0x00200000
|
||||
#define NGE_RXSTAT_GIANT 0x00400000
|
||||
#define NGE_RXSTAT_DSTCLASS 0x01800000
|
||||
#define NGE_RXSTAT_OVERRUN 0x02000000
|
||||
#define NGE_RXSTAT_RX_ABORT 0x04000000
|
||||
|
||||
#define NGE_DSTCLASS_REJECT 0x00000000
|
||||
#define NGE_DSTCLASS_UNICAST 0x00800000
|
||||
#define NGE_DSTCLASS_MULTICAST 0x01000000
|
||||
#define NGE_DSTCLASS_BROADCAST 0x02000000
|
||||
|
||||
#define NGE_TXSTAT_COLLCNT 0x000F0000
|
||||
#define NGE_TXSTAT_EXCESSCOLLS 0x00100000
|
||||
#define NGE_TXSTAT_OUTOFWINCOLL 0x00200000
|
||||
#define NGE_TXSTAT_EXCESS_DEFER 0x00400000
|
||||
#define NGE_TXSTAT_DEFERED 0x00800000
|
||||
#define NGE_TXSTAT_CARR_LOST 0x01000000
|
||||
#define NGE_TXSTAT_UNDERRUN 0x02000000
|
||||
#define NGE_TXSTAT_TX_ABORT 0x04000000
|
||||
|
||||
#define NGE_TXEXTSTS_VLAN_TCI 0x0000FFFF
|
||||
#define NGE_TXEXTSTS_VLANPKT 0x00010000
|
||||
#define NGE_TXEXTSTS_IPCSUM 0x00020000
|
||||
#define NGE_TXEXTSTS_TCPCSUM 0x00080000
|
||||
#define NGE_TXEXTSTS_UDPCSUM 0x00200000
|
||||
|
||||
#define NGE_RXEXTSTS_VTCI 0x0000FFFF
|
||||
#define NGE_RXEXTSTS_VLANPKT 0x00010000
|
||||
#define NGE_RXEXTSTS_IPPKT 0x00020000
|
||||
#define NGE_RXEXTSTS_IPCSUMERR 0x00040000
|
||||
#define NGE_RXEXTSTS_TCPPKT 0x00080000
|
||||
#define NGE_RXEXTSTS_TCPCSUMERR 0x00100000
|
||||
#define NGE_RXEXTSTS_UDPPKT 0x00200000
|
||||
#define NGE_RXEXTSTS_UDPCSUMERR 0x00400000
|
||||
|
||||
#define NGE_RX_LIST_CNT 64
|
||||
#define NGE_TX_LIST_CNT 128
|
||||
|
||||
struct nge_list_data {
|
||||
struct nge_desc nge_rx_list[NGE_RX_LIST_CNT];
|
||||
struct nge_desc nge_tx_list[NGE_TX_LIST_CNT];
|
||||
};
|
||||
|
||||
|
||||
/*
|
||||
* NatSemi PCI vendor ID.
|
||||
*/
|
||||
#define NGE_VENDORID 0x100B
|
||||
|
||||
/*
|
||||
* 83820/83821 PCI device IDs
|
||||
*/
|
||||
#define NGE_DEVICEID 0x0022
|
||||
|
||||
struct nge_type {
|
||||
u_int16_t nge_vid;
|
||||
u_int16_t nge_did;
|
||||
char *nge_name;
|
||||
};
|
||||
|
||||
struct nge_mii_frame {
|
||||
u_int8_t mii_stdelim;
|
||||
u_int8_t mii_opcode;
|
||||
u_int8_t mii_phyaddr;
|
||||
u_int8_t mii_regaddr;
|
||||
u_int8_t mii_turnaround;
|
||||
u_int16_t mii_data;
|
||||
};
|
||||
|
||||
/*
|
||||
* MII constants
|
||||
*/
|
||||
#define NGE_MII_STARTDELIM 0x01
|
||||
#define NGE_MII_READOP 0x02
|
||||
#define NGE_MII_WRITEOP 0x01
|
||||
#define NGE_MII_TURNAROUND 0x02
|
||||
|
||||
#define NGE_JUMBO_FRAMELEN 9018
|
||||
#define NGE_JUMBO_MTU (NGE_JUMBO_FRAMELEN-ETHER_HDR_LEN-ETHER_CRC_LEN)
|
||||
#define NGE_JSLOTS 384
|
||||
|
||||
#define NGE_JRAWLEN (NGE_JUMBO_FRAMELEN + ETHER_ALIGN)
|
||||
#define NGE_JLEN (NGE_JRAWLEN + (sizeof(u_int64_t) - \
|
||||
(NGE_JRAWLEN % sizeof(u_int64_t))))
|
||||
#define NGE_MCLBYTES (NGE_JLEN - sizeof(u_int64_t))
|
||||
#define NGE_JPAGESZ PAGE_SIZE
|
||||
#define NGE_RESID (NGE_JPAGESZ - (NGE_JLEN * NGE_JSLOTS) % NGE_JPAGESZ)
|
||||
#define NGE_JMEM ((NGE_JLEN * NGE_JSLOTS) + NGE_RESID)
|
||||
|
||||
struct nge_jpool_entry {
|
||||
int slot;
|
||||
SLIST_ENTRY(nge_jpool_entry) jpool_entries;
|
||||
};
|
||||
|
||||
struct nge_ring_data {
|
||||
int nge_rx_prod;
|
||||
int nge_tx_prod;
|
||||
int nge_tx_cons;
|
||||
int nge_tx_cnt;
|
||||
/* Stick the jumbo mem management stuff here too. */
|
||||
caddr_t nge_jslots[NGE_JSLOTS];
|
||||
void *nge_jumbo_buf;
|
||||
};
|
||||
|
||||
struct nge_softc {
|
||||
struct arpcom arpcom; /* interface info */
|
||||
bus_space_handle_t nge_bhandle;
|
||||
bus_space_tag_t nge_btag;
|
||||
struct resource *nge_res;
|
||||
struct resource *nge_irq;
|
||||
void *nge_intrhand;
|
||||
device_t nge_miibus;
|
||||
int nge_if_flags;
|
||||
u_int8_t nge_unit;
|
||||
u_int8_t nge_type;
|
||||
u_int8_t nge_link;
|
||||
u_int8_t nge_width;
|
||||
#define NGE_WIDTH_32BITS 0
|
||||
#define NGE_WIDTH_64BITS 1
|
||||
struct nge_list_data *nge_ldata;
|
||||
struct nge_ring_data nge_cdata;
|
||||
struct callout_handle nge_stat_ch;
|
||||
SLIST_HEAD(__nge_jfreehead, nge_jpool_entry) nge_jfree_listhead;
|
||||
SLIST_HEAD(__nge_jinusehead, nge_jpool_entry) nge_jinuse_listhead;
|
||||
struct mtx nge_mtx;
|
||||
};
|
||||
|
||||
/*
|
||||
* register space access macros
|
||||
*/
|
||||
#define CSR_WRITE_4(sc, reg, val) \
|
||||
bus_space_write_4(sc->nge_btag, sc->nge_bhandle, reg, val)
|
||||
|
||||
#define CSR_READ_4(sc, reg) \
|
||||
bus_space_read_4(sc->nge_btag, sc->nge_bhandle, reg)
|
||||
|
||||
#define NGE_TIMEOUT 1000
|
||||
#define ETHER_ALIGN 2
|
||||
#define NGE_RXLEN 1536
|
||||
#define NGE_MIN_FRAMELEN 60
|
||||
|
||||
/*
|
||||
* PCI low memory base and low I/O base register, and
|
||||
* other PCI registers.
|
||||
*/
|
||||
|
||||
#define NGE_PCI_VENDOR_ID 0x00
|
||||
#define NGE_PCI_DEVICE_ID 0x02
|
||||
#define NGE_PCI_COMMAND 0x04
|
||||
#define NGE_PCI_STATUS 0x06
|
||||
#define NGE_PCI_REVID 0x08
|
||||
#define NGE_PCI_CLASSCODE 0x09
|
||||
#define NGE_PCI_CACHELEN 0x0C
|
||||
#define NGE_PCI_LATENCY_TIMER 0x0D
|
||||
#define NGE_PCI_HEADER_TYPE 0x0E
|
||||
#define NGE_PCI_LOIO 0x10
|
||||
#define NGE_PCI_LOMEM 0x14
|
||||
#define NGE_PCI_BIOSROM 0x30
|
||||
#define NGE_PCI_INTLINE 0x3C
|
||||
#define NGE_PCI_INTPIN 0x3D
|
||||
#define NGE_PCI_MINGNT 0x3E
|
||||
#define NGE_PCI_MINLAT 0x0F
|
||||
#define NGE_PCI_RESETOPT 0x48
|
||||
#define NGE_PCI_EEPROM_DATA 0x4C
|
||||
|
||||
/* power management registers */
|
||||
#define NGE_PCI_CAPID 0x50 /* 8 bits */
|
||||
#define NGE_PCI_NEXTPTR 0x51 /* 8 bits */
|
||||
#define NGE_PCI_PWRMGMTCAP 0x52 /* 16 bits */
|
||||
#define NGE_PCI_PWRMGMTCTRL 0x54 /* 16 bits */
|
||||
|
||||
#define NGE_PSTATE_MASK 0x0003
|
||||
#define NGE_PSTATE_D0 0x0000
|
||||
#define NGE_PSTATE_D1 0x0001
|
||||
#define NGE_PSTATE_D2 0x0002
|
||||
#define NGE_PSTATE_D3 0x0003
|
||||
#define NGE_PME_EN 0x0010
|
||||
#define NGE_PME_STATUS 0x8000
|
||||
|
||||
#ifdef __alpha__
|
||||
#undef vtophys
|
||||
#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va)
|
||||
#endif
|
||||
@ -1634,6 +1634,10 @@ device miibus
|
||||
# DE101, DE200, DE201, DE202, DE203, DE204, DE205, DE422)
|
||||
# lnc: Lance/PCnet cards (Isolan, Novell NE2100, NE32-VL, AMD Am7990 and
|
||||
# Am79C960)
|
||||
# nge: Support for PCI gigabit ethernet adapters based on the National
|
||||
# Semiconductor DP83820 and DP83821 chipset. This includes the
|
||||
# SMC EZ Card 1000 (SMC9462TX), D-Link DGE-500T, Asante FriendlyNet
|
||||
# GigaNIX 1000TA and 1000TPC, and the Addtron AEG320T.
|
||||
# oltr: Olicom ISA token-ring adapters OC-3115, OC-3117, OC-3118 and OC-3133
|
||||
# (no hints needed).
|
||||
# Olicom PCI token-ring adapters OC-3136, OC-3137, OC-3139, OC-3140,
|
||||
@ -1803,6 +1807,7 @@ device de # DEC/Intel DC21x4x (``Tulip'')
|
||||
device vx # 3Com 3c590, 3c595 (``Vortex'')
|
||||
|
||||
# PCI Gigabit & FDDI NICs.
|
||||
device nge
|
||||
device sk
|
||||
device ti
|
||||
device wx
|
||||
|
||||
@ -9,8 +9,8 @@ _random= random
|
||||
SUBDIR= 3dfx accf_data accf_http agp aha amr an aue \
|
||||
cam ccd cd9660 coda cue dc de dgm digi ed fdesc fxp if_disc if_ef \
|
||||
if_ppp if_sl if_tap if_tun ip6fw ipfilter ipfw ispfw joy kue \
|
||||
libmchain linux lnc md mfs mii mlx msdos ncp netgraph nfs ntfs nullfs \
|
||||
nwfs pcn portal procfs ${_random} \
|
||||
libmchain linux lnc md mfs mii mlx msdos ncp netgraph nfs nge ntfs \
|
||||
nullfs nwfs pcn portal procfs ${_random} \
|
||||
rl rp sf sis sk sn sound sppp ste sym syscons sysvipc ti tl twe tx \
|
||||
udbp ugen uhid ukbd ulpt umapfs umass umodem ums union urio usb \
|
||||
uscanner \
|
||||
|
||||
@ -6,6 +6,6 @@ KMOD= miibus
|
||||
SRCS= mii.c mii_physubr.c ukphy.c ukphy_subr.c bus_if.h pci_if.h
|
||||
SRCS+= miibus_if.h device_if.h miibus_if.c e1000phy.c exphy.c nsphy.c
|
||||
SRCS+= mlphy.c tlphy.c rlphy.c amphy.c dcphy.c pnphy.c inphy.c
|
||||
SRCS+= brgphy.c xmphy.c pnaphy.c lxtphy.c qsphy.c acphy.c
|
||||
SRCS+= brgphy.c xmphy.c pnaphy.c lxtphy.c qsphy.c acphy.c nsgphy.c
|
||||
|
||||
.include <bsd.kmod.mk>
|
||||
|
||||
12
sys/modules/nge/Makefile
Normal file
12
sys/modules/nge/Makefile
Normal file
@ -0,0 +1,12 @@
|
||||
# $FreeBSD$
|
||||
|
||||
.PATH: ${.CURDIR}/../../dev/nge
|
||||
|
||||
KMOD= if_nge
|
||||
SRCS= if_nge.c opt_bdg.h vlan.h device_if.h bus_if.h pci_if.h
|
||||
CLEANFILES= vlan.h
|
||||
|
||||
vlan.h:
|
||||
touch vlan.h
|
||||
|
||||
.include <bsd.kmod.mk>
|
||||
@ -100,6 +100,7 @@ static struct _devname {
|
||||
{ DEVICE_TYPE_NETWORK, "kue", "Kawasaki LSI USB ethernet adapter" },
|
||||
{ DEVICE_TYPE_NETWORK, "le", "DEC EtherWorks 2 or 3 ethernet card" },
|
||||
{ DEVICE_TYPE_NETWORK, "lnc", "Lance/PCnet (Isolan/Novell NE2100/NE32-VL) ethernet" },
|
||||
{ DEVICE_TYPE_NETWORK, "nge", "NatSemi PCI gigabit ethernet card" },
|
||||
{ DEVICE_TYPE_NETWORK, "pcn", "AMD Am79c79x PCI ethernet card" },
|
||||
{ DEVICE_TYPE_NETWORK, "rl", "RealTek 8129/8139 PCI ethernet card" },
|
||||
{ DEVICE_TYPE_NETWORK, "sf", "Adaptec AIC-6915 PCI ethernet card" },
|
||||
|
||||
@ -100,6 +100,7 @@ static struct _devname {
|
||||
{ DEVICE_TYPE_NETWORK, "kue", "Kawasaki LSI USB ethernet adapter" },
|
||||
{ DEVICE_TYPE_NETWORK, "le", "DEC EtherWorks 2 or 3 ethernet card" },
|
||||
{ DEVICE_TYPE_NETWORK, "lnc", "Lance/PCnet (Isolan/Novell NE2100/NE32-VL) ethernet" },
|
||||
{ DEVICE_TYPE_NETWORK, "nge", "NatSemi PCI gigabit ethernet card" },
|
||||
{ DEVICE_TYPE_NETWORK, "pcn", "AMD Am79c79x PCI ethernet card" },
|
||||
{ DEVICE_TYPE_NETWORK, "rl", "RealTek 8129/8139 PCI ethernet card" },
|
||||
{ DEVICE_TYPE_NETWORK, "sf", "Adaptec AIC-6915 PCI ethernet card" },
|
||||
|
||||
Loading…
Reference in New Issue
Block a user