can't do a timeout bigger than 15 seconds. The code wasn't checking for
this and because bitmasking was involved the requested timeout was
basically adjusted modulo-16. That led to things like a 128 second
timeout actually being a 9 second timeout, which accidentally worked fine
until watchdogd was changed to only pet the dog once every 10 seconds.
o Move similar block/networking methods to common file
o Follow r275640 and correct MMIO registers width
o Pass value to MMIO platform_note method.
Sponsored by: DARPA, AFRL
far away from a ldr psuedo instruction. With this clang will place the
literal value here where it's close enough to be loaded.
MFC after: 1 week
Sponsored by: ABT Systems Ltd
If this feels like deja vu... the last time this was fixed in this file
only ARM_MMU_V6 was fixed, this time it's ARM_ARCH_V6 (and this time I
searched for other occurrances of pj4b in here).
the first cacheline if the buffer start address is not on a cacheline
boundary. Normally a buffer which is not cacheline-aligned is bounced,
but a special rule applies for mbufs, which are always misaligned due to
the header. We know the cpu will not write to the header while dma is in
progress (so we've been told anyway), but it may have written to the
header shortly before starting a read, so we need to flush that write out
to memory before invalidating the whole buffer.
In collaboration with Mical Meloun and Svata Kraus.
It is automatically set when -fPIC is passed to the compiler.
Reviewed by: dim, kib
Sponsored by: The FreeBSD Foundation
Differential Revision: https://reviews.freebsd.org/D1179
For OMAP4, the old values for 1MHz gave a bus frequency of about 890KHz.
The new numbers hit 1MHz exactly.
For AM335x the prescaler values are adjusted to give a 24MHz clock for
all 3 standard speeds, as the manual recommends (as near as we can tell,
there are errors and typos apparent in the document). Also, 1MHz speed
is added, and has been tested successfully on a BeagleboneWhite board.
PR: 195009
The current support for controlling i2c bus speed is an inconsistant mess.
There are 4 symbolic speed values defined, UNKNOWN, SLOW, FAST, FASTEST.
It seems to be universally assumed that SLOW means the standard 100KHz
rate from the original spec. Nothing ever calls iicbus_reset() with a
speed of FAST, although some drivers would treat it as the 400KHz standard
speed. Mostly iicbus_reset() is called with the speed set to UNKNOWN or
FASTEST, and there's really no telling what any individual driver will do
with those.
The speed of an i2c bus is limited by the speed of the slowest device on
the bus. This means that generally the bus speed needs to be configured
based on the board/system and the components within it. Historically for
i2c we've configured with device hints. Newer systems use FDT data and it
documents a clock-frequency property for i2c busses. Hobbyists and
developers are likely to want on the fly changes. These changes provide
all 3 methods, but do not require any existing drivers to change to use
the new facilities.
This adds an iicbus method, iicbus_get_frequency(dev, speed) that gets the
frequency for the requested symbolic speed. If the symbolic speed is SLOW
or if there is no speed configured for the bus, the returned value is
100KHz, always. Otherwise, if bus speed is configured by hints, fdt,
tunable, or sysctl, that speed is returned. It also adds a helper
function, iicbus_init_frequency() that any bus driver subclassed from
iicbus can initialize the frequency from some other source of info.
Initial driver implementations are provided for Freescale and TI.
Differential Revision: https://reviews.freebsd.org/D1174
PR: 195009
We used to invalidate the cache for PREREAD alone, or writeback+invalidate
for PREREAD with PREWRITE, then treat POSTREAD as a no-op. Prefetching on
modern systems can lead to parts of a DMA buffer getting pulled into the
caches while DMA is in progress (due to access of "nearby" data), so it's
mandatory to invalidate during the POSTREAD sync even if a PREREAD
invalidate also happened.
In the PREREAD case the invalidate is done to ensure that there are no
dirty cache lines that might get automatically evicted during the DMA,
corrupting the buffer. In a PREREAD+PREWRITE case the writeback which is
required for PREWRITE handling is suffficient to avoid corruption caused
by eviction and no invalidate need be done until POSTREAD time.
Submitted by: Michal Meloun <meloun@miracle.cz>
The PREWRITE handling does a writeback of any dirty cachelines, so there's
no danger of an eviction during the DMA corrupting the buffer. There will
be an invalidate done during POSTREAD, so doing it before the read too is
wasted time.
for cache maintenance operations, but ensure that all prior writes have
reached memory when doing a PREWRITE sync.
Submitted by: Michal Meloun <meloun@miracle.cz>
I originally overlooked a couple flag bits defined in the fdt binding docs.
One flag suppresses the pad configuration (pullup/pulldown/etc). The other
one requires that the SION (set input on) flag be set in the mux register.
Also, it appears from the data involved that if the input register
address in the config tuple is zero, there is no input configuration. The
old code was writing to register zero, which contains a collection of misc
control bits (having nothing to do with input configuration) that probably
shouldn't get overwritten arbitrarily. The bindings doc doesn't explictly
mention this.
that expose new bugs with HS mode.
When the old code could not do the proper card detection it would boot with
lower defaults (and no HS mode) and this makes some HS cards boots.
Now, with the card always identified as HS capable, the sdhci controller
tries to run the card at HS speeds and makes the boot always fail.
Disable the HS mode for now (which still can be enabled with the tunable)
until it is properly fixed.
MFC with: r273264
Requested by: many
have chosen different (and more traditional) stateless/statuful
NAT64 as translation mechanism. Last non-trivial commits to both
faith(4) and faithd(8) happened more than 12 years ago, so I assume
it is time to drop RFC3142 in FreeBSD.
No objections from: net@
It turns out an alignment of zero can lead to an endless loop in the
vm reservations code, so specifically disallow that. The manpage says
hardware which can do dma at any address should use a value of one, which
hints at the forbiddeness of zero without exactly saying it. Several
other conditions which could lead to insanity in working with the tag are
also checked now.
Every existing call to bus_dma_tag_create() (about 680 of them) was
eyeballed for violations of these things, and two alignment=0 glitches
were fixed. It's possible something was missed, but overall this
shouldn't lead to any arm users suddenly experiencing failures.
unit 0.
It seems that this 'simplification' was copied to all GPIO drivers in tree.
This fix a bug where a GPIO controller could fail to attach its children
(gpioc and gpiobus) if another GPIO driver attach first.
and casuword(9), but do not mix value read and indication of fault.
I know (or remember) enough assembly to handle x86 and powerpc. For
arm, mips and sparc64, implement fueword() and casueword() as wrappers
around fuword() and casuword(), which means that the functions cannot
distinguish between -1 and fault.
On architectures where fueword() and casueword() are native, implement
fuword() and casuword() using fueword() and casuword(), to reduce
assembly code duplication.
Sponsored by: The FreeBSD Foundation
Tested by: pho
MFC after: 2 weeks (ia64 needs treating)
Multipass device attachment was tested on many arm platforms by users and
only success was reported on the arm@ mailing list. This is just the
long-delayed followup of making it the default.
Multipass attachment is necessary when using vendor-supplied FDT data,
because our devices may need to be attached in a different order than they
are described in the FDT data.
used for kernel devices it is used by i2c(8).
This fix the 'error: Device not configured' when i2c(8) tries to reset the
controller, as an example:
# i2c -r
Resetting I2C controller on /dev/iic0: error: Device not configured
For now use conservative settings for default i2c speeds.
MFC after: 1 week
For an unkown reason (at moment), sometimes if_cpsw cannot read from PHY
and fails to attach calling cpsw_detach() which end up in a panic.
Fix it by doing the proper check before detach the miibus and also fix the
leak of few variables.
And to actually make it work, ether_ifattach() has to be moved to the end
of cpsw_attach() to avoid a race where calling ether_ifdetach() before
domain_init() (which will only run later on) would make it crash at
INP_INFO_RLOCK() on in_pcbpurgeif0().
Tested on: BBB (am335x)
MFC after: 1 week
the map count and without being able to keep track of the current map
allocation, bus_dma_tag_destroy() will fail to proceed and will return
EBUSY even after all the maps have been correctly destroyed with
bus_dmamap_destroy().
Found while testing the detach method of a NIC.
Tested on: BBB (am335x)
Reviewed by: cognet, ian
MFC after: 1 week
workaround for an imx6 chip erratum. Linux works around the bug with
changes in fdt data that we can't currently handle, so to enable running
with standard vendor-supplied fdt data, this watches for an attempt to map
the gpio1_6 interrupt and remaps it back to the standard ethernet interrupt.
This can be undone when the intrng project is completed and our gpio drivers
can also be interrupt controllers.
for, or that are required to run the chip (such as busses). Turn off all
the devices we don't yet have drivers for.
Some day we will have a fully functional imx6 clock driver so that we can
manage clocks based on fdt data. This will have to do until then.
- Wrong integer type was specified.
- Wrong or missing "access" specifier. The "access" specifier
sometimes included the SYSCTL type, which it should not, except for
procedural SYSCTL nodes.
- Logical OR where binary OR was expected.
- Properly assert the "access" argument passed to all SYSCTL macros,
using the CTASSERT macro. This applies to both static- and dynamically
created SYSCTLs.
- Properly assert the the data type for both static and dynamic
SYSCTLs. In the case of static SYSCTLs we only assert that the data
pointed to by the SYSCTL data pointer has the correct size, hence
there is no easy way to assert types in the C language outside a
C-function.
- Rewrote some code which doesn't pass a constant "access" specifier
when creating dynamic SYSCTL nodes, which is now a requirement.
- Updated "EXAMPLES" section in SYSCTL manual page.
MFC after: 3 days
Sponsored by: Mellanox Technologies
timecounter resolution is available, so ask for a 1 GHz frequency. It
won't actually get one that fast, but that'll get the fastest available
clock and use a divisor of 1 (probably 132 or 66mhz on current hardware).
EWOULDBLOCK.
Do not print any message at errors. The errors are properly sent to upper
layers which should be able to deal with it, including printing the errors
when they need to.
The error message was quite annoying while scanning the i2c bus.
MFC after: 1 week
This fix a race where the threads waiting for the bus would wake up early
and still see bus as busy.
While here, give a better description to wmesg for the two use cases we
have (bus and io waiting).
MFC after: 1 week
will now find the virtual to physical mapping for libkvm to use at
runtime. This makes PHYSADDR redundant, however keep it around to give
everyone a chance to update their libkvm.
MFC after: 1 week
physaddr. This should allow for a kernel where PHYSADDR and KERNPHYSADDR
are both undefined.
For now libkvm will use the old method of reading physaddr and kernaddr
to allow it to work with old kernels. This could be removed in the future
when enough time has passed.
Differential Revision: https://reviews.freebsd.org/D939
MFC after: 1 week
bus_new_pass() handler so it doesn't happen until BUS_PASS_CPU. This allows
the anatop driver to outbid the generic simplebus driver (which the FDT
data describes as compatible).
Some day when we handle power regulators, this driver may actually
become a functional simplebus and attach the regulators as children, as
described in the FDT data.
lose the contents of consecutive writes (that happens within two SD card
clock cycles).
This fixes the causes of instability during the SD card detection and
identification on Raspberry Pi (which happens at 400 kHz and so was much
more vulnerable to this issue).
Remove the previous workaround which clearly can't provide the same effect.
MFC after: 1 week
Relnotes: yes
to be present. Thsi creates a new per-SoC driver that handles probe and
setting/getting the gpio flags.
Differential Revision: https://reviews.freebsd.org/D943
Reviewed by: loos, rpaulo
MFC after: 1 week
The TI watchdog timer is present on BeagleBone's. Since 2014, U-Boot
has been booting the BeagleBone with the watchdog enabled. We need to
disable it on boot to avoid a spurious reset.
The timer isn't exactly precise, but it will do as a watchdog. This
is also a reflection of the watchdog(9) API.
In the future, we could handle interrupts, but the watchdog(9) API
needs to be a bit smarter before that can happen.
Differential Revision: https://reviews.freebsd.org/D965
Reviewed by: andrew
MFC after: 1 week
Relnotes: yes
in userland rename in-kernel getenv()/setenv() to kern_setenv()/kern_getenv().
This fixes a namespace collision with libc symbols.
Submitted by: kmacy
Tested by: make universe
few changes to drivers, no kernel config was added. As the SoCs are quite
old and the code is unmaintained start the process of removing support by
deleting the header file and code that depends on it along with the macro
SOC_OMAP3. Other Ti SoCs shouldn't be affected, other than for us to have
less code to maintain.
Differential Revision: https://reviews.freebsd.org/D936
Reviewed by: rpaulo, loos
registers and use it in the ARMv7 CPU functions.
The sysreg.h file has been checked by hand, however it may contain errors
with the comments on when a register was first introduced. The ARMv7 cpu
functions have been checked by compiling both the previous and this version
and comparing the md5 of the object files.
Submitted by: Svatopluk Kraus <onwahe at gmail.com>
Submitted by: Michal Meloun <meloun at miracle.cz>
Reviewed by: ian, rpaulo
Differential Revision: https://reviews.freebsd.org/D795
When the FreeBSD kernel is loaded from Xen the symtab and strtab are
not loaded the same way as the native boot loader. This patch adds
three new global variables to ddb that can be used to specify the
exact position and size of those tables, so they can be directly used
as parameters to db_add_symbol_table. A new helper is introduced, so callers
that used to set ksym_start and ksym_end can use this helper to set the new
variables.
It also adds support for loading them from the Xen PVH port, that was
previously missing those tables.
Sponsored by: Citrix Systems R&D
Reviewed by: kib
ddb/db_main.c:
- Add three new global variables: ksymtab, kstrtab, ksymtab_size that
can be used to specify the position and size of the symtab and
strtab.
- Use those new variables in db_init in order to call db_add_symbol_table.
- Move the logic in db_init to db_fetch_symtab in order to set ksymtab,
kstrtab, ksymtab_size from ksym_start and ksym_end.
ddb/ddb.h:
- Add prototype for db_fetch_ksymtab.
- Declate the extern variables ksymtab, kstrtab and ksymtab_size.
x86/xen/pv.c:
- Add support for finding the symtab and strtab when booted as a Xen
PVH guest. Since Xen loads the symtab and strtab as NetBSD expects
to find them we have to adapt and use the same method.
amd64/amd64/machdep.c:
arm/arm/machdep.c:
i386/i386/machdep.c:
mips/mips/machdep.c:
pc98/pc98/machdep.c:
powerpc/aim/machdep.c:
powerpc/booke/machdep.c:
sparc64/sparc64/machdep.c:
- Use the newly introduced db_fetch_ksymtab in order to set ksymtab,
kstrtab and ksymtab_size.
We've always considered the mpcore timers to be a single monolithic device
and we defined our own fdt binding for it with our own compat string. The
published bindings treat the timers as two separate devices, a global
timer and a "timer-watchdog" device for the per-cpu private timers. Thus
our binding has two tuples in the regs property, one set of registers for
the global timer and one for the private timers. The published bindings
have two separate devices, each with a single set of registers. (Note that
we don't use the optional watchdog feature of the hardware.)
These changes add the compat strings for the published bindings. If our
own compat string appears, we expect to get two sets of memory resources.
For the published bindings, there's only one set of memory resources, and
only the private timers have an associated interrupt.
The other major change is that there can no longer be a single global var
for the softc pointer because now there may be multiple devices at
runtime. Since the global timer is used only as a timecounter and the
private timers only as eventtimers, and there will only be one of each,
those are now the pointers which are global, and the priv fields of those
structures backlink to the device softc.
In the fdt data we've written for ourselves, the interrupt properties
for GIC interrupts have just been a bare interrupt number. In standard
data that conforms to the published bindings, GIC interrupt properties
contain 3-tuples that describe the interrupt as shared vs private, the
interrupt number within the shared/private address space, and configuration
info such as level vs edge triggered.
The new gic_decode_fdt() function parses both types of data, based on the
#interrupt-cells property. Previously, each platform implemented a decode
routine and put a pointer to it into fdt_pic_table. Now they can just
list this function in their table instead if they use arm/gic.c.
The code had references to both intr_offset and intr_parent variable names
as referring to the parent interrupt node. The intr_parent variable
wasn't actually defined anywhere, but the only references to it were as
an argument to a macro that didn't use that argument in expansion, so
the undefined variable accidentally didn't cause an error.
The intr_parent name makes more sense in context, so change all occurrances
of intr_offset to intr_parent.
nexus_alloc_resource() and don't set a bushandle.
nexus_activate_resource() will set a proper bushandle.
- Implement a proper nexus_release_resource().
- Fix ixppcib_activate_resource() to call rman_activate_resource()
before creating a mapping for the resource.
Tested by: jmg
va == pa map.
I'm not sure the code would work if we are not running from the identity
map as the ARM core may attempt to read the next instruction from an
invalid memory location.
boards.
This is just intended to split the common config entries out, further
cleanup is expected.
Reviewed by: ian@, rpaulo@ (earlier version)
Differential Revision: https://reviews.freebsd.org/D731
o Unmagic 'configuration done' bit
o Move probe() to place before attach() for better navigation
o Use bus_read_n instead of bus_space_read_n functions
Pointed out by: andrew
Sponsored by: DARPA, AFRL
be usable as the default timer in place of the physical timer.
We are guaranteed to have access to the virtual timer, but when running
under a hypervisor may not have access to the physical.
Differential Revision: https://reviews.freebsd.org/D588
few "general purpose registers" whose values control chip behavior in ways
that have nothing to do with IO pin mux control. Define a simple API that
other soc-specific code can use to read and write the registers, and provide
the imx51 implementation of them.
- miibus fixes as suggested by Yonghyeon Pyun.
- enable VLAN MTU support.
- fix a few WITNESS complaints in cgem_attach().
- have cgem_attach() properly init the ifnet struct before calling
mii_attach() to fix panic when using e1000phy.
- fix ethernet address changing.
- fix transmit queue overflow handling.
- tweak receive queue handling to reduce receive overflows.
- bring out MAC statistic counters to sysctls.
- add e1000phy to config file.
- implement receive hang work-around described in reference guide.
- change device name from if_cgem to cgem to be consistent with other
interfaces.
Submitted by: Thomas Skibo <ThomasSkibo@sbcglobal.net>
Reviewed by: wkoszek, Yonghyeon PYUN <pyunyh@gmail.com>
. interrupt storm detected on "intr70:"; throttling interrupt source;
. Added access serialization on iicbus_transfer(), previously there was
no such protection and a new transfer could easily confuse the
controller;
. Add error checkings (i.e. stop the transfer when a error is detected
and do _not_ overwrite the previous error);
. On command done interrupt do not assume that the transfer was finished
sucessfully as we will receive the command done interrupt even after
errors;
. Simplify the FIFO handling;
. Reset the FIFO between the transfers as the FIFO may contain data from
the last (failed) transfer;
. Fix the iicbus speed for AM335x, which in turn will make better use of
the I2C noise filter (set to one internal clock cycle);
. Move the read and write handler to ithread instead of notifying the
requesting thread with wakeup(9);
. Fix the comments based on OMAP4 TRM.
The above changes allows me to read the EDID from my HDMI monitor on BBB
with gonzo's patches to support TDA19988 (which does 128 bytes reads) and
repeatedly scan the iicbus (with a modified i2c(8)) without lock up the bus.
Phabric: D465
header (Elf_Ehdr) to determine if a particular interpretor wants to
accept it or not. Use this mechanism to filter EABI arm on OABI arm
kernels, and vice versa. This method could also be used to implement
OABI on EABI arm kernels, if desired, or to allow a single mips kernel
to run o32, n32 and n64 binaries.
Differential Revision: https://reviews.freebsd.org/D609
soc-wide info lives. It was under dev.imx6_anatop.0.
What does anatop mean anyway? Nobody seems to know, so it's probably
not where somebody will think to look for imx6 hardware info.
configure the mux and config registers for PIO devices based on what
we find in the FDT. I developed it per the spec that had been
committed to Linux in the January 2014 time frame and haven't
updated. In short, bundles of pins are activated in specific ways for
specific configurations, and we implement all of that.
What's not included is a MI device infrastructure, any dynamic
run-time changing of these pins, etc. Also not included are hooks into
all the drivers to enable the latter (static at boot no driver changes
are needed). These larger questions will need to be answered once we
have more drivers like this for more platforms, or somebody has a heck
of a lot of time to research a bunch of platforms, the Linux solution
(which is good, but has its warts), etc.
work. This gets my AT91SAM9260-based boards almost booting with
current in multi pass. The MCI driver is broken, but it is equally
broken before multi-pass.
By Richard Earnshaw at ARM
>
>GCC has for a number of years provides a set of pre-defined macros for
>use with determining the ISA and features of the target during
>pre-processing. However, the design was always somewhat cumbersome in
>that each new architecture revision created a new define and then
>removed the previous one. This meant that it was necessary to keep
>updating the support code simply to recognise a new architecture being
>added.
>
>The ACLE specification (ARM C Language Extentions)
>(http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.set.swdev/index.html)
>provides a much more suitable interface and GCC has supported this
>since gcc-4.8.
>
>This patch makes use of the ACLE pre-defines to map to the internal
>feature definitions. To support older versions of GCC a compatibility
>header is provided that maps the traditional pre-defines onto the new
>ACLE ones.
Stop using __FreeBSD_ARCH_armv6__ and switch to __ARM_ARCH >= 6 in the
couple of places in tree. clang already implements ACLE. Add a define
that says we implement version 1.1, even though the implementation
isn't quite complete.
mapping size (currently unused). The flags includes the fault access
bits, wired flag as PMAP_ENTER_WIRED, and a new flag
PMAP_ENTER_NOSLEEP to indicate that pmap should not sleep.
For powerpc aim both 32 and 64 bit, fix implementation to ensure that
the requested mapping is created when PMAP_ENTER_NOSLEEP is not
specified, in particular, wait for the available memory required to
proceed.
In collaboration with: alc
Tested by: nwhitehorn (ppc aim32 and booke)
Sponsored by: The FreeBSD Foundation and EMC / Isilon Storage Division
MFC after: 2 weeks
device attachment on arm platforms. If this is defined, nexus attaches
early in BUS_PASS_BUS, and other busses and devices attach later, in the
pass number they are set up for. Without it defined, nexus attaches in
BUS_PASS_DEFAULT and thus so does everything else, which is status quo.
Arm platforms which use FDT data to enumerate devices have been relying
on devices being attached in the exact order they're listed in the dts
source file. That's one of things currently preventing us from using
vendor-supplied fdt data (because then we don't control the order of the
devices in the data). Multi-pass attachment can go a long way towards
solving that problem by ensuring things like clock and interrupt drivers
are attached before the more mundane devices that need them.
The long-term goal is to have all arm fdt-based platforms using multipass.
This option is a bridge to that, letting us enable it selectively as
platforms are converted and tested (the alternative being to just throw
a big switch and try to fight fires as they're reported).
The MD allocators were very common, however there were some minor
differencies. These differencies were all consolidated in the MI allocator,
under ifdefs. The defines from machine/vmparam.h turn on features required
for a particular machine. For details look in the comment in sys/sf_buf.h.
As result no MD code left in sys/*/*/vm_machdep.c. Some arches still have
machine/sf_buf.h, which is usually quite small.
Tested by: glebius (i386), tuexen (arm32), kevlo (arm32)
Reviewed by: kib
Sponsored by: Netflix
Sponsored by: Nginx, Inc.
We continue to use pmap_enter() for that. For unwiring virtual pages, we
now use pmap_unwire(), which unwires a range of virtual addresses instead
of a single virtual page.
Sponsored by: EMC / Isilon Storage Division
don't need any #ifdef stuff to use atomic_load/store_64() elsewhere in
the kernel. For armv4 the atomics are trivial to implement for kernel
code (just disable interrupts), less so for user mode, so this only has
the kernel mode implementations for now.
value shared across multiple cores is with atomic_load_64() and
atomic_store_64(), because the normal 64-bit load/store instructions
are not atomic on 32-bit arm. Luckily the ldrexd/strexd instructions
that are atomic are fairly cheap on armv6. Because it's fairly simple
to do, this implements all the ops for 64-bit, not just load/store.
Reviewed by: andrew, cognet
We have functions nested within functions, and places where we start a
function then never end it, we just jump to the middle of something else.
We tried to express this with nested ENTRY()/END() macros (which result
in .fnstart and .fnend directives), but it turns out there's no way to
express that nesting in ARM EHABI unwind info, and newer tools treat
multiple .fnstart directives without an intervening .fnend as an error.
These changes introduce two new macros, EENTRY() and EEND(). EENTRY()
creates a global label you can call/jump to just like ENTRY(), but it
doesn't emit a .fnstart. EEND() is a no-op that just documents the
conceptual endpoint that matches up with the same-named EENTRY().
This is based on patches submitted by Stepan Dyatkovskiy, but I made some
changes and added the EEND() stuff, so blame any problems on me.
Submitted by: Stepan Dyatkovskiy <stpworld@narod.ru>
(4 in operation), 4GB ram (3.5 usable) ARM machine.
Support covers device drivers for:
- Serial Peripheral Interface (SPI)
- Chrome Embedded Controller (EC) - SPI-based version
- XHCI and USB 3.0 dual-role device PHY
Also:
- Add support for Exynos5420 in Pad module
- Move power-related functions to separate driver --
Power Management Unit (PMU)
- Enable XHCI for Chromebook1
Special thanks to grehan@ for hardware, and to
hselasky@ for r269139.
moved from the stack into the tag structure. In retrospect that was a bad
idea, because nothing protects that array from concurrent access by
multiple threads.
This change moves the array to the map structure (actually it's allocated
following the structure, but all in a single malloc() call).
This also establishes a "sane" limit of 4096 segments per map. This is
mostly to prevent trying to allocate all of memory if someone accidentally
uses a tag with nsegments set to BUS_SPACE_UNRESTRICTED. If there's ever
a genuine need for more than 4096, don't hesitate to increase this (or
maybe make it tunable).
Reviewed by: cognet
