FIFO or the in-RAM descriptors it will switch to RX_IDLE from where it
is not restarted.
We used to deal with RX_IDLE by doing a total reinit but this lost
our link and caused a potential 30sec autonegotiation against
switches. This was changed to a less heavyhanded approach, but this
failed to restart the receiver it it were in the RX_IDLE state.
This change adds the RX_IDLE and the RX_FIFO_OFLOW conditions as
triggers for interrupts and receive side processing, and restarts
the receiver when it is RX_IDLE.
Remove the #ifdef notyet'ed nge_rxeoc() function.
Sponsored by: Cybercity Internet, Denmark.
MFC after: 7 days
of the rxeoc handler for now. The rxeoc handler will reset the link,
and the NatSemi chip's RX FIFO will overflow on a 32-bit bus once you
start hitting it with 500Mbps or more of traffic.
Also increase the size of the RX ring to 128 descriptors (was 64).
converting from the old external mbuf buffer code to the new (with the
MEXTADD() macro). Also free free list memory correctly in
foo_free_jumbo_mem() routines: grab the head of the list, then
remove it, _then_ free() it.
This fixes the memory corruption problem I've been chasing in the level 1
driver.
use of the extsts field in DMA descriptors. We need this to tell the chip
to calculate TCP/IP checksums in hardware on a per-packet basis.
- Fix the unions in DMA descriptor structures. Breakage on alpha led
me to realize I'd done it wrong the first time.
be unions with enough padding to make sure they always end up being
a multiple of 8 bytes in size, since the 83820/83821 chips require
descriptors to be aligned on 64-bit boundaries. I happened to get it
right for the 32-bit descriptor/x86 case, but botched everything else.
Things should work properle on 32-bit/64-bit platforms now.
Note that the 64-bit descriptor format isn't being used currently.
and DP83821 gigabit ethernet MAC chips and the NatSemi DP83861 10/100/1000
copper PHY. There are a whole bunch of very low cost cards available with
this chipset selling for $150USD or less. This includes the SMC9462TX,
D-Link DGE-500T, Asante GigaNIX 1000TA and 1000TPC, and a couple cards
from Addtron.
This chip supports TCP/IP checksum offload, VLAN tagging/insertion.
2048-bit multicast filter, jumbograms and has 8K TX and 32K RX FIFOs.
I have not done serious performance testing with this driver. I know
it works, and I want it under CVS control so I can keep tabs on it.
Note that there's no serious mutex stuff in here yet either: I need
to talk more with jhb to figure out the right way to do this. That
said, I don't think there will be any problems.
This driver should also work on the alpha. It's not turned on in
GENERIC.
