As a prerequisite for multiple queues, the guest must have MSIX enabled.
Unfortunately, to work around device passthrough bugs, FreeBSD disables
MSIX when running as a VMWare guest due to the hw.pci.honor_msi_blacklist
tunable; this tunable must be disabled for multiple queues.
Also included is various minor changes from the projects/vmxnet branch.
MFC after: 1 month
don't do it also in ia64_handle_intr(). With ia64_handle_intr()
not saving and setting td_intr_frame, make sure to do it for
timer interrupts in ia64_ih_hardclock().
The armv7 architecture uses a unified TLB model for maintenence ops even
if separate instruction and data TLBs are implemented in hardware. That
means that there's no distinction between the 'I' and 'D' flavors of flush,
they all use the same 'ID' implementation. On the other hand, there is a
difference between SMP and UP on armv7, but not on arm11, so use the armv7
routines for cortex-a processors.
don't do it also in ia64_handle_intr(). With ia64_handle_intr()
not saving and setting td_intr_frame, make sure to do it for
clock interrupts in ia64_ih_clock().
helps when bits and pieces of GENERIC from i386 or amd64 are cut and
pasted into other architecture's config files (which in the case of
ARM had gotten rather akimbo).
are only used on armv6 when the vfp unit is detected. They will also be
available for the upcoming armv6hf platform, however while not used by
default there will need to be defined for any software that calls them
directly.
proprietary binary format.
* Add support for a diagnostic information error cause.
The code is sysctlable and the default is 0, which
means it is not sent.
This is joint work with rrs@.
MFC after: 1 week
further refinement is required as some device drivers intended to be
portable over FreeBSD versions rely on __FreeBSD_version to decide whether
to include capability.h.
MFC after: 3 weeks
draft POSIX.1e capability.h used on some systems (e.g., Linux). On
FreeBSD, leave a wrapper header so that current code continues to compile.
We will eventually want to deprecate the old header as the presence of a
capability.h may be confusing some configure scripts.
Suggested by: David Drysdale <drysdale at google.com>
Discussed on: cl-capsicum-discuss
MFC after: 3 weeks
chips have more.
So for now, let's allow more. We should teach the apb code to just
reject interrupts that lie outside what the chip can do at runtime.
later. If the interrupts are ACKed even if they're not masked, we get
the interrupts again later. Grr.
* The AR724x and later chips want the interrupt bits cleared by writing the
relevant bit to it, NOT by writing all but the current interrupt to it.
Tested:
* AR9344, DB120 reference board
TODO:
* Test ar724x and later chips to ensure no regressions have occured.
I'm starting with the easy cases. The leftovers need to be looked at a
bit more closely.
Note that this change _does_ modify the code of the old tests. This is
required in order to allow the code to locate the data files in the
source directory instead of the current directory, because Kyua
automatically changes the latter to a temporary directory.
Also note that at least one test is known to be broken here. Actually,
the test is not really broken: it's marked as a TODO but unfortunately
Kyua's TAP parser currently does not understand that. Will have to be
fixed separately.
This change was originally going to only migrate the usr.sbin tests but, as
it turns out, the usr.sbin/sa/ tests require files from usr.bin/lastcomm/
so it's better to just also migrate the latter at the same time. The other
usr.bin tests will be moved separately.
To make these tests work within the test suite, some of them have required
changes to prevent modifying the source directory and instead just rely on
the current directory for file manipulation.
'eeprommac'.
The existing driver would just make arge units past 0 take the primary
MAC and increment it by the unit number, without correct address wrapping.
That has to be fixed at a later date.
Tested:
* Atheros DB120 reference obard
my tests, it is faster ~20%, even on an old IXP425 533MHz it is ~45%
faster... This is partly due to loop unrolling, so the code size does
significantly increase... I do plan on committing a version that
rolls up the loops again for smaller code size for embedded systems
where size is more important than absolute performance (it'll save ~6k
code)...
The kernel implementation is now shared w/ userland's libcrypt and
libmd...
We drop support for sha256 from sha2.c, so now sha2.c only contains
sha384 and sha512...
Reviewed by: secteam@
change... This eliminates a cast, and also forces td_retval
(often 2 32-bit registers) to be aligned so that off_t's can be
stored there on arches with strict alignment requirements like
armeb (AVILA)... On i386, this doesn't change alignment, and on
amd64 it doesn't either, as register_t is already 64bits...
This will also prevent future breakage due to people adding additional
fields to the struct...
This gets AVILA booting a bit farther...
Reviewed by: bde
attributed if an ExtINT arrives during interrupt injection.
Also, fix a spurious interrupt if the PIC tries to raise an interrupt
before the outstanding one is accepted.
Finally, improve the PIC interrupt latency when another interrupt is
raised immediately after the outstanding one is accepted by creating a
vmexit rather than waiting for one to occur by happenstance.
Approved by: neel (co-mentor)
When killing a %job started without job control, kill all processes in it.
As with process groups and zombies, if any process in the job can be killed
or has already terminated, the command is successful.
This also fixes occasional failures of the builtins/kill1.0 test.
