Jung-uk Kim 0e78005e5c Work around an emulator problem where virtual CPU advertises TSC is P-state ... invariant and APERF/MPERF MSRs exist but these MSRs never tick. When we calculate effective frequency from cpu_est_clockrate(), it caused panic of division-by-zero. Now we test whether these MSRs actually increase to avoid such foot-shooting. Reported by: dim Tested by: dim		2011-04-14 17:50:26 +00:00
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acpica	Remove unneeded includes of <sys/linker_set.h>. Other headers that use	2011-01-11 13:59:06 +00:00
bios
cpufreq	Use atomic load & store for TSC frequency. It may be overkill for amd64 but	2011-04-07 23:28:28 +00:00
include	Copy powerpc/include/_inttypes.h to x86 and replace i386/amd64/pc98	2011-01-08 18:09:48 +00:00
isa	Add some tunable descriptions about x86 timers.	2011-04-14 00:07:08 +00:00
pci	Each processor socket in a QPI system has a special PCI bus for the	2010-09-07 13:50:02 +00:00
x86	Work around an emulator problem where virtual CPU advertises TSC is P-state	2011-04-14 17:50:26 +00:00