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134c58d3c0
the built-in 1000baseX interface in the Level 1 LXT1001 chip. The Level 1 PHY comes up with the isolate bit in the control register set by default, but it also has the autonegotiate bit set. When you tell the xmphy driver to select IFM_AUTO mode, it sees that the autoneg bit is already on, and thus doesn't bother updating the control register. However this means that the isolate bit is never turned off (unless you manually select 1000baseSX full or half duplex mode, which does result in the control register being modified and the ISO bit being turned off). This subtle and unusual behavioral difference stopped me from being able to receive packets on the SMC9462TX card for several days, since isolating the PHY disconnects it from the MAC's data interface. The fix is to omit the 'is the autoneg big set?' test, since it doesn't really provide much of an optimization anyway. This commit also updates the xmphy driver to support the Jato/Level 1 internal PHY. (I'm not sure how Jato Technologies is related to Level 1: all I know is the OUI from the PHY ID registers maps to Jato in the OUI database.) This will be used once I add the if_lge driver to support the LXT10010 chip. |
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| .. | ||
| acphy.c | ||
| acphyreg.h | ||
| amphy.c | ||
| amphyreg.h | ||
| brgphy.c | ||
| brgphyreg.h | ||
| dcphy.c | ||
| devlist2h.awk | ||
| e1000phy.c | ||
| e1000phyreg.h | ||
| exphy.c | ||
| inphy.c | ||
| inphyreg.h | ||
| lxtphy.c | ||
| lxtphyreg.h | ||
| Makefile.miidevs | ||
| mii_physubr.c | ||
| mii.c | ||
| mii.h | ||
| miibus_if.m | ||
| miidevs | ||
| miidevs.h | ||
| miivar.h | ||
| mlphy.c | ||
| nsgphy.c | ||
| nsgphyreg.h | ||
| nsphy.c | ||
| nsphyreg.h | ||
| pnaphy.c | ||
| pnphy.c | ||
| qsphy.c | ||
| qsphyreg.h | ||
| rlphy.c | ||
| tdkphy.c | ||
| tdkphyreg.h | ||
| tlphy.c | ||
| tlphyreg.h | ||
| ukphy_subr.c | ||
| ukphy.c | ||
| xmphy.c | ||
| xmphyreg.h | ||