John Baldwin 215e7c161a Rework how we wire up interrupt sources to CPUs: ... - Throw out all of the logical APIC ID stuff. The Intel docs are somewhat ambiguous, but it seems that the "flat" cluster model we are currently using is only supported on Pentium and P6 family CPUs. The other "hierarchy" cluster model that is supported on all Intel CPUs with local APICs is severely underdocumented. For example, it's not clear if the OS needs to glean the topology of the APIC hierarchy from somewhere (neither ACPI nor MP Table include it) and setup the logical clusters based on the physical hierarchy or not. Not only that, but on certain Intel chipsets, even though there were 4 CPUs in a logical cluster, all the interrupts were only sent to one CPU anyway. - We now bind interrupts to individual CPUs using physical addressing via the local APIC IDs. This code has also moved out of the ioapic PIC driver and into the common interrupt source code so that it can be shared with MSI interrupt sources since MSI is addressed to APICs the same way that I/O APIC pins are. - Interrupt source classes grow a new method pic_assign_cpu() to bind an interrupt source to a specific local APIC ID. - The SMP code now tells the interrupt code which CPUs are avaiable to handle interrupts in a simpler and more intuitive manner. For one thing, it means we could now choose to not route interrupts to HT cores if we wanted to (this code is currently in place in fact, but under an #if 0 for now). - For now we simply do static round-robin of IRQs to CPUs when the first interrupt handler just as before, with the change that IRQs are now bound to individual CPUs rather than groups of up to 4 CPUs. - Because the IRQ to CPU mapping has now been moved up a layer, it would be easier to manage this mapping from higher levels. For example, we could allow drivers to specify a CPU affinity map for their interrupts, or we could allow a userland tool to bind IRQs to specific CPUs. The MFC is tentative, but I want to see if this fixes problems some folks had with UP APIC kernels on 6.0 on SMP machines (an SMP kernel would work fine, but a UP APIC kernel (such as GENERIC in RELENG_6) would lose interrupts). MFC after: 1 week		2006-02-28 22:24:55 +00:00
..
pcvt	Use ttyalloc() instead of ttymalloc()	2006-01-04 09:46:20 +00:00
atpic_vector.s	- Move PUSH_FRAME and POP_FRAME into machine/asmacros.h.	2005-12-05 21:44:47 +00:00
atpic.c	Rework how we wire up interrupt sources to CPUs:	2006-02-28 22:24:55 +00:00
ccbque.h
clock.c	Tweak how the MD code calls the fooclock() methods some. Instead of	2005-12-22 22:16:09 +00:00
elcr.c
elink.c
elink.h
icu.h	Change the i386 code to pass the interrupt vector as a separate argument	2005-12-05 22:39:09 +00:00
isa_dma.c
isa.c	__RMAN_RESOURCE_VISIBLE not necessary.	2005-09-25 20:21:48 +00:00
isa.h
nmi.c
npx.c	Don't panic if IRQ 13 doesn't exist. On some machines (see previous	2005-12-05 22:11:44 +00:00
pmtimer.c
prof_machdep.c
spic.c
spicreg.h
vesa.c	Fix -Wundef warnings found when compiling i386 LINT, GENERIC and	2005-12-05 11:58:35 +00:00