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47e073941f
To support virtual machines on arm64 add the vmm code. This is based on earlier work by Mihai Carabas and Alexandru Elisei at University Politehnica of Bucharest, with further work by myself and Mark Johnston. All AArch64 CPUs should work, however only the GICv3 interrupt controller is supported. There is initial support to allow the GICv2 to be supported in the future. Only pure Armv8.0 virtualisation is supported, the Virtualization Host Extensions are not currently used. With a separate userspace patch and U-Boot port FreeBSD guests are able to boot to multiuser mode, and the hypervisor can be tested with the kvm unit tests. Linux partially boots, but hangs before entering userspace. Other operating systems are untested. Sponsored by: Arm Ltd Sponsored by: Innovate UK Sponsored by: The FreeBSD Foundation Sponsored by: University Politehnica of Bucharest Differential Revision: https://reviews.freebsd.org/D37428
53 lines
2.1 KiB
C
53 lines
2.1 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2023 Arm Ltd
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#ifndef _VGIC_H_
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#define _VGIC_H_
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struct hyp;
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struct hypctx;
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struct vm_vgic_descr;
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extern device_t vgic_dev;
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bool vgic_present(void);
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void vgic_init(void);
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int vgic_attach_to_vm(struct hyp *hyp, struct vm_vgic_descr *descr);
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void vgic_detach_from_vm(struct hyp *hyp);
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void vgic_vminit(struct hyp *hyp);
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void vgic_cpuinit(struct hypctx *hypctx);
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void vgic_cpucleanup(struct hypctx *hypctx);
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void vgic_vmcleanup(struct hyp *hyp);
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int vgic_max_cpu_count(struct hyp *hyp);
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bool vgic_has_pending_irq(struct hypctx *hypctx);
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int vgic_inject_irq(struct hyp *hyp, int vcpuid, uint32_t irqid, bool level);
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int vgic_inject_msi(struct hyp *hyp, uint64_t msg, uint64_t addr);
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void vgic_flush_hwstate(struct hypctx *hypctx);
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void vgic_sync_hwstate(struct hypctx *hypctx);
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#endif /* _VGIC_H_ */
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