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43469be308
Move definition of `stat_imask' to clock.c. clock.c: Rename `rtcmask' to `stat_imask' and export it. Rename `clkmask' to `clk_imask' for consistency. Only calculate TIMER_DIV(hz) once. Merge debugging and "garbage" code to produce debugging code and format the output better. Make writertc() static inline and use it everywhere. Now all accesses to the clock registers go through rtcin() and writertc(). Move rtc initialization to cpu_initclocks(). Merge enablertclock() with cpu_initclocks() and remove enablertclock(). The extra entry point was just a leftover from 1.1.5.
336 lines
9.4 KiB
ArmAsm
336 lines
9.4 KiB
ArmAsm
/*-
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* Copyright (c) 1989, 1990 William F. Jolitz.
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* Copyright (c) 1990 The Regents of the University of California.
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* All rights reserved.
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*
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* This code is derived from software contributed to Berkeley by
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* William Jolitz.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by the University of
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* California, Berkeley and its contributors.
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* 4. Neither the name of the University nor the names of its contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* @(#)icu.s 7.2 (Berkeley) 5/21/91
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*
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* $Id: icu.s,v 1.16 1994/12/03 10:03:16 bde Exp $
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*/
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/*
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* AT/386
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* Vector interrupt control section
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*/
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/*
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* XXX this file should be named ipl.s. All spls are now soft and the
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* only thing related to the hardware icu is that the h/w interrupt
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* numbers are used without translation in the masks.
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*/
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#include <net/netisr.h>
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.data
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.globl _cpl
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_cpl: .long HWI_MASK | SWI_MASK /* current priority (all off) */
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.globl _imen
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_imen: .long HWI_MASK /* interrupt mask enable (all h/w off) */
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.globl _tty_imask
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_tty_imask: .long 0
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.globl _bio_imask
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_bio_imask: .long 0
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.globl _net_imask
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_net_imask: .long 0
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.globl _ipending
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_ipending: .long 0
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.globl _astpending
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_astpending: .long 0 /* tells us an AST needs to be taken */
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.globl _netisr
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_netisr: .long 0 /* set with bits for which queue to service */
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vec:
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.long vec0, vec1, vec2, vec3, vec4, vec5, vec6, vec7
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.long vec8, vec9, vec10, vec11, vec12, vec13, vec14, vec15
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.text
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/*
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* Handle return from interrupts, traps and syscalls.
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*/
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SUPERALIGN_TEXT
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_doreti:
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FAKE_MCOUNT(_bintr) /* init "from" _bintr -> _doreti */
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addl $4,%esp /* discard unit number */
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popl %eax /* cpl to restore */
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doreti_next:
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/*
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* Check for pending HWIs and SWIs atomically with restoring cpl
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* and exiting. The check has to be atomic with exiting to stop
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* (ipending & ~cpl) changing from zero to nonzero while we're
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* looking at it (this wouldn't be fatal but it would increase
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* interrupt latency). Restoring cpl has to be atomic with exiting
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* so that the stack cannot pile up (the nesting level of interrupt
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* handlers is limited by the number of bits in cpl).
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*/
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movl %eax,%ecx
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notl %ecx
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cli
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andl _ipending,%ecx
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jne doreti_unpend
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doreti_exit:
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movl %eax,_cpl
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decb _intr_nesting_level
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MEXITCOUNT
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popl %es
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popl %ds
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popal
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addl $8,%esp
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iret
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ALIGN_TEXT
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doreti_unpend:
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/*
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* Enabling interrupts is safe because we haven't restored cpl yet.
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* The locking from the "btrl" test is probably no longer necessary.
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* We won't miss any new pending interrupts because we will check
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* for them again.
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*/
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sti
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bsfl %ecx,%ecx /* slow, but not worth optimizing */
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btrl %ecx,_ipending
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jnc doreti_next /* some intr cleared memory copy */
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movl ihandlers(,%ecx,4),%edx
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testl %edx,%edx
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je doreti_next /* "can't happen" */
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cmpl $NHWI,%ecx
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jae doreti_swi
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cli
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movl %eax,_cpl
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MEXITCOUNT
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jmp %edx
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ALIGN_TEXT
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doreti_swi:
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pushl %eax
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/*
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* The SWI_AST handler has to run at cpl = SWI_AST_MASK and the
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* SWI_CLOCK handler at cpl = SWI_CLOCK_MASK, so we have to restore
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* all the h/w bits in cpl now and have to worry about stack growth.
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* The worst case is currently (30 Jan 1994) 2 SWI handlers nested
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* in dying interrupt frames and about 12 HWIs nested in active
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* interrupt frames. There are only 4 different SWIs and the HWI
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* and SWI masks limit the nesting further.
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*/
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orl imasks(,%ecx,4),%eax
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movl %eax,_cpl
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call %edx
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popl %eax
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jmp doreti_next
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ALIGN_TEXT
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swi_ast:
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addl $8,%esp /* discard raddr & cpl to get trap frame */
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testb $SEL_RPL_MASK,TRAPF_CS_OFF(%esp)
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je swi_ast_phantom
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movl $T_ASTFLT,(2+8+0)*4(%esp)
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call _trap
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subl %eax,%eax /* recover cpl */
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jmp doreti_next
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ALIGN_TEXT
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swi_ast_phantom:
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/*
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* These happen when there is an interrupt in a trap handler before
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* ASTs can be masked or in an lcall handler before they can be
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* masked or after they are unmasked. They could be avoided for
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* trap entries by using interrupt gates, and for lcall exits by
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* using by using cli, but they are unavoidable for lcall entries.
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*/
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cli
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orl $SWI_AST_PENDING,_ipending
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jmp doreti_exit /* SWI_AST is highest so we must be done */
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/*
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* Interrupt priority mechanism
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* -- soft splXX masks with group mechanism (cpl)
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* -- h/w masks for currently active or unused interrupts (imen)
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* -- ipending = active interrupts currently masked by cpl
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*/
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ENTRY(splz)
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/*
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* The caller has restored cpl and checked that (ipending & ~cpl)
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* is nonzero. We have to repeat the check since if there is an
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* interrupt while we're looking, _doreti processing for the
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* interrupt will handle all the unmasked pending interrupts
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* because we restored early. We're repeating the calculation
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* of (ipending & ~cpl) anyway so that the caller doesn't have
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* to pass it, so this only costs one "jne". "bsfl %ecx,%ecx"
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* is undefined when %ecx is 0 so we can't rely on the secondary
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* btrl tests.
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*/
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movl _cpl,%eax
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splz_next:
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/*
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* We don't need any locking here. (ipending & ~cpl) cannot grow
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* while we're looking at it - any interrupt will shrink it to 0.
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*/
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movl %eax,%ecx
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notl %ecx
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andl _ipending,%ecx
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jne splz_unpend
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ret
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ALIGN_TEXT
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splz_unpend:
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bsfl %ecx,%ecx
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btrl %ecx,_ipending
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jnc splz_next
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movl ihandlers(,%ecx,4),%edx
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testl %edx,%edx
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je splz_next /* "can't happen" */
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cmpl $NHWI,%ecx
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jae splz_swi
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/*
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* We would prefer to call the intr handler directly here but that
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* doesn't work for badly behaved handlers that want the interrupt
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* frame. Also, there's a problem determining the unit number.
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* We should change the interface so that the unit number is not
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* determined at config time.
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*/
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jmp *vec(,%ecx,4)
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ALIGN_TEXT
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splz_swi:
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cmpl $SWI_AST,%ecx
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je splz_next /* "can't happen" */
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pushl %eax
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orl imasks(,%ecx,4),%eax
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movl %eax,_cpl
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call %edx
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popl %eax
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movl %eax,_cpl
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jmp splz_next
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/*
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* Fake clock interrupt(s) so that they appear to come from our caller instead
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* of from here, so that system profiling works.
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* XXX do this more generally (for all vectors; look up the C entry point).
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* XXX frame bogusness stops us from just jumping to the C entry point.
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*/
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ALIGN_TEXT
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vec0:
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popl %eax /* return address */
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pushfl
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#define KCSEL 8
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pushl $KCSEL
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pushl %eax
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cli
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MEXITCOUNT
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jmp _Xintr0 /* XXX might need _Xfastintr0 */
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ALIGN_TEXT
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vec8:
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popl %eax
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pushfl
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pushl $KCSEL
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pushl %eax
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cli
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MEXITCOUNT
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jmp _Xintr8 /* XXX might need _Xfastintr8 */
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#define BUILD_VEC(irq_num) \
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ALIGN_TEXT ; \
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vec/**/irq_num: ; \
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int $ICU_OFFSET + (irq_num) ; \
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ret
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BUILD_VEC(1)
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BUILD_VEC(2)
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BUILD_VEC(3)
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BUILD_VEC(4)
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BUILD_VEC(5)
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BUILD_VEC(6)
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BUILD_VEC(7)
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BUILD_VEC(9)
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BUILD_VEC(10)
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BUILD_VEC(11)
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BUILD_VEC(12)
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BUILD_VEC(13)
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BUILD_VEC(14)
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BUILD_VEC(15)
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ALIGN_TEXT
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.globl _dummynetisr
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_dummynetisr:
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MCOUNT
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ret
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.data
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.globl _netisrs
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_netisrs:
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.long _dummynetisr, _dummynetisr, _dummynetisr, _dummynetisr
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.long _dummynetisr, _dummynetisr, _dummynetisr, _dummynetisr
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.long _dummynetisr, _dummynetisr, _dummynetisr, _dummynetisr
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.long _dummynetisr, _dummynetisr, _dummynetisr, _dummynetisr
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.long _dummynetisr, _dummynetisr, _dummynetisr, _dummynetisr
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.long _dummynetisr, _dummynetisr, _dummynetisr, _dummynetisr
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.long _dummynetisr, _dummynetisr, _dummynetisr, _dummynetisr
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.long _dummynetisr, _dummynetisr, _dummynetisr, _dummynetisr
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.text
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#define DONET(s) ; \
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btrl $s,_netisr ; \
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jnc 9f ; \
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movl $_netisrs+4*s,%eax ; \
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call (%eax) ; \
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9:
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ALIGN_TEXT
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swi_net:
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MCOUNT
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DONET(0) ; DONET(1) ; DONET(2) ; DONET(3) ; DONET(4)
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DONET(5) ; DONET(6) ; DONET(7) ; DONET(8) ; DONET(9)
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DONET(10) ; DONET(11) ; DONET(12) ; DONET(13) ; DONET(14)
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DONET(15) ; DONET(16) ; DONET(17) ; DONET(18) ; DONET(19)
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DONET(20) ; DONET(21) ; DONET(22) ; DONET(23) ; DONET(24)
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DONET(25) ; DONET(26) ; DONET(27) ; DONET(28) ; DONET(29)
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DONET(30) ; DONET(31)
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ret
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/*
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* XXX there should be a registration function to put the handler for the
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* attached driver directly in ihandlers. Then this function will go away.
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*/
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ALIGN_TEXT
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swi_tty:
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MCOUNT
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#include "sio.h"
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#if NSIO > 0
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jmp _siopoll
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#else
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ret
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#endif
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