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88afb90f3c
This is the vastly updated cx drvier from Roman Kurakin <rik@cronyx.ru> who has been patiently waiting for this update for sometime. The driver is mostly a rewrite from the version we have in the tree. While some similarities remain, losing the little history that the old driver has is not a big loss, and the re@ felt it was easier this way (less error prone). The userland parts of this update will be committed shortly. The driver is not connected to the build yet. I want to make sure I don't break any platform at any time, so I want to test that with these files in the tree before I continue (on the off chance I'm forgetting a file). I changed the DEBUG macro to CX_DEBUG from the code that was submitted (to not break when we go to building with opt_global.h after the release), as well adding $FreeBSD$. Submitted by: Roman Kurakin Approved by: re@ <scottl>
906 lines
21 KiB
C
906 lines
21 KiB
C
/*
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* Cronyx-Sigma Driver Development Kit.
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*
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* Copyright (C) 1998 Cronyx Engineering.
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* Author: Pavel Novikov, <pavel@inr.net.kiae.su>
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*
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* Copyright (C) 1998-2003 Cronyx Engineering.
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* Author: Roman Kurakin, <rik@cronyx.ru>
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*
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* This software is distributed with NO WARRANTIES, not even the implied
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* warranties for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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*
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* Authors grant any other persons or organisations permission to use
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* or modify this software as long as this message is kept with the software,
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* all derivative works or modified versions.
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*
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* Cronyx Id: cxddk.c,v 1.1.2.2 2003/11/27 14:24:50 rik Exp $
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <dev/cx/machdep.h>
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#include <dev/cx/cxddk.h>
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#include <dev/cx/cxreg.h>
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#include <dev/cx/cronyxfw.h>
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#include <dev/cx/csigmafw.h>
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#define BYTE *(unsigned char*)&
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/* standard base port set */
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static short porttab [] = {
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0x200, 0x220, 0x240, 0x260, 0x280, 0x2a0, 0x2c0, 0x2e0,
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0x300, 0x320, 0x340, 0x360, 0x380, 0x3a0, 0x3c0, 0x3e0, 0
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};
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/*
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* Compute the optimal size of the receive buffer.
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*/
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static int cx_compute_buf_len (cx_chan_t *c)
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{
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int rbsz;
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if (c->mode == M_ASYNC) {
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rbsz = (c->rxbaud + 800 - 1) / 800 * 2;
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if (rbsz < 4)
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rbsz = 4;
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else if (rbsz > DMABUFSZ)
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rbsz = DMABUFSZ;
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}
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else
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rbsz = DMABUFSZ;
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return rbsz;
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}
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/*
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* Auto-detect the installed adapters.
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*/
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int cx_find (port_t *board_ports)
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{
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int i, n;
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for (i=0, n=0; porttab[i] && n<NBRD; i++)
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if (cx_probe_board (porttab[i], -1, -1))
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board_ports[n++] = porttab[i];
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return n;
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}
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/*
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* Initialize the adapter.
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*/
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int cx_open_board (cx_board_t *b, int num, port_t port, int irq, int dma)
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{
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cx_chan_t *c;
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if (num >= NBRD || ! cx_probe_board (port, irq, dma))
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return 0;
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/* init callback pointers */
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for (c=b->chan; c<b->chan+NCHAN; ++c) {
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c->call_on_tx = 0;
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c->call_on_rx = 0;
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c->call_on_msig = 0;
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c->call_on_err = 0;
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}
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cx_init (b, num, port, irq, dma);
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/* Loading firmware */
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if (! cx_setup_board (b, csigma_fw_data, csigma_fw_len, csigma_fw_tvec))
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return 0;
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return 1;
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}
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/*
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* Shutdown the adapter.
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*/
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void cx_close_board (cx_board_t *b)
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{
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cx_setup_board (b, 0, 0, 0);
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/* Reset the controller. */
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outb (BCR0(b->port), 0);
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if (b->chan[8].type || b->chan[12].type)
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outb (BCR0(b->port+0x10), 0);
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}
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/*
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* Start the channel.
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*/
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void cx_start_chan (cx_chan_t *c, cx_buf_t *cb, unsigned long phys)
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{
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int command = 0;
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int mode = 0;
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int ier = 0;
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int rbsz;
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c->overflow = 0;
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/* Setting up buffers */
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if (cb) {
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c->arbuf = cb->rbuffer[0];
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c->brbuf = cb->rbuffer[1];
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c->atbuf = cb->tbuffer[0];
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c->btbuf = cb->tbuffer[1];
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c->arphys = phys + ((char*)c->arbuf - (char*)cb);
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c->brphys = phys + ((char*)c->brbuf - (char*)cb);
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c->atphys = phys + ((char*)c->atbuf - (char*)cb);
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c->btphys = phys + ((char*)c->btbuf - (char*)cb);
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}
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/* Set current channel number */
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outb (CAR(c->port), c->num & 3);
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/* set receiver A buffer physical address */
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outw (ARBADRU(c->port), (unsigned short) (c->arphys>>16));
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outw (ARBADRL(c->port), (unsigned short) c->arphys);
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/* set receiver B buffer physical address */
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outw (BRBADRU(c->port), (unsigned short) (c->brphys>>16));
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outw (BRBADRL(c->port), (unsigned short) c->brphys);
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/* set transmitter A buffer physical address */
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outw (ATBADRU(c->port), (unsigned short) (c->atphys>>16));
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outw (ATBADRL(c->port), (unsigned short) c->atphys);
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/* set transmitter B buffer physical address */
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outw (BTBADRU(c->port), (unsigned short) (c->btphys>>16));
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outw (BTBADRL(c->port), (unsigned short) c->btphys);
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/* rx */
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command |= CCR_ENRX;
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ier |= IER_RXD;
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if (c->board->dma) {
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mode |= CMR_RXDMA;
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if (c->mode == M_ASYNC)
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ier |= IER_RET;
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}
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/* tx */
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command |= CCR_ENTX;
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ier |= (c->mode == M_ASYNC) ? IER_TXD : (IER_TXD | IER_TXMPTY);
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if (c->board->dma)
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mode |= CMR_TXDMA;
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/* Set mode */
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outb (CMR(c->port), mode | (c->mode == M_ASYNC ? CMR_ASYNC : CMR_HDLC));
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/* Clear and initialize channel */
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cx_cmd (c->port, CCR_CLRCH);
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cx_cmd (c->port, CCR_INITCH | command);
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if (c->mode == M_ASYNC)
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cx_cmd (c->port, CCR_ENTX);
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/* Start receiver */
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rbsz = cx_compute_buf_len(c);
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outw (ARBCNT(c->port), rbsz);
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outw (BRBCNT(c->port), rbsz);
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outw (ARBSTS(c->port), BSTS_OWN24);
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outw (BRBSTS(c->port), BSTS_OWN24);
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if (c->mode == M_ASYNC)
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ier |= IER_MDM;
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/* Enable interrupts */
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outb (IER(c->port), ier);
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/* Clear DTR and RTS */
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cx_set_dtr (c, 0);
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cx_set_rts (c, 0);
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}
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/*
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* Turn the receiver on/off.
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*/
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void cx_enable_receive (cx_chan_t *c, int on)
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{
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unsigned char ier;
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if (cx_receive_enabled(c) && ! on) {
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outb (CAR(c->port), c->num & 3);
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if (c->mode == M_ASYNC) {
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ier = inb (IER(c->port));
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outb (IER(c->port), ier & ~ (IER_RXD | IER_RET));
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}
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cx_cmd (c->port, CCR_DISRX);
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} else if (! cx_receive_enabled(c) && on) {
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outb (CAR(c->port), c->num & 3);
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ier = inb (IER(c->port));
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if (c->mode == M_ASYNC)
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outb (IER(c->port), ier | (IER_RXD | IER_RET));
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else
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outb (IER(c->port), ier | IER_RXD);
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cx_cmd (c->port, CCR_ENRX);
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}
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}
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/*
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* Turn the transmiter on/off.
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*/
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void cx_enable_transmit (cx_chan_t *c, int on)
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{
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if (cx_transmit_enabled(c) && ! on) {
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outb (CAR(c->port), c->num & 3);
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if (c->mode != M_ASYNC)
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outb (STCR(c->port), STC_ABORTTX | STC_SNDSPC);
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cx_cmd (c->port, CCR_DISTX);
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} else if (! cx_transmit_enabled(c) && on) {
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outb (CAR(c->port), c->num & 3);
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cx_cmd (c->port, CCR_ENTX);
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}
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}
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/*
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* Get channel status.
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*/
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int cx_receive_enabled (cx_chan_t *c)
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{
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outb (CAR(c->port), c->num & 3);
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return (inb (CSR(c->port)) & CSRA_RXEN) != 0;
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}
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int cx_transmit_enabled (cx_chan_t *c)
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{
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outb (CAR(c->port), c->num & 3);
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return (inb (CSR(c->port)) & CSRA_TXEN) != 0;
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}
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unsigned long cx_get_baud (cx_chan_t *c)
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{
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return (c->opt.tcor.clk == CLK_EXT) ? 0 : c->txbaud;
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}
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int cx_get_loop (cx_chan_t *c)
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{
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return c->opt.tcor.llm ? 1 : 0;
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}
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int cx_get_nrzi (cx_chan_t *c)
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{
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return c->opt.rcor.encod == ENCOD_NRZI;
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}
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int cx_get_dpll (cx_chan_t *c)
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{
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return c->opt.rcor.dpll ? 1 : 0;
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}
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void cx_set_baud (cx_chan_t *c, unsigned long bps)
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{
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int clock, period;
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c->txbaud = c->rxbaud = bps;
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/* Set current channel number */
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outb (CAR(c->port), c->num & 3);
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if (bps) {
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if (c->mode == M_ASYNC || c->opt.rcor.dpll || c->opt.tcor.llm) {
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/* Receive baud - internal */
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cx_clock (c->oscfreq, c->rxbaud, &clock, &period);
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c->opt.rcor.clk = clock;
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outb (RCOR(c->port), BYTE c->opt.rcor);
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outb (RBPR(c->port), period);
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} else {
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/* Receive baud - external */
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c->opt.rcor.clk = CLK_EXT;
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outb (RCOR(c->port), BYTE c->opt.rcor);
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outb (RBPR(c->port), 1);
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}
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/* Transmit baud - internal */
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cx_clock (c->oscfreq, c->txbaud, &clock, &period);
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c->opt.tcor.clk = clock;
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c->opt.tcor.ext1x = 0;
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outb (TBPR(c->port), period);
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} else if (c->mode != M_ASYNC) {
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/* External clock - disable local loopback and DPLL */
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c->opt.tcor.llm = 0;
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c->opt.rcor.dpll = 0;
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/* Transmit baud - external */
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c->opt.tcor.ext1x = 1;
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c->opt.tcor.clk = CLK_EXT;
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outb (TBPR(c->port), 1);
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/* Receive baud - external */
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c->opt.rcor.clk = CLK_EXT;
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outb (RCOR(c->port), BYTE c->opt.rcor);
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outb (RBPR(c->port), 1);
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}
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if (c->opt.tcor.llm)
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outb (COR2(c->port), (BYTE c->hopt.cor2) & ~3);
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else
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outb (COR2(c->port), BYTE c->hopt.cor2);
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outb (TCOR(c->port), BYTE c->opt.tcor);
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}
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void cx_set_loop (cx_chan_t *c, int on)
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{
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if (! c->txbaud)
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return;
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c->opt.tcor.llm = on ? 1 : 0;
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cx_set_baud (c, c->txbaud);
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}
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void cx_set_dpll (cx_chan_t *c, int on)
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{
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if (! c->txbaud)
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return;
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c->opt.rcor.dpll = on ? 1 : 0;
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cx_set_baud (c, c->txbaud);
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}
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void cx_set_nrzi (cx_chan_t *c, int nrzi)
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{
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c->opt.rcor.encod = (nrzi ? ENCOD_NRZI : ENCOD_NRZ);
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outb (CAR(c->port), c->num & 3);
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outb (RCOR(c->port), BYTE c->opt.rcor);
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}
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static int cx_send (cx_chan_t *c, char *data, int len,
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void *attachment)
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{
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unsigned char *buf;
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port_t cnt_port, sts_port;
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void **attp;
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/* Set the current channel number. */
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outb (CAR(c->port), c->num & 3);
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/* Determine the buffer order. */
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if (inb (DMABSTS(c->port)) & DMABSTS_NTBUF) {
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if (inb (BTBSTS(c->port)) & BSTS_OWN24) {
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buf = c->atbuf;
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cnt_port = ATBCNT(c->port);
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sts_port = ATBSTS(c->port);
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attp = &c->attach[0];
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} else {
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buf = c->btbuf;
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cnt_port = BTBCNT(c->port);
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sts_port = BTBSTS(c->port);
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attp = &c->attach[1];
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}
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} else {
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if (inb (ATBSTS(c->port)) & BSTS_OWN24) {
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buf = c->btbuf;
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cnt_port = BTBCNT(c->port);
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sts_port = BTBSTS(c->port);
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attp = &c->attach[1];
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} else {
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buf = c->atbuf;
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cnt_port = ATBCNT(c->port);
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sts_port = ATBSTS(c->port);
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attp = &c->attach[0];
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}
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}
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/* Is it busy? */
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if (inb (sts_port) & BSTS_OWN24)
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return -1;
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memcpy (buf, data, len);
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*attp = attachment;
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/* Start transmitter. */
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outw (cnt_port, len);
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outb (sts_port, BSTS_EOFR | BSTS_INTR | BSTS_OWN24);
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/* Enable TXMPTY interrupt,
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* to catch the case when the second buffer is empty. */
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if (c->mode != M_ASYNC) {
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if ((inb(ATBSTS(c->port)) & BSTS_OWN24) &&
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(inb(BTBSTS(c->port)) & BSTS_OWN24)) {
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outb (IER(c->port), IER_RXD | IER_TXD | IER_TXMPTY);
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} else
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outb (IER(c->port), IER_RXD | IER_TXD);
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}
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return 0;
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}
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/*
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* Number of free buffs
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*/
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int cx_buf_free (cx_chan_t *c)
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{
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return ! (inb (ATBSTS(c->port)) & BSTS_OWN24) +
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! (inb (BTBSTS(c->port)) & BSTS_OWN24);
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}
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/*
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* Send the data packet.
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*/
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int cx_send_packet (cx_chan_t *c, char *data, int len, void *attachment)
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{
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if (len >= DMABUFSZ)
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return -2;
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if (c->mode == M_ASYNC) {
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static char buf [DMABUFSZ];
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char *p, *t = buf;
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/* Async -- double all nulls. */
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for (p=data; p < data+len && t < buf+DMABUFSZ-1; ++p)
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if ((*t++ = *p) == 0)
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*t++ = 0;
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return cx_send (c, buf, t-buf, attachment);
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}
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return cx_send (c, data, len, attachment);
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}
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static int cx_receive_interrupt (cx_chan_t *c)
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{
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unsigned short risr;
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int len = 0, rbsz;
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++c->rintr;
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risr = inw (RISR(c->port));
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/* Compute optimal receiver buffer length */
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rbsz = cx_compute_buf_len(c);
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if (c->mode == M_ASYNC && (risr & RISA_TIMEOUT)) {
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unsigned long rcbadr = (unsigned short) inw (RCBADRL(c->port)) |
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(long) inw (RCBADRU(c->port)) << 16;
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unsigned char *buf = 0;
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port_t cnt_port = 0, sts_port = 0;
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if (rcbadr >= c->brphys && rcbadr < c->brphys+DMABUFSZ) {
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buf = c->brbuf;
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len = rcbadr - c->brphys;
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cnt_port = BRBCNT(c->port);
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sts_port = BRBSTS(c->port);
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} else if (rcbadr >= c->arphys && rcbadr < c->arphys+DMABUFSZ) {
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buf = c->arbuf;
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len = rcbadr - c->arphys;
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cnt_port = ARBCNT(c->port);
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sts_port = ARBSTS(c->port);
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}
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if (len) {
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c->ibytes += len;
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c->received_data = buf;
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c->received_len = len;
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/* Restart receiver. */
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outw (cnt_port, rbsz);
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outb (sts_port, BSTS_OWN24);
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}
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return (REOI_TERMBUFF);
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}
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/* Receive errors. */
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if (risr & RIS_OVERRUN) {
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++c->ierrs;
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if (c->call_on_err)
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c->call_on_err (c, CX_OVERRUN);
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|
} else if (c->mode != M_ASYNC && (risr & RISH_CRCERR)) {
|
|
++c->ierrs;
|
|
if (c->call_on_err)
|
|
c->call_on_err (c, CX_CRC);
|
|
} else if (c->mode != M_ASYNC && (risr & (RISH_RXABORT | RISH_RESIND))) {
|
|
++c->ierrs;
|
|
if (c->call_on_err)
|
|
c->call_on_err (c, CX_FRAME);
|
|
} else if (c->mode == M_ASYNC && (risr & RISA_PARERR)) {
|
|
++c->ierrs;
|
|
if (c->call_on_err)
|
|
c->call_on_err (c, CX_CRC);
|
|
} else if (c->mode == M_ASYNC && (risr & RISA_FRERR)) {
|
|
++c->ierrs;
|
|
if (c->call_on_err)
|
|
c->call_on_err (c, CX_FRAME);
|
|
} else if (c->mode == M_ASYNC && (risr & RISA_BREAK)) {
|
|
if (c->call_on_err)
|
|
c->call_on_err (c, CX_BREAK);
|
|
} else if (! (risr & RIS_EOBUF)) {
|
|
++c->ierrs;
|
|
} else {
|
|
/* Handle received data. */
|
|
len = (risr & RIS_BB) ? inw(BRBCNT(c->port)) : inw(ARBCNT(c->port));
|
|
|
|
if (len > DMABUFSZ) {
|
|
/* Fatal error: actual DMA transfer size
|
|
* exceeds our buffer size. It could be caused
|
|
* by incorrectly programmed DMA register or
|
|
* hardware fault. Possibly, should panic here. */
|
|
len = DMABUFSZ;
|
|
} else if (c->mode != M_ASYNC && ! (risr & RIS_EOFR)) {
|
|
/* The received frame does not fit in the DMA buffer.
|
|
* It could be caused by serial lie noise,
|
|
* or if the peer has too big MTU. */
|
|
if (! c->overflow) {
|
|
if (c->call_on_err)
|
|
c->call_on_err (c, CX_OVERFLOW);
|
|
c->overflow = 1;
|
|
++c->ierrs;
|
|
}
|
|
} else if (! c->overflow) {
|
|
if (risr & RIS_BB) {
|
|
c->received_data = c->brbuf;
|
|
c->received_len = len;
|
|
} else {
|
|
c->received_data = c->arbuf;
|
|
c->received_len = len;
|
|
}
|
|
if (c->mode != M_ASYNC)
|
|
++c->ipkts;
|
|
c->ibytes += len;
|
|
} else
|
|
c->overflow = 0;
|
|
}
|
|
|
|
/* Restart receiver. */
|
|
if (! (inb (ARBSTS(c->port)) & BSTS_OWN24)) {
|
|
outw (ARBCNT(c->port), rbsz);
|
|
outb (ARBSTS(c->port), BSTS_OWN24);
|
|
}
|
|
if (! (inb (BRBSTS(c->port)) & BSTS_OWN24)) {
|
|
outw (BRBCNT(c->port), rbsz);
|
|
outb (BRBSTS(c->port), BSTS_OWN24);
|
|
}
|
|
|
|
/* Discard exception characters. */
|
|
if ((risr & RISA_SCMASK) && c->aopt.cor2.ixon)
|
|
return (REOI_DISCEXC);
|
|
else
|
|
return (0);
|
|
}
|
|
|
|
static void cx_transmit_interrupt (cx_chan_t *c)
|
|
{
|
|
unsigned char tisr;
|
|
int len = 0;
|
|
|
|
++c->tintr;
|
|
tisr = inb (TISR(c->port));
|
|
if (tisr & TIS_UNDERRUN) { /* Transmit underrun error */
|
|
if (c->call_on_err)
|
|
c->call_on_err (c, CX_UNDERRUN);
|
|
++c->oerrs;
|
|
} else if (tisr & (TIS_EOBUF | TIS_TXEMPTY | TIS_TXDATA)) {
|
|
/* Call processing function */
|
|
if (tisr & TIS_BB) {
|
|
len = inw(BTBCNT(c->port));
|
|
if (c->call_on_tx)
|
|
c->call_on_tx (c, c->attach[1], len);
|
|
} else {
|
|
len = inw(ATBCNT(c->port));
|
|
if (c->call_on_tx)
|
|
c->call_on_tx (c, c->attach[0], len);
|
|
}
|
|
if (c->mode != M_ASYNC && len != 0)
|
|
++c->opkts;
|
|
c->obytes += len;
|
|
}
|
|
|
|
/* Enable TXMPTY interrupt,
|
|
* to catch the case when the second buffer is empty. */
|
|
if (c->mode != M_ASYNC) {
|
|
if ((inb (ATBSTS(c->port)) & BSTS_OWN24) &&
|
|
(inb (BTBSTS(c->port)) & BSTS_OWN24)) {
|
|
outb (IER(c->port), IER_RXD | IER_TXD | IER_TXMPTY);
|
|
} else
|
|
outb (IER(c->port), IER_RXD | IER_TXD);
|
|
}
|
|
}
|
|
|
|
void cx_int_handler (cx_board_t *b)
|
|
{
|
|
unsigned char livr;
|
|
cx_chan_t *c;
|
|
|
|
while (! (inw (BSR(b->port)) & BSR_NOINTR)) {
|
|
/* Enter the interrupt context, using IACK bus cycle.
|
|
Read the local interrupt vector register. */
|
|
livr = inb (IACK(b->port, BRD_INTR_LEVEL));
|
|
c = b->chan + (livr>>2 & 0xf);
|
|
if (c->type == T_NONE)
|
|
continue;
|
|
switch (livr & 3) {
|
|
case LIV_MODEM: /* modem interrupt */
|
|
++c->mintr;
|
|
if (c->call_on_msig)
|
|
c->call_on_msig (c);
|
|
outb (MEOIR(c->port), 0);
|
|
break;
|
|
case LIV_EXCEP: /* receive exception */
|
|
case LIV_RXDATA: /* receive interrupt */
|
|
outb (REOIR(c->port), cx_receive_interrupt (c));
|
|
if (c->call_on_rx && c->received_data) {
|
|
c->call_on_rx (c, c->received_data,
|
|
c->received_len);
|
|
c->received_data = 0;
|
|
}
|
|
break;
|
|
case LIV_TXDATA: /* transmit interrupt */
|
|
cx_transmit_interrupt (c);
|
|
outb (TEOIR(c->port), 0);
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Register event processing functions
|
|
*/
|
|
void cx_register_transmit (cx_chan_t *c,
|
|
void (*func) (cx_chan_t *c, void *attachment, int len))
|
|
{
|
|
c->call_on_tx = func;
|
|
}
|
|
|
|
void cx_register_receive (cx_chan_t *c,
|
|
void (*func) (cx_chan_t *c, char *data, int len))
|
|
{
|
|
c->call_on_rx = func;
|
|
}
|
|
|
|
void cx_register_modem (cx_chan_t *c, void (*func) (cx_chan_t *c))
|
|
{
|
|
c->call_on_msig = func;
|
|
}
|
|
|
|
void cx_register_error (cx_chan_t *c, void (*func) (cx_chan_t *c, int data))
|
|
{
|
|
c->call_on_err = func;
|
|
}
|
|
|
|
/*
|
|
* Async protocol functions.
|
|
*/
|
|
|
|
/*
|
|
* Enable/disable transmitter.
|
|
*/
|
|
void cx_transmitter_ctl (cx_chan_t *c,int start)
|
|
{
|
|
outb (CAR(c->port), c->num & 3);
|
|
cx_cmd (c->port, start ? CCR_ENTX : CCR_DISTX);
|
|
}
|
|
|
|
/*
|
|
* Discard all data queued in transmitter.
|
|
*/
|
|
void cx_flush_transmit (cx_chan_t *c)
|
|
{
|
|
outb (CAR(c->port), c->num & 3);
|
|
cx_cmd (c->port, CCR_CLRTX);
|
|
}
|
|
|
|
/*
|
|
* Send the XON/XOFF flow control symbol.
|
|
*/
|
|
void cx_xflow_ctl (cx_chan_t *c, int on)
|
|
{
|
|
outb (CAR(c->port), c->num & 3);
|
|
outb (STCR(c->port), STC_SNDSPC | (on ? STC_SSPC_1 : STC_SSPC_2));
|
|
}
|
|
|
|
/*
|
|
* Send the break signal for a given number of milliseconds.
|
|
*/
|
|
void cx_send_break (cx_chan_t *c, int msec)
|
|
{
|
|
static unsigned char buf [128];
|
|
unsigned char *p;
|
|
|
|
p = buf;
|
|
*p++ = 0; /* extended transmit command */
|
|
*p++ = 0x81; /* send break */
|
|
|
|
if (msec > 10000) /* max 10 seconds */
|
|
msec = 10000;
|
|
if (msec < 10) /* min 10 msec */
|
|
msec = 10;
|
|
while (msec > 0) {
|
|
int ms = 250; /* 250 msec */
|
|
if (ms > msec)
|
|
ms = msec;
|
|
msec -= ms;
|
|
*p++ = 0; /* extended transmit command */
|
|
*p++ = 0x82; /* insert delay */
|
|
*p++ = ms;
|
|
}
|
|
*p++ = 0; /* extended transmit command */
|
|
*p++ = 0x83; /* stop break */
|
|
|
|
cx_send (c, buf, p-buf, 0);
|
|
}
|
|
|
|
/*
|
|
* Set async parameters.
|
|
*/
|
|
void cx_set_async_param (cx_chan_t *c, int baud, int bits, int parity,
|
|
int stop2, int ignpar, int rtscts,
|
|
int ixon, int ixany, int symstart, int symstop)
|
|
{
|
|
int clock, period;
|
|
cx_cor1_async_t cor1;
|
|
|
|
/* Set character length and parity mode. */
|
|
BYTE cor1 = 0;
|
|
cor1.charlen = bits - 1;
|
|
cor1.parmode = parity ? PARM_NORMAL : PARM_NOPAR;
|
|
cor1.parity = parity==1 ? PAR_ODD : PAR_EVEN;
|
|
cor1.ignpar = ignpar ? 1 : 0;
|
|
|
|
/* Enable/disable hardware CTS. */
|
|
c->aopt.cor2.ctsae = rtscts ? 1 : 0;
|
|
|
|
/* Enable extended transmit command mode.
|
|
* Unfortunately, there is no other method for sending break. */
|
|
c->aopt.cor2.etc = 1;
|
|
|
|
/* Enable/disable hardware XON/XOFF. */
|
|
c->aopt.cor2.ixon = ixon ? 1 : 0;
|
|
c->aopt.cor2.ixany = ixany ? 1 : 0;
|
|
|
|
/* Set the number of stop bits. */
|
|
if (stop2)
|
|
c->aopt.cor3.stopb = STOPB_2;
|
|
else
|
|
c->aopt.cor3.stopb = STOPB_1;
|
|
|
|
/* Disable/enable passing XON/XOFF chars to the host. */
|
|
c->aopt.cor3.scde = ixon ? 1 : 0;
|
|
c->aopt.cor3.flowct = ixon ? FLOWCC_NOTPASS : FLOWCC_PASS;
|
|
|
|
c->aopt.schr1 = symstart; /* XON */
|
|
c->aopt.schr2 = symstop; /* XOFF */
|
|
|
|
/* Set current channel number. */
|
|
outb (CAR(c->port), c->num & 3);
|
|
|
|
/* Set up clock values. */
|
|
if (baud) {
|
|
c->rxbaud = c->txbaud = baud;
|
|
|
|
/* Receiver. */
|
|
cx_clock (c->oscfreq, c->rxbaud, &clock, &period);
|
|
c->opt.rcor.clk = clock;
|
|
outb (RCOR(c->port), BYTE c->opt.rcor);
|
|
outb (RBPR(c->port), period);
|
|
|
|
/* Transmitter. */
|
|
cx_clock (c->oscfreq, c->txbaud, &clock, &period);
|
|
c->opt.tcor.clk = clock;
|
|
c->opt.tcor.ext1x = 0;
|
|
outb (TCOR(c->port), BYTE c->opt.tcor);
|
|
outb (TBPR(c->port), period);
|
|
}
|
|
outb (COR2(c->port), BYTE c->aopt.cor2);
|
|
outb (COR3(c->port), BYTE c->aopt.cor3);
|
|
outb (SCHR1(c->port), c->aopt.schr1);
|
|
outb (SCHR2(c->port), c->aopt.schr2);
|
|
|
|
if (BYTE c->aopt.cor1 != BYTE cor1) {
|
|
BYTE c->aopt.cor1 = BYTE cor1;
|
|
outb (COR1(c->port), BYTE c->aopt.cor1);
|
|
/* Any change to COR1 require reinitialization. */
|
|
/* Unfortunately, it may cause transmitter glitches... */
|
|
cx_cmd (c->port, CCR_INITCH);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Set mode: M_ASYNC or M_HDLC.
|
|
* Both receiver and transmitter are disabled.
|
|
*/
|
|
int cx_set_mode (cx_chan_t *c, int mode)
|
|
{
|
|
if (mode == M_HDLC) {
|
|
if (c->type == T_ASYNC)
|
|
return -1;
|
|
|
|
if (c->mode == M_HDLC)
|
|
return 0;
|
|
|
|
c->mode = M_HDLC;
|
|
} else if (mode == M_ASYNC) {
|
|
if (c->type == T_SYNC_RS232 ||
|
|
c->type == T_SYNC_V35 ||
|
|
c->type == T_SYNC_RS449)
|
|
return -1;
|
|
|
|
if (c->mode == M_ASYNC)
|
|
return 0;
|
|
|
|
c->mode = M_ASYNC;
|
|
c->opt.tcor.ext1x = 0;
|
|
c->opt.tcor.llm = 0;
|
|
c->opt.rcor.dpll = 0;
|
|
c->opt.rcor.encod = ENCOD_NRZ;
|
|
if (! c->txbaud || ! c->rxbaud)
|
|
c->txbaud = c->rxbaud = 9600;
|
|
} else
|
|
return -1;
|
|
|
|
cx_setup_chan (c);
|
|
cx_start_chan (c, 0, 0);
|
|
cx_enable_receive (c, 0);
|
|
cx_enable_transmit (c, 0);
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* Set port type for old models of Sigma
|
|
*/
|
|
void cx_set_port (cx_chan_t *c, int iftype)
|
|
{
|
|
if (c->board->type == B_SIGMA_XXX) {
|
|
switch (c->num) {
|
|
case 0:
|
|
if ((c->board->if0type != 0) == (iftype != 0))
|
|
return;
|
|
c->board->if0type = iftype;
|
|
c->board->bcr0 &= ~BCR0_UMASK;
|
|
if (c->board->if0type &&
|
|
(c->type==T_UNIV_RS449 || c->type==T_UNIV_V35))
|
|
c->board->bcr0 |= BCR0_UI_RS449;
|
|
outb (BCR0(c->board->port), c->board->bcr0);
|
|
break;
|
|
case 8:
|
|
if ((c->board->if8type != 0) == (iftype != 0))
|
|
return;
|
|
c->board->if8type = iftype;
|
|
c->board->bcr0b &= ~BCR0_UMASK;
|
|
if (c->board->if8type &&
|
|
(c->type==T_UNIV_RS449 || c->type==T_UNIV_V35))
|
|
c->board->bcr0b |= BCR0_UI_RS449;
|
|
outb (BCR0(c->board->port+0x10), c->board->bcr0b);
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
|
|
/*
|
|
* Get port type for old models of Sigma
|
|
* -1 Fixed port type or auto detect
|
|
* 0 RS232
|
|
* 1 V35
|
|
* 2 RS449
|
|
*/
|
|
int cx_get_port (cx_chan_t *c)
|
|
{
|
|
int iftype;
|
|
|
|
if (c->board->type == B_SIGMA_XXX) {
|
|
switch (c->num) {
|
|
case 0:
|
|
iftype = c->board->if0type; break;
|
|
case 8:
|
|
iftype = c->board->if8type; break;
|
|
default:
|
|
return -1;
|
|
}
|
|
|
|
if (iftype)
|
|
switch (c->type) {
|
|
case T_UNIV_V35: return 1; break;
|
|
case T_UNIV_RS449: return 2; break;
|
|
default: return -1; break;
|
|
}
|
|
else
|
|
return 0;
|
|
} else
|
|
return -1;
|
|
}
|
|
|
|
void cx_intr_off (cx_board_t *b)
|
|
{
|
|
outb (BCR0(b->port), b->bcr0 & ~BCR0_IRQ_MASK);
|
|
if (b->chan[8].port || b->chan[12].port)
|
|
outb (BCR0(b->port+0x10), b->bcr0b & ~BCR0_IRQ_MASK);
|
|
}
|
|
|
|
void cx_intr_on (cx_board_t *b)
|
|
{
|
|
outb (BCR0(b->port), b->bcr0);
|
|
if (b->chan[8].port || b->chan[12].port)
|
|
outb (BCR0(b->port+0x10), b->bcr0b);
|
|
}
|
|
|
|
int cx_checkintr (cx_board_t *b)
|
|
{
|
|
return (!(inw (BSR(b->port)) & BSR_NOINTR));
|
|
}
|