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b47f51b4a0
SMP. We used to route all PIC based interrupts to cpu 0, and used the per-CPU interrupt mask to enable/disable interrupts. But the interrupt threads can run on any cpu on SMP, and the interrupt thread will re-enable the interrupts on the CPU it runs on when it is done, and not on cpu0 where the PIC will still send interrupts to. The fix is move the disable/enable for PIC based interrupts to PIC, we will ack on PIC only when the interrupt thread is done, and we do not use the per-CPU interrupt mask. The changes also introduce a way for subsystems to add a function that will be called to clear the interrupt on the subsystem. Currently This is used by the PCI/PCIe for doing additional work during the interrupt handling.
251 lines
6.1 KiB
C
251 lines
6.1 KiB
C
/*-
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* Copyright (c) 2006-2009 RMI Corporation
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* Copyright (c) 2002-2004 Juli Mallett <jmallett@FreeBSD.org>
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions, and the following disclaimer,
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* without modification, immediately at the beginning of the file.
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* 2. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
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* OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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*/
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#include <sys/cdefs.h>
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__FBSDID("$FreeBSD$");
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/interrupt.h>
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#include <sys/kernel.h>
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#include <machine/cpu.h>
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#include <machine/cpufunc.h>
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#include <machine/cpuinfo.h>
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#include <machine/cpuregs.h>
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#include <machine/frame.h>
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#include <machine/intr_machdep.h>
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#include <machine/md_var.h>
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#include <machine/trap.h>
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#include <machine/hwfunc.h>
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#include <mips/rmi/xlrconfig.h>
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#include <mips/rmi/interrupt.h>
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#include <mips/rmi/clock.h>
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#include <mips/rmi/pic.h>
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struct xlr_intrsrc {
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void (*busack)(int); /* Additional ack */
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struct intr_event *ie; /* event corresponding to intr */
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int irq;
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};
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static struct xlr_intrsrc xlr_interrupts[XLR_MAX_INTR];
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static mips_intrcnt_t mips_intr_counters[XLR_MAX_INTR];
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static int intrcnt_index;
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void
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xlr_enable_irq(int irq)
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{
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write_c0_eimr64(read_c0_eimr64() | (1ULL << irq));
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}
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void
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cpu_establish_softintr(const char *name, driver_filter_t * filt,
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void (*handler) (void *), void *arg, int irq, int flags,
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void **cookiep)
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{
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panic("Soft interrupts unsupported!\n");
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}
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void
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cpu_establish_hardintr(const char *name, driver_filter_t * filt,
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void (*handler) (void *), void *arg, int irq, int flags,
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void **cookiep)
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{
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xlr_establish_intr(name, filt, handler, arg, irq, flags,
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cookiep, NULL);
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}
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static void
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xlr_post_filter(void *source)
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{
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struct xlr_intrsrc *src = source;
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if (src->busack)
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src->busack(src->irq);
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pic_ack(PIC_IRQ_TO_INTR(src->irq));
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}
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static void
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xlr_pre_ithread(void *source)
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{
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struct xlr_intrsrc *src = source;
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if (src->busack)
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src->busack(src->irq);
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}
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static void
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xlr_post_ithread(void *source)
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{
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struct xlr_intrsrc *src = source;
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pic_ack(PIC_IRQ_TO_INTR(src->irq));
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}
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void
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xlr_establish_intr(const char *name, driver_filter_t filt,
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driver_intr_t handler, void *arg, int irq, int flags,
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void **cookiep, void (*busack)(int))
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{
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struct intr_event *ie; /* descriptor for the IRQ */
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struct xlr_intrsrc *src = NULL;
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int errcode;
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if (irq < 0 || irq > XLR_MAX_INTR)
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panic("%s called for unknown hard intr %d", __func__, irq);
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/*
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* FIXME locking - not needed now, because we do this only on
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* startup from CPU0
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*/
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printf("[%s] Setup intr %d called on cpu %d (%d)\n", name, irq,
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xlr_cpu_id(), PCPU_GET(cpuid));
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src = &xlr_interrupts[irq];
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ie = src->ie;
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if (ie == NULL) {
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/*
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* PIC based interrupts need ack in PIC, and some SoC
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* components need additional acks (e.g. PCI)
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*/
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if (PIC_IRQ_IS_PICINTR(irq))
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errcode = intr_event_create(&ie, src, 0, irq,
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xlr_pre_ithread, xlr_post_ithread, xlr_post_filter,
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NULL, "hard intr%d:", irq);
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else {
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if (filt == NULL)
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panic("Not supported - non filter percpu intr");
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errcode = intr_event_create(&ie, src, 0, irq,
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NULL, NULL, NULL, NULL, "hard intr%d:", irq);
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}
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if (errcode) {
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printf("Could not create event for intr %d\n", irq);
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return;
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}
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src->irq = irq;
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src->busack = busack;
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src->ie = ie;
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}
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intr_event_add_handler(ie, name, filt, handler, arg,
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intr_priority(flags), flags, cookiep);
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xlr_enable_irq(irq);
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}
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void
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cpu_intr(struct trapframe *tf)
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{
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struct intr_event *ie;
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uint64_t eirr, eimr;
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int i;
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critical_enter();
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/* find a list of enabled interrupts */
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eirr = read_c0_eirr64();
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eimr = read_c0_eimr64();
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eirr &= eimr;
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if (eirr == 0) {
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critical_exit();
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return;
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}
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/*
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* No need to clear the EIRR here as the handler writes to
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* compare which ACKs the interrupt.
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*/
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if (eirr & (1 << IRQ_TIMER)) {
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intr_event_handle(xlr_interrupts[IRQ_TIMER].ie, tf);
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critical_exit();
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return;
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}
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/* FIXME sched pin >? LOCK>? */
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for (i = sizeof(eirr) * 8 - 1; i >= 0; i--) {
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if ((eirr & (1ULL << i)) == 0)
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continue;
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ie = xlr_interrupts[i].ie;
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/* Don't account special IRQs */
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switch (i) {
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case IRQ_IPI:
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case IRQ_MSGRING:
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break;
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default:
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mips_intrcnt_inc(mips_intr_counters[i]);
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}
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/* Ack the IRQ on the CPU */
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write_c0_eirr64(1ULL << i);
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if (intr_event_handle(ie, tf) != 0) {
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printf("stray interrupt %d\n", i);
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}
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}
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critical_exit();
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}
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void
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mips_intrcnt_setname(mips_intrcnt_t counter, const char *name)
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{
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int idx = counter - intrcnt;
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KASSERT(counter != NULL, ("mips_intrcnt_setname: NULL counter"));
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snprintf(intrnames + (MAXCOMLEN + 1) * idx,
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MAXCOMLEN + 1, "%-*s", MAXCOMLEN, name);
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}
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mips_intrcnt_t
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mips_intrcnt_create(const char* name)
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{
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mips_intrcnt_t counter = &intrcnt[intrcnt_index++];
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mips_intrcnt_setname(counter, name);
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return counter;
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}
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void
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cpu_init_interrupts()
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{
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int i;
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char name[MAXCOMLEN + 1];
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/*
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* Initialize all available vectors so spare IRQ
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* would show up in systat output
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*/
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for (i = 0; i < XLR_MAX_INTR; i++) {
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snprintf(name, MAXCOMLEN + 1, "int%d:", i);
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mips_intr_counters[i] = mips_intrcnt_create(name);
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}
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}
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