Add a driver for Emulex OneConnect ethernet cards (10 Gbit PCIe)
A manpage will come in a future commit. Submitted by: Naresh Raju Gottumukkala (emulex)
This commit is contained in:
parent
9b4f251484
commit
2f345d8ed5
|
@ -1972,6 +1972,7 @@ device xmphy # XaQti XMAC II
|
|||
# SMC EZ Card 1000 (SMC9462TX), D-Link DGE-500T, Asante FriendlyNet
|
||||
# GigaNIX 1000TA and 1000TPC, the Addtron AEG320T, the Surecom
|
||||
# EP-320G-TX and the Netgear GA622T.
|
||||
# oce: Emulex 10 Gbit adapters (OneConnect Ethernet)
|
||||
# pcn: Support for PCI fast ethernet adapters based on the AMD Am79c97x
|
||||
# PCnet-FAST, PCnet-FAST+, PCnet-FAST III, PCnet-PRO and PCnet-Home
|
||||
# chipsets. These can also be handled by the le(4) driver if the
|
||||
|
@ -2112,6 +2113,7 @@ device ixgbe # Intel Pro/10Gbe PCIE Ethernet
|
|||
device le # AMD Am7900 LANCE and Am79C9xx PCnet
|
||||
device mxge # Myricom Myri-10G 10GbE NIC
|
||||
device nxge # Neterion Xframe 10GbE Server/Storage Adapter
|
||||
device oce # Emulex 10 GbE (OneConnect Ethernet)
|
||||
device ti # Alteon Networks Tigon I/II gigabit Ethernet
|
||||
device txp # 3Com 3cR990 (``Typhoon'')
|
||||
device vx # 3Com 3c590, 3c595 (``Vortex'')
|
||||
|
|
|
@ -1068,6 +1068,12 @@ dev/e1000/e1000_mbx.c optional em | igb \
|
|||
compile-with "${NORMAL_C} -I$S/dev/e1000"
|
||||
dev/e1000/e1000_osdep.c optional em | igb \
|
||||
compile-with "${NORMAL_C} -I$S/dev/e1000"
|
||||
dev/oce/oce_hw.c optional oce pci
|
||||
dev/oce/oce_if.c optional oce pci
|
||||
dev/oce/oce_mbox.c optional oce pci
|
||||
dev/oce/oce_queue.c optional oce pci
|
||||
dev/oce/oce_sysctl.c optional oce pci
|
||||
dev/oce/oce_util.c optional oce pci
|
||||
dev/et/if_et.c optional et
|
||||
dev/en/if_en_pci.c optional en pci
|
||||
dev/en/midway.c optional en
|
||||
|
|
|
@ -0,0 +1,588 @@
|
|||
/*-
|
||||
* Copyright (C) 2012 Emulex
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the Emulex Corporation nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Contact Information:
|
||||
* freebsd-drivers@emulex.com
|
||||
*
|
||||
* Emulex
|
||||
* 3333 Susan Street
|
||||
* Costa Mesa, CA 92626
|
||||
*/
|
||||
|
||||
/* $FreeBSD$ */
|
||||
|
||||
#include "oce_if.h"
|
||||
|
||||
static int oce_POST(POCE_SOFTC sc);
|
||||
|
||||
/**
|
||||
* @brief Function to post status
|
||||
* @param sc software handle to the device
|
||||
*/
|
||||
static int
|
||||
oce_POST(POCE_SOFTC sc)
|
||||
{
|
||||
mpu_ep_semaphore_t post_status;
|
||||
int tmo = 60000;
|
||||
|
||||
/* read semaphore CSR */
|
||||
post_status.dw0 = OCE_READ_REG32(sc, csr, MPU_EP_SEMAPHORE(sc));
|
||||
|
||||
/* if host is ready then wait for fw ready else send POST */
|
||||
if (post_status.bits.stage <= POST_STAGE_AWAITING_HOST_RDY) {
|
||||
post_status.bits.stage = POST_STAGE_CHIP_RESET;
|
||||
OCE_WRITE_REG32(sc, csr, MPU_EP_SEMAPHORE(sc), post_status.dw0);
|
||||
}
|
||||
|
||||
/* wait for FW ready */
|
||||
for (;;) {
|
||||
if (--tmo == 0)
|
||||
break;
|
||||
|
||||
DELAY(1000);
|
||||
|
||||
post_status.dw0 = OCE_READ_REG32(sc, csr, MPU_EP_SEMAPHORE(sc));
|
||||
if (post_status.bits.error) {
|
||||
device_printf(sc->dev,
|
||||
"POST failed: %x\n", post_status.dw0);
|
||||
return ENXIO;
|
||||
}
|
||||
if (post_status.bits.stage == POST_STAGE_ARMFW_READY)
|
||||
return 0;
|
||||
}
|
||||
|
||||
device_printf(sc->dev, "POST timed out: %x\n", post_status.dw0);
|
||||
|
||||
return ENXIO;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Function for hardware initialization
|
||||
* @param sc software handle to the device
|
||||
*/
|
||||
int
|
||||
oce_hw_init(POCE_SOFTC sc)
|
||||
{
|
||||
int rc = 0;
|
||||
|
||||
rc = oce_POST(sc);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
/* create the bootstrap mailbox */
|
||||
rc = oce_dma_alloc(sc, sizeof(struct oce_bmbx), &sc->bsmbx, 0);
|
||||
if (rc) {
|
||||
device_printf(sc->dev, "Mailbox alloc failed\n");
|
||||
return rc;
|
||||
}
|
||||
|
||||
rc = oce_reset_fun(sc);
|
||||
if (rc)
|
||||
goto error;
|
||||
|
||||
|
||||
rc = oce_mbox_init(sc);
|
||||
if (rc)
|
||||
goto error;
|
||||
|
||||
|
||||
rc = oce_get_fw_version(sc);
|
||||
if (rc)
|
||||
goto error;
|
||||
|
||||
|
||||
rc = oce_get_fw_config(sc);
|
||||
if (rc)
|
||||
goto error;
|
||||
|
||||
|
||||
sc->macaddr.size_of_struct = 6;
|
||||
rc = oce_read_mac_addr(sc, 0, 1, MAC_ADDRESS_TYPE_NETWORK,
|
||||
&sc->macaddr);
|
||||
if (rc)
|
||||
goto error;
|
||||
|
||||
if (IS_BE(sc) && (sc->flags & OCE_FLAGS_BE3)) {
|
||||
rc = oce_mbox_check_native_mode(sc);
|
||||
if (rc)
|
||||
goto error;
|
||||
} else
|
||||
sc->be3_native = 0;
|
||||
|
||||
return rc;
|
||||
|
||||
error:
|
||||
oce_dma_free(sc, &sc->bsmbx);
|
||||
device_printf(sc->dev, "Hardware initialisation failed\n");
|
||||
return rc;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Releases the obtained pci resources
|
||||
* @param sc software handle to the device
|
||||
*/
|
||||
void
|
||||
oce_hw_pci_free(POCE_SOFTC sc)
|
||||
{
|
||||
int pci_cfg_barnum = 0;
|
||||
|
||||
if (IS_BE(sc) && (sc->flags & OCE_FLAGS_BE2))
|
||||
pci_cfg_barnum = OCE_DEV_BE2_CFG_BAR;
|
||||
else
|
||||
pci_cfg_barnum = OCE_DEV_CFG_BAR;
|
||||
|
||||
if (sc->devcfg_res != NULL) {
|
||||
bus_release_resource(sc->dev,
|
||||
SYS_RES_MEMORY,
|
||||
PCIR_BAR(pci_cfg_barnum), sc->devcfg_res);
|
||||
sc->devcfg_res = (struct resource *)NULL;
|
||||
sc->devcfg_btag = (bus_space_tag_t) 0;
|
||||
sc->devcfg_bhandle = (bus_space_handle_t)0;
|
||||
sc->devcfg_vhandle = (void *)NULL;
|
||||
}
|
||||
|
||||
if (sc->csr_res != NULL) {
|
||||
bus_release_resource(sc->dev,
|
||||
SYS_RES_MEMORY,
|
||||
PCIR_BAR(OCE_PCI_CSR_BAR), sc->csr_res);
|
||||
sc->csr_res = (struct resource *)NULL;
|
||||
sc->csr_btag = (bus_space_tag_t)0;
|
||||
sc->csr_bhandle = (bus_space_handle_t)0;
|
||||
sc->csr_vhandle = (void *)NULL;
|
||||
}
|
||||
|
||||
if (sc->db_res != NULL) {
|
||||
bus_release_resource(sc->dev,
|
||||
SYS_RES_MEMORY,
|
||||
PCIR_BAR(OCE_PCI_DB_BAR), sc->db_res);
|
||||
sc->db_res = (struct resource *)NULL;
|
||||
sc->db_btag = (bus_space_tag_t)0;
|
||||
sc->db_bhandle = (bus_space_handle_t)0;
|
||||
sc->db_vhandle = (void *)NULL;
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function to get the PCI capabilities
|
||||
* @param sc software handle to the device
|
||||
*/
|
||||
static
|
||||
void oce_get_pci_capabilities(POCE_SOFTC sc)
|
||||
{
|
||||
uint32_t val;
|
||||
|
||||
if (pci_find_extcap(sc->dev, PCIY_PCIX, &val) == 0) {
|
||||
if (val != 0)
|
||||
sc->flags |= OCE_FLAGS_PCIX;
|
||||
}
|
||||
|
||||
if (pci_find_extcap(sc->dev, PCIY_EXPRESS, &val) == 0) {
|
||||
if (val != 0) {
|
||||
uint16_t link_status =
|
||||
pci_read_config(sc->dev, val + 0x12, 2);
|
||||
|
||||
sc->flags |= OCE_FLAGS_PCIE;
|
||||
sc->pcie_link_speed = link_status & 0xf;
|
||||
sc->pcie_link_width = (link_status >> 4) & 0x3f;
|
||||
}
|
||||
}
|
||||
|
||||
if (pci_find_extcap(sc->dev, PCIY_MSI, &val) == 0) {
|
||||
if (val != 0)
|
||||
sc->flags |= OCE_FLAGS_MSI_CAPABLE;
|
||||
}
|
||||
|
||||
if (pci_find_extcap(sc->dev, PCIY_MSIX, &val) == 0) {
|
||||
if (val != 0) {
|
||||
val = pci_msix_count(sc->dev);
|
||||
sc->flags |= OCE_FLAGS_MSIX_CAPABLE;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Allocate PCI resources.
|
||||
*
|
||||
* @param sc software handle to the device
|
||||
* @returns 0 if successful, or error
|
||||
*/
|
||||
int
|
||||
oce_hw_pci_alloc(POCE_SOFTC sc)
|
||||
{
|
||||
int rr, pci_cfg_barnum = 0;
|
||||
pci_sli_intf_t intf;
|
||||
|
||||
pci_enable_busmaster(sc->dev);
|
||||
|
||||
oce_get_pci_capabilities(sc);
|
||||
|
||||
sc->fn = pci_get_function(sc->dev);
|
||||
|
||||
/* setup the device config region */
|
||||
if (IS_BE(sc) && (sc->flags & OCE_FLAGS_BE2))
|
||||
pci_cfg_barnum = OCE_DEV_BE2_CFG_BAR;
|
||||
else
|
||||
pci_cfg_barnum = OCE_DEV_CFG_BAR;
|
||||
|
||||
rr = PCIR_BAR(pci_cfg_barnum);
|
||||
|
||||
if (IS_BE(sc))
|
||||
sc->devcfg_res = bus_alloc_resource_any(sc->dev,
|
||||
SYS_RES_MEMORY, &rr,
|
||||
RF_ACTIVE|RF_SHAREABLE);
|
||||
else
|
||||
sc->devcfg_res = bus_alloc_resource(sc->dev,
|
||||
SYS_RES_MEMORY, &rr,
|
||||
0ul, ~0ul, 32768,
|
||||
RF_ACTIVE|RF_SHAREABLE);
|
||||
|
||||
if (!sc->devcfg_res)
|
||||
goto error;
|
||||
|
||||
sc->devcfg_btag = rman_get_bustag(sc->devcfg_res);
|
||||
sc->devcfg_bhandle = rman_get_bushandle(sc->devcfg_res);
|
||||
sc->devcfg_vhandle = rman_get_virtual(sc->devcfg_res);
|
||||
|
||||
/* Read the SLI_INTF register and determine whether we
|
||||
* can use this port and its features
|
||||
*/
|
||||
intf.dw0 = pci_read_config((sc)->dev,OCE_INTF_REG_OFFSET,4);
|
||||
|
||||
if (intf.bits.sli_valid != OCE_INTF_VALID_SIG)
|
||||
goto error;
|
||||
|
||||
if (intf.bits.sli_rev != OCE_INTF_SLI_REV4) {
|
||||
device_printf(sc->dev, "Adapter doesnt support SLI4\n");
|
||||
goto error;
|
||||
}
|
||||
|
||||
if (intf.bits.sli_if_type == OCE_INTF_IF_TYPE_1)
|
||||
sc->flags |= OCE_FLAGS_MBOX_ENDIAN_RQD;
|
||||
|
||||
if (intf.bits.sli_hint1 == OCE_INTF_FUNC_RESET_REQD)
|
||||
sc->flags |= OCE_FLAGS_FUNCRESET_RQD;
|
||||
|
||||
if (intf.bits.sli_func_type == OCE_INTF_VIRT_FUNC)
|
||||
sc->flags |= OCE_FLAGS_VIRTUAL_PORT;
|
||||
|
||||
/* Lancer has one BAR (CFG) but BE3 has three (CFG, CSR, DB) */
|
||||
if (IS_BE(sc)) {
|
||||
/* set up CSR region */
|
||||
rr = PCIR_BAR(OCE_PCI_CSR_BAR);
|
||||
sc->csr_res = bus_alloc_resource_any(sc->dev,
|
||||
SYS_RES_MEMORY, &rr, RF_ACTIVE|RF_SHAREABLE);
|
||||
if (!sc->csr_res)
|
||||
goto error;
|
||||
sc->csr_btag = rman_get_bustag(sc->csr_res);
|
||||
sc->csr_bhandle = rman_get_bushandle(sc->csr_res);
|
||||
sc->csr_vhandle = rman_get_virtual(sc->csr_res);
|
||||
|
||||
/* set up DB doorbell region */
|
||||
rr = PCIR_BAR(OCE_PCI_DB_BAR);
|
||||
sc->db_res = bus_alloc_resource_any(sc->dev,
|
||||
SYS_RES_MEMORY, &rr, RF_ACTIVE|RF_SHAREABLE);
|
||||
if (!sc->db_res)
|
||||
goto error;
|
||||
sc->db_btag = rman_get_bustag(sc->db_res);
|
||||
sc->db_bhandle = rman_get_bushandle(sc->db_res);
|
||||
sc->db_vhandle = rman_get_virtual(sc->db_res);
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
error:
|
||||
oce_hw_pci_free(sc);
|
||||
return ENXIO;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for device shutdown
|
||||
* @param sc software handle to the device
|
||||
* @returns 0 on success, error otherwise
|
||||
*/
|
||||
void
|
||||
oce_hw_shutdown(POCE_SOFTC sc)
|
||||
{
|
||||
|
||||
oce_stats_free(sc);
|
||||
/* disable hardware interrupts */
|
||||
oce_hw_intr_disable(sc);
|
||||
/* Free LRO resources */
|
||||
oce_free_lro(sc);
|
||||
/* Release queue*/
|
||||
oce_queue_release_all(sc);
|
||||
/*Delete Network Interface*/
|
||||
oce_delete_nw_interface(sc);
|
||||
/* After fw clean we dont send any cmds to fw.*/
|
||||
oce_fw_clean(sc);
|
||||
/* release intr resources */
|
||||
oce_intr_free(sc);
|
||||
/* release PCI resources */
|
||||
oce_hw_pci_free(sc);
|
||||
/* free mbox specific resources */
|
||||
LOCK_DESTROY(&sc->bmbx_lock);
|
||||
LOCK_DESTROY(&sc->dev_lock);
|
||||
|
||||
oce_dma_free(sc, &sc->bsmbx);
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for creating nw interface.
|
||||
* @param sc software handle to the device
|
||||
* @returns 0 on success, error otherwise
|
||||
*/
|
||||
int
|
||||
oce_create_nw_interface(POCE_SOFTC sc)
|
||||
{
|
||||
int rc;
|
||||
uint32_t capab_flags;
|
||||
uint32_t capab_en_flags;
|
||||
|
||||
/* interface capabilities to give device when creating interface */
|
||||
capab_flags = OCE_CAPAB_FLAGS;
|
||||
|
||||
/* capabilities to enable by default (others set dynamically) */
|
||||
capab_en_flags = OCE_CAPAB_ENABLE;
|
||||
|
||||
if (IS_XE201(sc)) {
|
||||
/* LANCER A0 workaround */
|
||||
capab_en_flags &= ~MBX_RX_IFACE_FLAGS_PASS_L3L4_ERR;
|
||||
capab_flags &= ~MBX_RX_IFACE_FLAGS_PASS_L3L4_ERR;
|
||||
}
|
||||
|
||||
/* enable capabilities controlled via driver startup parameters */
|
||||
if (sc->rss_enable)
|
||||
capab_en_flags |= MBX_RX_IFACE_FLAGS_RSS;
|
||||
else {
|
||||
capab_en_flags &= ~MBX_RX_IFACE_FLAGS_RSS;
|
||||
capab_flags &= ~MBX_RX_IFACE_FLAGS_RSS;
|
||||
}
|
||||
|
||||
rc = oce_if_create(sc,
|
||||
capab_flags,
|
||||
capab_en_flags,
|
||||
0, &sc->macaddr.mac_addr[0], &sc->if_id);
|
||||
if (rc)
|
||||
return rc;
|
||||
|
||||
atomic_inc_32(&sc->nifs);
|
||||
|
||||
sc->if_cap_flags = capab_en_flags;
|
||||
|
||||
/* Enable VLAN Promisc on HW */
|
||||
rc = oce_config_vlan(sc, (uint8_t) sc->if_id, NULL, 0, 1, 1);
|
||||
if (rc)
|
||||
goto error;
|
||||
|
||||
/* set default flow control */
|
||||
rc = oce_set_flow_control(sc, sc->flow_control);
|
||||
if (rc)
|
||||
goto error;
|
||||
|
||||
rc = oce_rxf_set_promiscuous(sc, sc->promisc);
|
||||
if (rc)
|
||||
goto error;
|
||||
|
||||
return rc;
|
||||
|
||||
error:
|
||||
oce_delete_nw_interface(sc);
|
||||
return rc;
|
||||
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Function to delete a nw interface.
|
||||
* @param sc software handle to the device
|
||||
*/
|
||||
void
|
||||
oce_delete_nw_interface(POCE_SOFTC sc)
|
||||
{
|
||||
/* currently only single interface is implmeneted */
|
||||
if (sc->nifs > 0) {
|
||||
oce_if_del(sc, sc->if_id);
|
||||
atomic_dec_32(&sc->nifs);
|
||||
}
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Soft reset.
|
||||
* @param sc software handle to the device
|
||||
* @returns 0 on success, error otherwise
|
||||
*/
|
||||
int
|
||||
oce_pci_soft_reset(POCE_SOFTC sc)
|
||||
{
|
||||
int rc;
|
||||
mpu_ep_control_t ctrl;
|
||||
|
||||
ctrl.dw0 = OCE_READ_REG32(sc, csr, MPU_EP_CONTROL);
|
||||
ctrl.bits.cpu_reset = 1;
|
||||
OCE_WRITE_REG32(sc, csr, MPU_EP_CONTROL, ctrl.dw0);
|
||||
DELAY(50);
|
||||
rc=oce_POST(sc);
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Function for hardware start
|
||||
* @param sc software handle to the device
|
||||
* @returns 0 on success, error otherwise
|
||||
*/
|
||||
int
|
||||
oce_hw_start(POCE_SOFTC sc)
|
||||
{
|
||||
struct link_status link = { 0 };
|
||||
int rc = 0;
|
||||
|
||||
rc = oce_get_link_status(sc, &link);
|
||||
if (rc)
|
||||
return 1;
|
||||
|
||||
if (link.logical_link_status == NTWK_LOGICAL_LINK_UP) {
|
||||
sc->ifp->if_drv_flags |= IFF_DRV_RUNNING;
|
||||
sc->link_status = NTWK_LOGICAL_LINK_UP;
|
||||
if_link_state_change(sc->ifp, LINK_STATE_UP);
|
||||
} else {
|
||||
sc->ifp->if_drv_flags &=
|
||||
~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
|
||||
sc->link_status = NTWK_LOGICAL_LINK_DOWN;
|
||||
if_link_state_change(sc->ifp, LINK_STATE_DOWN);
|
||||
}
|
||||
|
||||
if (link.mac_speed > 0 && link.mac_speed < 5)
|
||||
sc->link_speed = link.mac_speed;
|
||||
else
|
||||
sc->link_speed = 0;
|
||||
|
||||
sc->qos_link_speed = (uint32_t )link.qos_link_speed * 10;
|
||||
|
||||
rc = oce_start_mq(sc->mq);
|
||||
|
||||
/* we need to get MCC aync events.
|
||||
So enable intrs and also arm first EQ
|
||||
*/
|
||||
oce_hw_intr_enable(sc);
|
||||
oce_arm_eq(sc, sc->eq[0]->eq_id, 0, TRUE, FALSE);
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for hardware enable interupts.
|
||||
* @param sc software handle to the device
|
||||
*/
|
||||
void
|
||||
oce_hw_intr_enable(POCE_SOFTC sc)
|
||||
{
|
||||
uint32_t reg;
|
||||
|
||||
reg = OCE_READ_REG32(sc, devcfg, PCICFG_INTR_CTRL);
|
||||
reg |= HOSTINTR_MASK;
|
||||
OCE_WRITE_REG32(sc, devcfg, PCICFG_INTR_CTRL, reg);
|
||||
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for hardware disable interupts
|
||||
* @param sc software handle to the device
|
||||
*/
|
||||
void
|
||||
oce_hw_intr_disable(POCE_SOFTC sc)
|
||||
{
|
||||
uint32_t reg;
|
||||
|
||||
reg = OCE_READ_REG32(sc, devcfg, PCICFG_INTR_CTRL);
|
||||
reg &= ~HOSTINTR_MASK;
|
||||
OCE_WRITE_REG32(sc, devcfg, PCICFG_INTR_CTRL, reg);
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Function for hardware update multicast filter
|
||||
* @param sc software handle to the device
|
||||
*/
|
||||
int
|
||||
oce_hw_update_multicast(POCE_SOFTC sc)
|
||||
{
|
||||
struct ifnet *ifp = sc->ifp;
|
||||
struct ifmultiaddr *ifma;
|
||||
struct mbx_set_common_iface_multicast *req = NULL;
|
||||
OCE_DMA_MEM dma;
|
||||
int rc = 0;
|
||||
|
||||
/* Allocate DMA mem*/
|
||||
if (oce_dma_alloc(sc, sizeof(struct mbx_set_common_iface_multicast),
|
||||
&dma, 0))
|
||||
return ENOMEM;
|
||||
|
||||
req = OCE_DMAPTR(&dma, struct mbx_set_common_iface_multicast);
|
||||
bzero(req, sizeof(struct mbx_set_common_iface_multicast));
|
||||
|
||||
#if __FreeBSD_version > 800000
|
||||
IF_ADDR_LOCK(ifp);
|
||||
#endif
|
||||
TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
|
||||
if (ifma->ifma_addr->sa_family != AF_LINK)
|
||||
continue;
|
||||
|
||||
if (req->params.req.num_mac == OCE_MAX_MC_FILTER_SIZE) {
|
||||
/*More multicast addresses than our hardware table
|
||||
So Enable multicast promiscus in our hardware to
|
||||
accept all multicat packets
|
||||
*/
|
||||
req->params.req.promiscuous = 1;
|
||||
break;
|
||||
}
|
||||
bcopy(LLADDR((struct sockaddr_dl *)ifma->ifma_addr),
|
||||
&req->params.req.mac[req->params.req.num_mac],
|
||||
ETH_ADDR_LEN);
|
||||
req->params.req.num_mac = req->params.req.num_mac + 1;
|
||||
}
|
||||
#if __FreeBSD_version > 800000
|
||||
IF_ADDR_UNLOCK(ifp);
|
||||
#endif
|
||||
req->params.req.if_id = sc->if_id;
|
||||
rc = oce_update_multicast(sc, &dma);
|
||||
oce_dma_free(sc, &dma);
|
||||
return rc;
|
||||
}
|
||||
|
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
@ -0,0 +1,270 @@
|
|||
/*-
|
||||
* Copyright (C) 2012 Emulex
|
||||
* All rights reserved.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
*
|
||||
* 1. Redistributions of source code must retain the above copyright notice,
|
||||
* this list of conditions and the following disclaimer.
|
||||
*
|
||||
* 2. Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
*
|
||||
* 3. Neither the name of the Emulex Corporation nor the names of its
|
||||
* contributors may be used to endorse or promote products derived from
|
||||
* this software without specific prior written permission.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
|
||||
* POSSIBILITY OF SUCH DAMAGE.
|
||||
*
|
||||
* Contact Information:
|
||||
* freebsd-drivers@emulex.com
|
||||
*
|
||||
* Emulex
|
||||
* 3333 Susan Street
|
||||
* Costa Mesa, CA 92626
|
||||
*/
|
||||
|
||||
|
||||
/* $FreeBSD$ */
|
||||
|
||||
|
||||
#include "oce_if.h"
|
||||
|
||||
static void oce_dma_map_ring(void *arg,
|
||||
bus_dma_segment_t *segs,
|
||||
int nseg,
|
||||
int error);
|
||||
|
||||
/**
|
||||
* @brief Allocate DMA memory
|
||||
* @param sc software handle to the device
|
||||
* @param size bus size
|
||||
* @param dma dma memory area
|
||||
* @param flags creation flags
|
||||
* @returns 0 on success, error otherwize
|
||||
*/
|
||||
int
|
||||
oce_dma_alloc(POCE_SOFTC sc, bus_size_t size, POCE_DMA_MEM dma, int flags)
|
||||
{
|
||||
int rc;
|
||||
|
||||
|
||||
memset(dma, 0, sizeof(OCE_DMA_MEM));
|
||||
|
||||
rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev),
|
||||
8, 0,
|
||||
BUS_SPACE_MAXADDR,
|
||||
BUS_SPACE_MAXADDR,
|
||||
NULL, NULL,
|
||||
size, 1, size, 0, NULL, NULL, &dma->tag);
|
||||
|
||||
if (rc == 0) {
|
||||
rc = bus_dmamem_alloc(dma->tag,
|
||||
&dma->ptr,
|
||||
BUS_DMA_NOWAIT | BUS_DMA_COHERENT,
|
||||
&dma->map);
|
||||
}
|
||||
|
||||
dma->paddr = 0;
|
||||
if (rc == 0) {
|
||||
rc = bus_dmamap_load(dma->tag,
|
||||
dma->map,
|
||||
dma->ptr,
|
||||
size,
|
||||
oce_dma_map_addr,
|
||||
&dma->paddr, flags | BUS_DMA_NOWAIT);
|
||||
if (dma->paddr == 0)
|
||||
rc = ENXIO;
|
||||
}
|
||||
|
||||
if (rc != 0)
|
||||
oce_dma_free(sc, dma);
|
||||
|
||||
return rc;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Free DMA memory
|
||||
* @param sc software handle to the device
|
||||
* @param dma dma area to free
|
||||
*/
|
||||
void
|
||||
oce_dma_free(POCE_SOFTC sc, POCE_DMA_MEM dma)
|
||||
{
|
||||
if (dma->tag == NULL)
|
||||
return;
|
||||
|
||||
if (dma->map != NULL) {
|
||||
bus_dmamap_sync(dma->tag, dma->map,
|
||||
BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
|
||||
bus_dmamap_unload(dma->tag, dma->map);
|
||||
}
|
||||
|
||||
if (dma->ptr != NULL) {
|
||||
bus_dmamem_free(dma->tag, dma->ptr, dma->map);
|
||||
dma->map = NULL;
|
||||
dma->ptr = NULL;
|
||||
}
|
||||
|
||||
bus_dma_tag_destroy(dma->tag);
|
||||
dma->tag = NULL;
|
||||
|
||||
return;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Map DMA memory segment addresses
|
||||
* @param arg physical address pointer
|
||||
* @param segs dma memory segments
|
||||
* @param nseg number of dma memory segments
|
||||
* @param error if error, zeroes the physical address
|
||||
*/
|
||||
void
|
||||
oce_dma_map_addr(void *arg, bus_dma_segment_t * segs, int nseg, int error)
|
||||
{
|
||||
bus_addr_t *paddr = arg;
|
||||
|
||||
if (error)
|
||||
*paddr = 0;
|
||||
else
|
||||
*paddr = segs->ds_addr;
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Destroy a ring buffer
|
||||
* @param sc software handle to the device
|
||||
* @param ring ring buffer
|
||||
*/
|
||||
|
||||
void
|
||||
oce_destroy_ring_buffer(POCE_SOFTC sc, oce_ring_buffer_t *ring)
|
||||
{
|
||||
oce_dma_free(sc, &ring->dma);
|
||||
free(ring, M_DEVBUF);
|
||||
}
|
||||
|
||||
|
||||
|
||||
oce_ring_buffer_t *
|
||||
oce_create_ring_buffer(POCE_SOFTC sc,
|
||||
uint32_t q_len, uint32_t item_size)
|
||||
{
|
||||
uint32_t size = q_len * item_size;
|
||||
int rc;
|
||||
oce_ring_buffer_t *ring;
|
||||
|
||||
|
||||
ring = malloc(sizeof(oce_ring_buffer_t), M_DEVBUF, M_NOWAIT | M_ZERO);
|
||||
if (ring == NULL)
|
||||
return NULL;
|
||||
|
||||
ring->item_size = item_size;
|
||||
ring->num_items = q_len;
|
||||
|
||||
rc = bus_dma_tag_create(bus_get_dma_tag(sc->dev),
|
||||
4096, 0,
|
||||
BUS_SPACE_MAXADDR,
|
||||
BUS_SPACE_MAXADDR,
|
||||
NULL, NULL,
|
||||
size, 8, 4096, 0, NULL, NULL, &ring->dma.tag);
|
||||
if (rc)
|
||||
goto fail;
|
||||
|
||||
|
||||
rc = bus_dmamem_alloc(ring->dma.tag,
|
||||
&ring->dma.ptr,
|
||||
BUS_DMA_NOWAIT | BUS_DMA_COHERENT,
|
||||
&ring->dma.map);
|
||||
if (rc)
|
||||
goto fail;
|
||||
|
||||
bzero(ring->dma.ptr, size);
|
||||
bus_dmamap_sync(ring->dma.tag, ring->dma.map,
|
||||
BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
|
||||
ring->dma.paddr = 0;
|
||||
|
||||
return ring;
|
||||
|
||||
fail:
|
||||
oce_dma_free(sc, &ring->dma);
|
||||
free(ring, M_DEVBUF);
|
||||
ring = NULL;
|
||||
return NULL;
|
||||
}
|
||||
|
||||
|
||||
|
||||
struct _oce_dmamap_paddr_table {
|
||||
uint32_t max_entries;
|
||||
uint32_t num_entries;
|
||||
struct phys_addr *paddrs;
|
||||
};
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Map ring buffer
|
||||
* @param arg dma map phyical address table pointer
|
||||
* @param segs dma memory segments
|
||||
* @param nseg number of dma memory segments
|
||||
* @param error maps only if error is 0
|
||||
*/
|
||||
static void
|
||||
oce_dma_map_ring(void *arg, bus_dma_segment_t * segs, int nseg, int error)
|
||||
{
|
||||
int i;
|
||||
struct _oce_dmamap_paddr_table *dpt =
|
||||
(struct _oce_dmamap_paddr_table *)arg;
|
||||
|
||||
if (error == 0) {
|
||||
if (nseg <= dpt->max_entries) {
|
||||
for (i = 0; i < nseg; i++) {
|
||||
dpt->paddrs[i].lo = ADDR_LO(segs[i].ds_addr);
|
||||
dpt->paddrs[i].hi = ADDR_HI(segs[i].ds_addr);
|
||||
}
|
||||
dpt->num_entries = nseg;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
|
||||
|
||||
/**
|
||||
* @brief Load bus dma map for a ring buffer
|
||||
* @param ring ring buffer pointer
|
||||
* @param pa_list physical address list
|
||||
* @returns number entries
|
||||
*/
|
||||
uint32_t
|
||||
oce_page_list(oce_ring_buffer_t *ring, struct phys_addr *pa_list)
|
||||
{
|
||||
struct _oce_dmamap_paddr_table dpt;
|
||||
|
||||
dpt.max_entries = 8;
|
||||
dpt.num_entries = 0;
|
||||
dpt.paddrs = pa_list;
|
||||
|
||||
bus_dmamap_load(ring->dma.tag,
|
||||
ring->dma.map,
|
||||
ring->dma.ptr,
|
||||
ring->item_size * ring->num_items,
|
||||
oce_dma_map_ring, &dpt, BUS_DMA_NOWAIT);
|
||||
|
||||
return dpt.num_entries;
|
||||
}
|
|
@ -240,6 +240,7 @@ SUBDIR= ${_3dfx} \
|
|||
${_nwfs} \
|
||||
${_nxge} \
|
||||
${_opensolaris} \
|
||||
oce \
|
||||
${_padlock} \
|
||||
patm \
|
||||
${_pccard} \
|
||||
|
|
|
@ -0,0 +1,15 @@
|
|||
#
|
||||
# $FreeBSD$
|
||||
#
|
||||
|
||||
.PATH: ${.CURDIR}/../../dev/oce
|
||||
KMOD = oce
|
||||
SRCS = oce_if.c oce_hw.c oce_mbox.c oce_util.c oce_queue.c oce_sysctl.c
|
||||
#SRCS += ${ofw_bus_if} bus_if.h device_if.h pci_if.h opt_inet.h opt_inet6.h
|
||||
|
||||
CFLAGS+= -I${.CURDIR}/../../dev/oce -DSMP
|
||||
|
||||
# uncomment for lock profiling statistics
|
||||
#CFLAGS += -DLOCK_PROFILING
|
||||
|
||||
.include <bsd.kmod.mk>
|
Loading…
Reference in New Issue