Incorporate changes made to the NetBSD version of this driver.
- Remove some obsolete code (NetBSD gem.c r1.12) - Clean up how the local MAC address is programmed (NetBSD gem.c r1.13) - Make the driver work on PowerMacs with gigabit interfaces (NetBSD gem.c r1.14 and r1.15, gemreg.h r1.3 and r1.4, gemvar.h r1.6 and 1.7) - Suppress RX_MAC interrutps regarding the FRAME_COUNT register. (NetBSD gem.c r1.16 and r1.17) - Fix receiver lockups. (NetBSD gem.c r1.18, gemvar.h r1.8) - Distinguish between Apple and Sun variants (NetBSD if_gem_pci.c r1.9) Reviewed by: tmm Obtained from: NetBSD
This commit is contained in:
Benno Rice
parent
d030984167
commit
336cca9e5f
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@ -23,7 +23,7 @@
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*
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* from: NetBSD: gem.c,v 1.9 2001/10/21 20:45:15 thorpej Exp
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* from: NetBSD: gem.c,v 1.21 2002/06/01 23:50:58 lukem Exp
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*
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* $FreeBSD$
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*/
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@ -124,6 +124,7 @@ gem_attach(sc)
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struct ifnet *ifp = &sc->sc_arpcom.ac_if;
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struct mii_softc *child;
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int i, error;
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u_int32_t v;
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/* Make sure the chip is stopped. */
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ifp->if_softc = sc;
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@ -228,7 +229,15 @@ gem_attach(sc)
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device_printf(sc->sc_dev, "Ethernet address:");
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for (i = 0; i < 6; i++)
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printf("%c%02x", i > 0 ? ':' : ' ', sc->sc_arpcom.ac_enaddr[i]);
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printf("\n");
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/* Get RX FIFO size */
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sc->sc_rxfifosize = 64 *
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bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_RX_FIFO_SIZE);
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printf(", %uKB RX fifo", sc->sc_rxfifosize / 1024);
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/* Get TX FIFO size */
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v = bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_FIFO_SIZE);
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printf(", %uKB TX fifo\n", v / 16);
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/* Initialize ifnet structure. */
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ifp->if_softc = sc;
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@ -416,6 +425,10 @@ gem_txdma_callback(xsc, segs, nsegs, error)
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CTR2(KTR_GEM, "txdma_cb: start of packet at seg %d, "
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"tx %d", seg, tx->txd_nexttx);
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flags |= GEM_TD_START_OF_PACKET;
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if (++tx->txd_sc->sc_txwin > GEM_NTXSEGS * 2 / 3) {
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tx->txd_sc->sc_txwin = 0;
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flags |= GEM_TD_INTERRUPT_ME;
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}
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}
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if ((tx->txd_flags & GTXD_LAST) != 0 && seg == nsegs - 1) {
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CTR2(KTR_GEM, "txdma_cb: end of packet at seg %d, "
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@ -680,8 +693,9 @@ gem_meminit(sc)
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}
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GEM_CDTXSYNC(sc, 0, GEM_NTXDESC,
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BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE);
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sc->sc_txfree = GEM_NTXDESC;
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sc->sc_txfree = GEM_NTXDESC-1;
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sc->sc_txnext = 0;
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sc->sc_txwin = 0;
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/*
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* Initialize the receive descriptor and receive job
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@ -821,7 +835,8 @@ gem_init(xsc)
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GEM_INTR_RX_TAG_ERR|GEM_INTR_PCS|
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GEM_INTR_MAC_CONTROL|GEM_INTR_MIF|
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GEM_INTR_BERR));
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bus_space_write_4(t, h, GEM_MAC_RX_MASK, 0); /* XXXX */
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bus_space_write_4(t, h, GEM_MAC_RX_MASK,
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GEM_MAC_RX_DONE|GEM_MAC_RX_FRAME_CNT);
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bus_space_write_4(t, h, GEM_MAC_TX_MASK, 0xffff); /* XXXX */
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bus_space_write_4(t, h, GEM_MAC_CONTROL_MASK, 0); /* XXXX */
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@ -844,14 +859,16 @@ gem_init(xsc)
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(2<<GEM_RX_CONFIG_FBOFF_SHFT)|GEM_RX_CONFIG_RXDMA_EN|
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(0<<GEM_RX_CONFIG_CXM_START_SHFT));
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/*
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* The following value is for an OFF Threshold of about 15.5 Kbytes
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* and an ON Threshold of 4K bytes.
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* The following value is for an OFF Threshold of about 3/4 full
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* and an ON Threshold of 1/4 full.
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*/
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bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH, 0xf8 | (0x40 << 12));
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bus_space_write_4(t, h, GEM_RX_BLANKING, (2<<12)|6);
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bus_space_write_4(t, h, GEM_RX_PAUSE_THRESH,
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(3 * sc->sc_rxfifosize / 256) |
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( (sc->sc_rxfifosize / 256) << 12));
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bus_space_write_4(t, h, GEM_RX_BLANKING, (6<<12)|6);
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/* step 11. Configure Media */
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(void)gem_mii_statchg(sc->sc_dev);
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mii_mediachg(sc->sc_mii);
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/* step 12. RX_MAC Configuration Register */
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v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG);
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@ -873,7 +890,7 @@ gem_init(xsc)
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ifp->if_flags |= IFF_RUNNING;
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ifp->if_flags &= ~IFF_OACTIVE;
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ifp->if_timer = 0;
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sc->sc_flags = ifp->if_flags;
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sc->sc_ifflags = ifp->if_flags;
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splx(s);
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}
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@ -1005,12 +1022,12 @@ static void
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gem_init_regs(sc)
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struct gem_softc *sc;
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{
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struct ifnet *ifp = &sc->sc_arpcom.ac_if;
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bus_space_tag_t t = sc->sc_bustag;
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bus_space_handle_t h = sc->sc_h;
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const u_char *laddr = sc->sc_arpcom.ac_enaddr;
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u_int32_t v;
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/* These regs are not cleared on reset */
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sc->sc_inited = 0;
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if (!sc->sc_inited) {
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/* Wooo. Magic values. */
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@ -1021,20 +1038,22 @@ gem_init_regs(sc)
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bus_space_write_4(t, h, GEM_MAC_MAC_MIN_FRAME, ETHER_MIN_LEN);
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/* Max frame and max burst size */
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bus_space_write_4(t, h, GEM_MAC_MAC_MAX_FRAME,
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(ifp->if_mtu+18) | (0x2000<<16)/* Burst size */);
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ETHER_MAX_LEN | (0x2000<<16));
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bus_space_write_4(t, h, GEM_MAC_PREAMBLE_LEN, 0x7);
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bus_space_write_4(t, h, GEM_MAC_JAM_SIZE, 0x4);
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bus_space_write_4(t, h, GEM_MAC_ATTEMPT_LIMIT, 0x10);
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/* Dunno.... */
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bus_space_write_4(t, h, GEM_MAC_CONTROL_TYPE, 0x8088);
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bus_space_write_4(t, h, GEM_MAC_RANDOM_SEED,
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((sc->sc_arpcom.ac_enaddr[5]<<8)|
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sc->sc_arpcom.ac_enaddr[4])&0x3ff);
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((laddr[5]<<8)|laddr[4])&0x3ff);
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/* Secondary MAC addr set to 0:0:0:0:0:0 */
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bus_space_write_4(t, h, GEM_MAC_ADDR3, 0);
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bus_space_write_4(t, h, GEM_MAC_ADDR4, 0);
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bus_space_write_4(t, h, GEM_MAC_ADDR5, 0);
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/* MAC control addr set to 0:1:c2:0:1:80 */
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/* MAC control addr set to 01:80:c2:00:00:01 */
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bus_space_write_4(t, h, GEM_MAC_ADDR6, 0x0001);
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bus_space_write_4(t, h, GEM_MAC_ADDR7, 0xc200);
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bus_space_write_4(t, h, GEM_MAC_ADDR8, 0x0180);
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@ -1073,12 +1092,21 @@ gem_init_regs(sc)
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/*
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* Set the station address.
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*/
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bus_space_write_4(t, h, GEM_MAC_ADDR0,
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(sc->sc_arpcom.ac_enaddr[4]<<8) | sc->sc_arpcom.ac_enaddr[5]);
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bus_space_write_4(t, h, GEM_MAC_ADDR1,
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(sc->sc_arpcom.ac_enaddr[2]<<8) | sc->sc_arpcom.ac_enaddr[3]);
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bus_space_write_4(t, h, GEM_MAC_ADDR2,
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(sc->sc_arpcom.ac_enaddr[0]<<8) | sc->sc_arpcom.ac_enaddr[1]);
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bus_space_write_4(t, h, GEM_MAC_ADDR0, (laddr[4]<<8)|laddr[5]);
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bus_space_write_4(t, h, GEM_MAC_ADDR1, (laddr[2]<<8)|laddr[3]);
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bus_space_write_4(t, h, GEM_MAC_ADDR2, (laddr[0]<<8)|laddr[1]);
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/*
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* Enable MII outputs. Enable GMII if there is a gigabit PHY.
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*/
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sc->sc_mif_config = bus_space_read_4(t, h, GEM_MIF_CONFIG);
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v = GEM_MAC_XIF_TX_MII_ENA;
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if (sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) {
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v |= GEM_MAC_XIF_FDPLX_LED;
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if (sc->sc_flags & GEM_GIGABIT)
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v |= GEM_MAC_XIF_GMII_MODE;
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}
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bus_space_write_4(t, h, GEM_MAC_XIF_CONFIG, v);
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}
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static void
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@ -1271,6 +1299,7 @@ gem_tint(sc)
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bus_space_handle_t mac = sc->sc_h;
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struct gem_txsoft *txs;
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int txlast;
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int progress = 0;
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DPRINTF(sc, ("%s: gem_tint\n", device_get_name(sc->sc_dev)));
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@ -1360,6 +1389,7 @@ gem_tint(sc)
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STAILQ_INSERT_TAIL(&sc->sc_txfreeq, txs, txs_q);
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ifp->if_opackets++;
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progress = 1;
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}
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DPRINTF(sc, ("gem_tint: GEM_TX_STATE_MACHINE %x "
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@ -1381,18 +1411,22 @@ gem_tint(sc)
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GEM_TX_DATA_PTR_LO),
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bus_space_read_4(sc->sc_bustag, sc->sc_h, GEM_TX_COMPLETION));
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if (STAILQ_FIRST(&sc->sc_txdirtyq) == NULL)
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ifp->if_timer = 0;
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if (progress) {
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if (sc->sc_txfree == GEM_NTXDESC - 1)
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sc->sc_txwin = 0;
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/* Freed some descriptors, so reset IFF_OACTIVE and restart. */
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ifp->if_flags &= ~IFF_OACTIVE;
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gem_start(ifp);
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if (STAILQ_EMPTY(&sc->sc_txdirtyq))
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ifp->if_timer = 0;
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}
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DPRINTF(sc, ("%s: gem_tint: watchdog %d\n",
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device_get_name(sc->sc_dev), ifp->if_timer));
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CTR2(KTR_GEM, "%s: gem_tint: watchdog %d",
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device_get_name(sc->sc_dev), ifp->if_timer);
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/* Freed some descriptors, so reset IFF_OACTIVE and restart. */
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ifp->if_flags &= ~IFF_OACTIVE;
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gem_start(ifp);
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}
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static void
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@ -1417,19 +1451,27 @@ gem_rint(sc)
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struct gem_rxsoft *rxs;
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struct mbuf *m;
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u_int64_t rxstat;
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int i, len;
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u_int32_t rxcomp;
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int i, len, progress = 0;
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callout_stop(&sc->sc_rx_ch);
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DPRINTF(sc, ("%s: gem_rint\n", device_get_name(sc->sc_dev)));
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CTR1(KTR_GEM, "%s: gem_rint", device_get_name(sc->sc_dev));
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/*
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* Read the completion register once. This limits
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* how long the following loop can execute.
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*/
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rxcomp = bus_space_read_4(t, h, GEM_RX_COMPLETION);
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/*
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* XXXX Read the lastrx only once at the top for speed.
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*/
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DPRINTF(sc, ("gem_rint: sc->rxptr %d, complete %d\n",
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sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION)));
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sc->sc_rxptr, rxcomp));
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CTR2(KTR_GEM, "gem_rint: sc->rxptr %d, complete %d",
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sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION));
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for (i = sc->sc_rxptr; i != bus_space_read_4(t, h, GEM_RX_COMPLETION);
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sc->sc_rxptr, rxcomp);
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for (i = sc->sc_rxptr; i != rxcomp;
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i = GEM_NEXTRX(i)) {
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rxs = &sc->sc_rxsoft[i];
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@ -1439,6 +1481,7 @@ gem_rint(sc)
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rxstat = GEM_DMA_READ(sc, sc->sc_rxdescs[i].gd_flags);
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if (rxstat & GEM_RD_OWN) {
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#if 0 /* XXX: In case of emergency, re-enable this. */
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/*
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* The descriptor is still marked as owned, although
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* it is supposed to have completed. This has been
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@ -1449,10 +1492,15 @@ gem_rint(sc)
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*/
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callout_reset(&sc->sc_rx_ch, GEM_RXOWN_TICKS,
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gem_rint_timeout, sc);
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#endif
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break;
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}
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progress++;
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ifp->if_ipackets++;
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if (rxstat & GEM_RD_BAD_CRC) {
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ifp->if_ierrors++;
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device_printf(sc->sc_dev, "receive error: CRC error\n");
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GEM_INIT_RXDESC(sc, i);
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continue;
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@ -1491,7 +1539,6 @@ gem_rint(sc)
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}
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m->m_data += 2; /* We're already off by two */
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ifp->if_ipackets++;
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eh = mtod(m, struct ether_header *);
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m->m_pkthdr.rcvif = ifp;
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m->m_pkthdr.len = m->m_len = len - ETHER_CRC_LEN;
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@ -1501,9 +1548,14 @@ gem_rint(sc)
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ether_input(ifp, eh, m);
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}
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/* Update the receive pointer. */
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sc->sc_rxptr = i;
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bus_space_write_4(t, h, GEM_RX_KICK, i);
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if (progress) {
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/* Update the receive pointer. */
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if (i == sc->sc_rxptr) {
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device_printf(sc->sc_dev, "rint: ring wrap\n");
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}
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sc->sc_rxptr = i;
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bus_space_write_4(t, h, GEM_RX_KICK, GEM_PREVRX(i));
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}
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DPRINTF(sc, ("gem_rint: done sc->rxptr %d, complete %d\n",
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sc->sc_rxptr, bus_space_read_4(t, h, GEM_RX_COMPLETION)));
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@ -1609,14 +1661,16 @@ gem_intr(v)
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if (status & GEM_INTR_TX_MAC) {
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int txstat = bus_space_read_4(t, seb, GEM_MAC_TX_STATUS);
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if (txstat & ~GEM_MAC_TX_XMIT_DONE)
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printf("MAC tx fault, status %x\n", txstat);
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device_printf(sc->sc_dev, "MAC tx fault, status %x\n",
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txstat);
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if (txstat & (GEM_MAC_TX_UNDERRUN | GEM_MAC_TX_PKT_TOO_LONG))
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gem_init(sc);
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}
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if (status & GEM_INTR_RX_MAC) {
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int rxstat = bus_space_read_4(t, seb, GEM_MAC_RX_STATUS);
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if (rxstat & ~(GEM_MAC_RX_DONE | GEM_MAC_RX_FRAME_CNT))
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printf("MAC rx fault, status %x\n", rxstat);
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device_printf(sc->sc_dev, "MAC rx fault, status %x\n",
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rxstat);
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if ((rxstat & GEM_MAC_RX_OVERFLOW) != 0)
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gem_init(sc);
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}
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@ -1800,6 +1854,7 @@ gem_mii_statchg(dev)
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v = bus_space_read_4(t, mac, GEM_MAC_XIF_CONFIG);
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v = GEM_MAC_XIF_LINK_LED;
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v |= GEM_MAC_XIF_TX_MII_ENA;
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/* If an external transceiver is connected, enable its MII drivers */
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sc->sc_mif_config = bus_space_read_4(t, mac, GEM_MIF_CONFIG);
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if ((sc->sc_mif_config & GEM_MIF_CONFIG_MDI1) != 0) {
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@ -1807,9 +1862,14 @@ gem_mii_statchg(dev)
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if ((IFM_OPTIONS(sc->sc_mii->mii_media_active) & IFM_FDX) != 0)
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/* turn on full duplex LED */
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v |= GEM_MAC_XIF_FDPLX_LED;
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else
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/* half duplex -- disable echo */
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v |= GEM_MAC_XIF_ECHO_DISABL;
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else
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/* half duplex -- disable echo */
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v |= GEM_MAC_XIF_ECHO_DISABL;
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if (IFM_SUBTYPE(sc->sc_mii->mii_media_active) == IFM_1000_T)
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v |= GEM_MAC_XIF_GMII_MODE;
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else
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v &= ~GEM_MAC_XIF_GMII_MODE;
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} else {
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/* Internal MII needs buf enable */
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v |= GEM_MAC_XIF_MII_BUF_ENA;
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@ -1864,7 +1924,7 @@ gem_ioctl(ifp, cmd, data)
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break;
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case SIOCSIFFLAGS:
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if (ifp->if_flags & IFF_UP) {
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if ((sc->sc_flags ^ ifp->if_flags) == IFF_PROMISC)
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if ((sc->sc_ifflags ^ ifp->if_flags) == IFF_PROMISC)
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gem_setladrf(sc);
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else
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gem_init(sc);
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@ -1872,7 +1932,7 @@ gem_ioctl(ifp, cmd, data)
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if (ifp->if_flags & IFF_RUNNING)
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gem_stop(ifp, 0);
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}
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sc->sc_flags = ifp->if_flags;
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sc->sc_ifflags = ifp->if_flags;
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error = 0;
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break;
|
||||
case SIOCADDMULTI:
|
||||
|
|
@ -1913,38 +1973,42 @@ gem_setladrf(sc)
|
|||
u_int32_t hash[16];
|
||||
u_int32_t v;
|
||||
int len;
|
||||
|
||||
/* Clear hash table */
|
||||
memset(hash, 0, sizeof(hash));
|
||||
int i;
|
||||
|
||||
/* Get current RX configuration */
|
||||
v = bus_space_read_4(t, h, GEM_MAC_RX_CONFIG);
|
||||
|
||||
/*
|
||||
* Turn off promiscuous mode, promiscuous group mode (all multicast),
|
||||
* and hash filter. Depending on the case, the right bit will be
|
||||
* enabled.
|
||||
*/
|
||||
v &= ~(GEM_MAC_RX_PROMISCUOUS|GEM_MAC_RX_HASH_FILTER|
|
||||
GEM_MAC_RX_PROMISC_GRP);
|
||||
|
||||
if ((ifp->if_flags & IFF_PROMISC) != 0) {
|
||||
/* Turn on promiscuous mode; turn off the hash filter */
|
||||
/* Turn on promiscuous mode */
|
||||
v |= GEM_MAC_RX_PROMISCUOUS;
|
||||
v &= ~GEM_MAC_RX_HASH_FILTER;
|
||||
;
|
||||
goto chipit;
|
||||
}
|
||||
if ((ifp->if_flags & IFF_ALLMULTI) != 0) {
|
||||
hash[3] = hash[2] = hash[1] = hash[0] = 0xffff;
|
||||
ifp->if_flags |= IFF_ALLMULTI;
|
||||
v |= GEM_MAC_RX_PROMISC_GRP;
|
||||
goto chipit;
|
||||
}
|
||||
|
||||
/* Turn off promiscuous mode; turn on the hash filter */
|
||||
v &= ~GEM_MAC_RX_PROMISCUOUS;
|
||||
v |= GEM_MAC_RX_HASH_FILTER;
|
||||
|
||||
/*
|
||||
* Set up multicast address filter by passing all multicast addresses
|
||||
* through a crc generator, and then using the high order 6 bits as an
|
||||
* index into the 256 bit logical address filter. The high order bit
|
||||
* selects the word, while the rest of the bits select the bit within
|
||||
* the word.
|
||||
* through a crc generator, and then using the high order 8 bits as an
|
||||
* index into the 256 bit logical address filter. The high order 4
|
||||
* bits selects the word, while the other 4 bits select the bit within
|
||||
* the word (where bit 0 is the MSB).
|
||||
*/
|
||||
|
||||
/* Clear hash table */
|
||||
memset(hash, 0, sizeof(hash));
|
||||
|
||||
TAILQ_FOREACH(inm, &sc->sc_arpcom.ac_if.if_multiaddrs, ifma_link) {
|
||||
if (inm->ifma_addr->sa_family != AF_LINK)
|
||||
continue;
|
||||
|
|
@ -1970,28 +2034,20 @@ gem_setladrf(sc)
|
|||
crc >>= 24;
|
||||
|
||||
/* Set the corresponding bit in the filter. */
|
||||
hash[crc >> 4] |= 1 << (crc & 0xf);
|
||||
hash[crc >> 4] |= 1 << (15 - (crc & 15));
|
||||
}
|
||||
|
||||
v |= GEM_MAC_RX_HASH_FILTER;
|
||||
ifp->if_flags &= ~IFF_ALLMULTI;
|
||||
|
||||
/* Now load the hash table into the chip (if we are using it) */
|
||||
for (i = 0; i < 16; i++) {
|
||||
bus_space_write_4(t, h,
|
||||
GEM_MAC_HASH0 + i * (GEM_MAC_HASH1-GEM_MAC_HASH0),
|
||||
hash[i]);
|
||||
}
|
||||
|
||||
chipit:
|
||||
/* Now load the hash table into the chip */
|
||||
bus_space_write_4(t, h, GEM_MAC_HASH0, hash[0]);
|
||||
bus_space_write_4(t, h, GEM_MAC_HASH1, hash[1]);
|
||||
bus_space_write_4(t, h, GEM_MAC_HASH2, hash[2]);
|
||||
bus_space_write_4(t, h, GEM_MAC_HASH3, hash[3]);
|
||||
bus_space_write_4(t, h, GEM_MAC_HASH4, hash[4]);
|
||||
bus_space_write_4(t, h, GEM_MAC_HASH5, hash[5]);
|
||||
bus_space_write_4(t, h, GEM_MAC_HASH6, hash[6]);
|
||||
bus_space_write_4(t, h, GEM_MAC_HASH7, hash[7]);
|
||||
bus_space_write_4(t, h, GEM_MAC_HASH8, hash[8]);
|
||||
bus_space_write_4(t, h, GEM_MAC_HASH9, hash[9]);
|
||||
bus_space_write_4(t, h, GEM_MAC_HASH10, hash[10]);
|
||||
bus_space_write_4(t, h, GEM_MAC_HASH11, hash[11]);
|
||||
bus_space_write_4(t, h, GEM_MAC_HASH12, hash[12]);
|
||||
bus_space_write_4(t, h, GEM_MAC_HASH13, hash[13]);
|
||||
bus_space_write_4(t, h, GEM_MAC_HASH14, hash[14]);
|
||||
bus_space_write_4(t, h, GEM_MAC_HASH15, hash[15]);
|
||||
|
||||
bus_space_write_4(t, h, GEM_MAC_RX_CONFIG, v);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -107,12 +107,13 @@ DRIVER_MODULE(if_gem, pci, gem_pci_driver, gem_devclass, 0, 0);
|
|||
|
||||
struct gem_pci_dev {
|
||||
u_int32_t gpd_devid;
|
||||
int gpd_variant;
|
||||
char *gpd_desc;
|
||||
} gem_pci_devlist[] = {
|
||||
{ 0x1101108e, "Sun ERI 10/100 Ethernet Adaptor" },
|
||||
{ 0x2bad108e, "Sun GEM Gigabit Ethernet Adaptor" },
|
||||
{ 0x0021106b, "Apple GMAC Ethernet Adaptor" },
|
||||
{ 0x0024106b, "Apple GMAC2 Ethernet Adaptor" },
|
||||
{ 0x1101108e, GEM_SUN_GEM, "Sun ERI 10/100 Ethernet Adaptor" },
|
||||
{ 0x2bad108e, GEM_SUN_GEM, "Sun GEM Gigabit Ethernet Adaptor" },
|
||||
{ 0x0021106b, GEM_APPLE_GMAC, "Apple GMAC Ethernet Adaptor" },
|
||||
{ 0x0024106b, GEM_APPLE_GMAC, "Apple GMAC2 Ethernet Adaptor" },
|
||||
{ 0, NULL }
|
||||
};
|
||||
|
||||
|
|
@ -125,11 +126,15 @@ gem_pci_probe(dev)
|
|||
{
|
||||
int i;
|
||||
u_int32_t devid;
|
||||
struct gem_pci_softc *gsc;
|
||||
|
||||
devid = pci_get_devid(dev);
|
||||
for (i = 0; gem_pci_devlist[i].gpd_desc != NULL; i++) {
|
||||
if (devid == gem_pci_devlist[i].gpd_devid) {
|
||||
device_set_desc(dev, gem_pci_devlist[i].gpd_desc);
|
||||
gsc = device_get_softc(dev);
|
||||
gsc->gsc_gem.sc_variant =
|
||||
gem_pci_devlist[i].gpd_variant;
|
||||
return (0);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -24,7 +24,7 @@
|
|||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* from: NetBSD: gemreg.h,v 1.2 2001/10/18 03:33:33 thorpej Exp
|
||||
* from: NetBSD: gemreg.h,v 1.15 2002/05/11 00:36:02 matt Exp
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
|
@ -205,13 +205,14 @@
|
|||
|
||||
/* GEM_RX_PAUSE_THRESH register bits -- sizes in multiples of 64 bytes */
|
||||
#define GEM_RX_PTH_XOFF_THRESH 0x000001ff
|
||||
#define GEM_RX_PTH_XON_THRESH 0x07fc0000
|
||||
#define GEM_RX_PTH_XON_THRESH 0x001ff000
|
||||
|
||||
|
||||
/* GEM_RX_BLANKING register bits */
|
||||
#define GEM_RX_BLANKING_PACKETS 0x000001ff /* Delay intr for x packets */
|
||||
#define GEM_RX_BLANKING_TIME 0x03fc0000 /* Delay intr for x ticks */
|
||||
/* One tick is 1048 PCI clocs, or 16us at 66MHz */
|
||||
#define GEM_RX_BLANKING_TIME 0x000ff000 /* Delay intr for x ticks */
|
||||
#define GEM_RX_BLANKING_TIME_SHIFT 12
|
||||
/* One tick is 2048 PCI clocks, or 16us at 66MHz */
|
||||
|
||||
|
||||
/* GEM_MAC registers */
|
||||
|
|
@ -324,7 +325,7 @@
|
|||
#define GEM_MAC_XIF_TX_MII_ENA 0x00000001 /* Enable XIF output drivers */
|
||||
#define GEM_MAC_XIF_MII_LOOPBK 0x00000002 /* Enable MII loopback mode */
|
||||
#define GEM_MAC_XIF_ECHO_DISABL 0x00000004 /* Disable echo */
|
||||
#define GEM_MAC_XIF_MII_MODE 0x00000008 /* Select GMII/MII mode */
|
||||
#define GEM_MAC_XIF_GMII_MODE 0x00000008 /* Select GMII/MII mode */
|
||||
#define GEM_MAC_XIF_MII_BUF_ENA 0x00000010 /* Enable MII recv buffers */
|
||||
#define GEM_MAC_XIF_LINK_LED 0x00000020 /* force link LED active */
|
||||
#define GEM_MAC_XIF_FDPLX_LED 0x00000040 /* force FDPLX LED active */
|
||||
|
|
|
|||
|
|
@ -23,7 +23,7 @@
|
|||
* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
|
||||
* SUCH DAMAGE.
|
||||
*
|
||||
* from: NetBSD: gemvar.h,v 1.5 2001/10/18 15:19:22 thorpej Exp
|
||||
* from: NetBSD: gemvar.h,v 1.8 2002/05/15 02:36:12 matt Exp
|
||||
*
|
||||
* $FreeBSD$
|
||||
*/
|
||||
|
|
@ -57,6 +57,7 @@
|
|||
*/
|
||||
#define GEM_NRXDESC 128
|
||||
#define GEM_NRXDESC_MASK (GEM_NRXDESC - 1)
|
||||
#define GEM_PREVRX(x) ((x - 1) & GEM_NRXDESC_MASK)
|
||||
#define GEM_NEXTRX(x) ((x + 1) & GEM_NRXDESC_MASK)
|
||||
|
||||
/*
|
||||
|
|
@ -153,6 +154,13 @@ struct gem_softc {
|
|||
int sc_mif_config; /* Selected MII reg setting */
|
||||
|
||||
int sc_pci; /* XXXXX -- PCI buses are LE. */
|
||||
u_int sc_variant; /* which GEM are we dealing with? */
|
||||
#define GEM_UNKNOWN 0 /* don't know */
|
||||
#define GEM_SUN_GEM 1 /* Sun GEM variant */
|
||||
#define GEM_APPLE_GMAC 2 /* Apple GMAC variant */
|
||||
|
||||
u_int sc_flags; /* */
|
||||
#define GEM_GIGABIT 0x0001 /* has a gigabit PHY */
|
||||
|
||||
/*
|
||||
* Ring buffer DMA stuff.
|
||||
|
|
@ -177,16 +185,18 @@ struct gem_softc {
|
|||
|
||||
int sc_txfree; /* number of free Tx descriptors */
|
||||
int sc_txnext; /* next ready Tx descriptor */
|
||||
int sc_txwin; /* Tx descriptors since last Tx int */
|
||||
|
||||
struct gem_txsq sc_txfreeq; /* free Tx descsofts */
|
||||
struct gem_txsq sc_txdirtyq; /* dirty Tx descsofts */
|
||||
|
||||
int sc_rxptr; /* next ready RX descriptor/descsoft */
|
||||
int sc_rxfifosize; /* Rx FIFO size (bytes) */
|
||||
|
||||
/* ========== */
|
||||
int sc_inited;
|
||||
int sc_debug;
|
||||
int sc_flags;
|
||||
int sc_ifflags;
|
||||
|
||||
/* Special hardware hooks */
|
||||
void (*sc_hwreset)(struct gem_softc *);
|
||||
|
|
|
|||
Loading…
Reference in New Issue