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Add SWI_TQ_MASK to all interrupt masks except SWI_CLOCK_MASK. Use a 

new macro SWI_LOW_MASK to give the mask for low priority SWIs instead
of hard-coding this mask as SWI_CLOCK_MASK.

Reviewed by:	dfr
This commit is contained in:
Bruce Evans 2000-05-31 13:32:28 +00:00
parent 1bcc7e80bf
commit 5f582114dd
13 changed files with 28 additions and 28 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
sys/amd64/amd64/fpu.c
View File

@ -136,7 +136,7 @@ SYSCTL_INT(_hw,HW_FLOATINGPT, floatingpoint,
"Floatingpoint instructions executed in hardware");
#ifndef SMP
static u_int npx0_imask = SWI_CLOCK_MASK;
static u_int npx0_imask = SWI_LOW_MASK;
static struct gate_descriptor npx_idt_probeintr;
static int npx_intrno;
static volatile u_int npx_intrs_while_probing;

2
sys/amd64/amd64/tsc.c
View File

@ -134,7 +134,7 @@ int clkintr_pending;
int disable_rtc_set; /* disable resettodr() if != 0 */
volatile u_int idelayed;
int statclock_disable;
u_int stat_imask = SWI_CLOCK_MASK;
u_int stat_imask = SWI_LOW_MASK;
#ifndef TIMER_FREQ
#define TIMER_FREQ 1193182
#endif

2
sys/amd64/isa/clock.c
View File

@ -134,7 +134,7 @@ int clkintr_pending;
int disable_rtc_set; /* disable resettodr() if != 0 */
volatile u_int idelayed;
int statclock_disable;
u_int stat_imask = SWI_CLOCK_MASK;
u_int stat_imask = SWI_LOW_MASK;
#ifndef TIMER_FREQ
#define TIMER_FREQ 1193182
#endif

4
sys/amd64/isa/intr_machdep.c
View File

@ -340,7 +340,7 @@ update_intr_masks(void)
maskptr = intr_mptr[intr];
if (!maskptr)
continue;
*maskptr |= SWI_CLOCK_MASK | (1 << intr);
*maskptr |= SWI_LOW_MASK | (1 << intr);
mask = *maskptr;
if (mask != intr_mask[intr]) {
#if 0
@ -427,7 +427,7 @@ icu_setup(int intr, inthand2_t *handler, void *arg, u_int *maskptr, int flags)
disable_intr();
intr_handler[intr] = handler;
intr_mptr[intr] = maskptr;
intr_mask[intr] = mask | SWI_CLOCK_MASK | (1 << intr);
intr_mask[intr] = mask | SWI_LOW_MASK | (1 << intr);
intr_unit[intr] = arg;
#ifdef FAST_HI
if (flags & INTR_FAST) {

4
sys/amd64/isa/nmi.c
View File

@ -340,7 +340,7 @@ update_intr_masks(void)
maskptr = intr_mptr[intr];
if (!maskptr)
continue;
*maskptr |= SWI_CLOCK_MASK | (1 << intr);
*maskptr |= SWI_LOW_MASK | (1 << intr);
mask = *maskptr;
if (mask != intr_mask[intr]) {
#if 0
@ -427,7 +427,7 @@ icu_setup(int intr, inthand2_t *handler, void *arg, u_int *maskptr, int flags)
disable_intr();
intr_handler[intr] = handler;
intr_mptr[intr] = maskptr;
intr_mask[intr] = mask | SWI_CLOCK_MASK | (1 << intr);
intr_mask[intr] = mask | SWI_LOW_MASK | (1 << intr);
intr_unit[intr] = arg;
#ifdef FAST_HI
if (flags & INTR_FAST) {

2
sys/amd64/isa/npx.c
View File

@ -136,7 +136,7 @@ SYSCTL_INT(_hw,HW_FLOATINGPT, floatingpoint,
"Floatingpoint instructions executed in hardware");
#ifndef SMP
static u_int npx0_imask = SWI_CLOCK_MASK;
static u_int npx0_imask = SWI_LOW_MASK;
static struct gate_descriptor npx_idt_probeintr;
static int npx_intrno;
static volatile u_int npx_intrs_while_probing;

2
sys/i386/i386/tsc.c
View File

@ -134,7 +134,7 @@ int clkintr_pending;
int disable_rtc_set; /* disable resettodr() if != 0 */
volatile u_int idelayed;
int statclock_disable;
u_int stat_imask = SWI_CLOCK_MASK;
u_int stat_imask = SWI_LOW_MASK;
#ifndef TIMER_FREQ
#define TIMER_FREQ 1193182
#endif

24
sys/i386/include/ipl.h
View File

@ -69,23 +69,23 @@
/*
* Corresponding interrupt-disable masks for cpl. The ordering is now by
* inclusion (where each mask is considered as a set of bits). Everything
* includes SWI_CLOCK_MASK so that softclock() doesn't
* run while other swi handlers are running and timeout routines can call
* swi handlers.
* SWI_TTY_MASK includes SWI_NET_MASK
* in case tty interrupts are processed at splsofttty() for a tty that is in
* inclusion (where each mask is considered as a set of bits). Everything
* except SWI_CLOCK_MASK includes SWI_LOW_MASK so that softclock() and low
* priority swi's don't run while other swi handlers are running and timeout
* routines can call swi handlers. SWI_TTY_MASK includes SWI_NET_MASK in
* case tty interrupts are processed at splsofttty() for a tty that is in
* SLIP or PPP line discipline (this is weaker than merging net_imask with
* tty_imask in isa.c - splimp() must mask hard and soft tty interrupts, but
* spltty() apparently only needs to mask soft net interrupts).
*/
#define SWI_TTY_MASK (SWI_TTY_PENDING | SWI_CLOCK_MASK | SWI_NET_MASK)
#define SWI_CAMNET_MASK (SWI_CAMNET_PENDING | SWI_CLOCK_MASK)
#define SWI_CAMBIO_MASK (SWI_CAMBIO_PENDING | SWI_CLOCK_MASK)
#define SWI_NET_MASK (SWI_NET_PENDING | SWI_CLOCK_MASK)
#define SWI_VM_MASK (SWI_VM_PENDING | SWI_CLOCK_MASK)
#define SWI_TQ_MASK (SWI_TQ_PENDING | SWI_CLOCK_MASK)
#define SWI_TTY_MASK (SWI_TTY_PENDING | SWI_LOW_MASK | SWI_NET_MASK)
#define SWI_CAMNET_MASK (SWI_CAMNET_PENDING | SWI_LOW_MASK)
#define SWI_CAMBIO_MASK (SWI_CAMBIO_PENDING | SWI_LOW_MASK)
#define SWI_NET_MASK (SWI_NET_PENDING | SWI_LOW_MASK)
#define SWI_VM_MASK (SWI_VM_PENDING | SWI_LOW_MASK)
#define SWI_TQ_MASK (SWI_TQ_PENDING | SWI_LOW_MASK)
#define SWI_CLOCK_MASK SWI_CLOCK_PENDING
#define SWI_LOW_MASK (SWI_TQ_PENDING | SWI_CLOCK_MASK)
#define SWI_MASK (~HWI_MASK)
/*

2
sys/i386/isa/clock.c
View File

@ -134,7 +134,7 @@ int clkintr_pending;
int disable_rtc_set; /* disable resettodr() if != 0 */
volatile u_int idelayed;
int statclock_disable;
u_int stat_imask = SWI_CLOCK_MASK;
u_int stat_imask = SWI_LOW_MASK;
#ifndef TIMER_FREQ
#define TIMER_FREQ 1193182
#endif

4
sys/i386/isa/intr_machdep.c
View File

@ -340,7 +340,7 @@ update_intr_masks(void)
maskptr = intr_mptr[intr];
if (!maskptr)
continue;
*maskptr |= SWI_CLOCK_MASK | (1 << intr);
*maskptr |= SWI_LOW_MASK | (1 << intr);
mask = *maskptr;
if (mask != intr_mask[intr]) {
#if 0
@ -427,7 +427,7 @@ icu_setup(int intr, inthand2_t *handler, void *arg, u_int *maskptr, int flags)
disable_intr();
intr_handler[intr] = handler;
intr_mptr[intr] = maskptr;
intr_mask[intr] = mask | SWI_CLOCK_MASK | (1 << intr);
intr_mask[intr] = mask | SWI_LOW_MASK | (1 << intr);
intr_unit[intr] = arg;
#ifdef FAST_HI
if (flags & INTR_FAST) {

4
sys/i386/isa/nmi.c
View File

@ -340,7 +340,7 @@ update_intr_masks(void)
maskptr = intr_mptr[intr];
if (!maskptr)
continue;
*maskptr |= SWI_CLOCK_MASK | (1 << intr);
*maskptr |= SWI_LOW_MASK | (1 << intr);
mask = *maskptr;
if (mask != intr_mask[intr]) {
#if 0
@ -427,7 +427,7 @@ icu_setup(int intr, inthand2_t *handler, void *arg, u_int *maskptr, int flags)
disable_intr();
intr_handler[intr] = handler;
intr_mptr[intr] = maskptr;
intr_mask[intr] = mask | SWI_CLOCK_MASK | (1 << intr);
intr_mask[intr] = mask | SWI_LOW_MASK | (1 << intr);
intr_unit[intr] = arg;
#ifdef FAST_HI
if (flags & INTR_FAST) {

2
sys/i386/isa/npx.c
View File

@ -136,7 +136,7 @@ SYSCTL_INT(_hw,HW_FLOATINGPT, floatingpoint,
"Floatingpoint instructions executed in hardware");
#ifndef SMP
static u_int npx0_imask = SWI_CLOCK_MASK;
static u_int npx0_imask = SWI_LOW_MASK;
static struct gate_descriptor npx_idt_probeintr;
static int npx_intrno;
static volatile u_int npx_intrs_while_probing;

2
sys/isa/atrtc.c
View File

@ -134,7 +134,7 @@ int clkintr_pending;
int disable_rtc_set; /* disable resettodr() if != 0 */
volatile u_int idelayed;
int statclock_disable;
u_int stat_imask = SWI_CLOCK_MASK;
u_int stat_imask = SWI_LOW_MASK;
#ifndef TIMER_FREQ
#define TIMER_FREQ 1193182
#endif