Synchronize with sys/i386/isa/npx.c revision 1.49.
This commit is contained in:
KATO Takenori
parent
b8b1bfc496
commit
684d56595c
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@ -32,7 +32,7 @@
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* SUCH DAMAGE.
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*
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* from: @(#)npx.c 7.2 (Berkeley) 5/12/91
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* $Id: npx.c,v 1.22 1997/07/17 10:35:01 kato Exp $
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* $Id: npx.c,v 1.23 1997/07/21 13:11:07 kato Exp $
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*/
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#include "npx.h"
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@ -59,11 +59,6 @@
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#include <machine/pcb.h>
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#include <machine/clock.h>
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#include <machine/specialreg.h>
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#if defined(APIC_IO)
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#include <machine/smp.h>
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#include <machine/apic.h>
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#include <machine/mpapic.h>
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#endif /* APIC_IO */
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#include <i386/isa/icu.h>
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#include <i386/isa/isa_device.h>
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@ -155,6 +150,7 @@ static volatile u_int npx_intrs_while_probing;
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static bool_t npx_irq13;
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static volatile u_int npx_traps_while_probing;
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#ifndef SMP
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/*
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* Special interrupt handlers. Someday intr0-intr15 will be used to count
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* interrupts. We'll still need a special exception 16 handler. The busy
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@ -162,30 +158,6 @@ static volatile u_int npx_traps_while_probing;
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*/
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inthand_t probeintr;
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#if defined(APIC_IO)
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asm
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("
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.text
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.p2align 2,0x90
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" __XSTRING(CNAME(probeintr)) ":
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ss
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incl " __XSTRING(CNAME(npx_intrs_while_probing)) "
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pushl %eax
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movl $lapic_eoi,%eax # EOI to local APIC
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movl $0,(%eax) # movl $0, APIC_EOI(%eax)
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movb $0,%al
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#ifdef PC98
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outb %al,$0xf8 # clear BUSY# latch
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#else
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outb %al,$0xf0 # clear BUSY# latch
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#endif
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popl %eax
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iret
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");
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#else
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asm
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("
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.text
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@ -212,8 +184,6 @@ asm
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iret
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");
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#endif /* APIC_IO */
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inthand_t probetrap;
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asm
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("
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@ -225,6 +195,8 @@ asm
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fnclex
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iret
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");
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#endif /* SMP */
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/*
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* Probe routine. Initialize cr0 to give correct behaviour for [f]wait
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@ -236,14 +208,16 @@ static int
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npxprobe(dvp)
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struct isa_device *dvp;
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{
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#ifdef SMP
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return npxprobe1(dvp);
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#else /* SMP */
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int result;
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u_long save_eflags;
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#if defined(APIC_IO)
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u_int save_apic_mask;
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#else
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u_char save_icu1_mask;
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u_char save_icu2_mask;
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#endif /* APIC_IO */
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struct gate_descriptor save_idt_npxintr;
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struct gate_descriptor save_idt_npxtrap;
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/*
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@ -256,9 +230,6 @@ npxprobe(dvp)
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npx_intrno = NRSVIDT + ffs(dvp->id_irq) - 1;
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save_eflags = read_eflags();
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disable_intr();
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#if defined(APIC_IO)
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save_apic_mask = INTRGET();
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#else
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#ifdef PC98
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save_icu1_mask = inb(IO_ICU1 + 2);
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save_icu2_mask = inb(IO_ICU2 + 2);
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@ -266,12 +237,8 @@ npxprobe(dvp)
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save_icu1_mask = inb(IO_ICU1 + 1);
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save_icu2_mask = inb(IO_ICU2 + 1);
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#endif
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#endif /* APIC_IO */
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save_idt_npxintr = idt[npx_intrno];
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save_idt_npxtrap = idt[16];
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#if defined(APIC_IO)
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INTRSET( ~dvp->id_irq );
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#else
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#ifdef PC98
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outb(IO_ICU1 + 2, ~(IRQ_SLAVE | dvp->id_irq));
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outb(IO_ICU2 + 2, ~(dvp->id_irq >> 8));
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@ -279,16 +246,12 @@ npxprobe(dvp)
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outb(IO_ICU1 + 1, ~(IRQ_SLAVE | dvp->id_irq));
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outb(IO_ICU2 + 1, ~(dvp->id_irq >> 8));
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#endif
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#endif /* APIC_IO */
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setidt(16, probetrap, SDT_SYS386TGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
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setidt(npx_intrno, probeintr, SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL));
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npx_idt_probeintr = idt[npx_intrno];
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enable_intr();
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result = npxprobe1(dvp);
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disable_intr();
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#if defined(APIC_IO)
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INTRSET( save_apic_mask );
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#else
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#ifdef PC98
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outb(IO_ICU1 + 2, save_icu1_mask);
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outb(IO_ICU2 + 2, save_icu2_mask);
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@ -296,11 +259,12 @@ npxprobe(dvp)
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outb(IO_ICU1 + 1, save_icu1_mask);
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outb(IO_ICU2 + 1, save_icu2_mask);
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#endif
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#endif /* APIC_IO */
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idt[npx_intrno] = save_idt_npxintr;
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idt[16] = save_idt_npxtrap;
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write_eflags(save_eflags);
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return (result);
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#endif /* SMP */
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}
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static int
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@ -346,6 +310,23 @@ npxprobe1(dvp)
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* IRQ13 and cleared the BUSY# latch early to handle them anyway.
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*/
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fninit();
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#ifdef SMP
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/*
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* Exception 16 MUST work for SMP.
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*/
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npx_irq13 = 0;
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npx_ex16 = hw_float = npx_exists = 1;
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dvp->id_irq = 0; /* zap the interrupt */
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/*
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* special return value to flag that we do not
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* actually use any I/O registers
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*/
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return (-1);
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#else /* SMP */
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/*
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* Don't use fwait here because it might hang.
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* Don't use fnop here because it usually hangs if there is no FPU.
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@ -428,6 +409,8 @@ npxprobe1(dvp)
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* actually use any I/O registers
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*/
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return (-1);
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#endif /* SMP */
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}
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/*
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@ -671,21 +654,23 @@ void
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npxsave(addr)
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struct save87 *addr;
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{
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#if defined(APIC_IO)
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u_int apic_mask;
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u_int old_apic_mask;
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#else
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#ifdef SMP
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stop_emulating();
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fnsave(addr);
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/* fnop(); */
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start_emulating();
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npxproc = NULL;
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#else /* SMP */
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u_char icu1_mask;
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u_char icu2_mask;
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u_char old_icu1_mask;
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u_char old_icu2_mask;
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#endif /* APIC_IO */
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struct gate_descriptor save_idt_npxintr;
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disable_intr();
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#if defined(APIC_IO)
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old_apic_mask = INTRGET();
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#else
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#ifdef PC98
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old_icu1_mask = inb(IO_ICU1 + 2);
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old_icu2_mask = inb(IO_ICU2 + 2);
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@ -693,12 +678,7 @@ npxsave(addr)
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old_icu1_mask = inb(IO_ICU1 + 1);
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old_icu2_mask = inb(IO_ICU2 + 1);
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#endif
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#endif /* APIC_IO */
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save_idt_npxintr = idt[npx_intrno];
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#if defined(APIC_IO)
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/** FIXME: try clrIoApicMaskBit( npx0_imask ); */
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INTRSET( old_apic_mask & ~(npx0_imask & 0xffff) );
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#else
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#ifdef PC98
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outb(IO_ICU1 + 2, old_icu1_mask & ~(IRQ_SLAVE | npx0_imask));
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outb(IO_ICU2 + 2, old_icu2_mask & ~(npx0_imask >> 8));
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@ -706,7 +686,6 @@ npxsave(addr)
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outb(IO_ICU1 + 1, old_icu1_mask & ~(IRQ_SLAVE | npx0_imask));
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outb(IO_ICU2 + 1, old_icu2_mask & ~(npx0_imask >> 8));
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#endif
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#endif /* APIC_IO */
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idt[npx_intrno] = npx_idt_probeintr;
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enable_intr();
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stop_emulating();
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@ -715,11 +694,6 @@ npxsave(addr)
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start_emulating();
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npxproc = NULL;
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disable_intr();
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#if defined(APIC_IO)
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apic_mask = INTRGET(); /* masks may have changed */
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INTRSET( (apic_mask & ~(npx0_imask & 0xffff)) |
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(old_apic_mask & (npx0_imask & 0xffff)));
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#else
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#ifdef PC98
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icu1_mask = inb(IO_ICU1 + 2); /* masks may have changed */
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icu2_mask = inb(IO_ICU2 + 2);
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@ -737,9 +711,10 @@ npxsave(addr)
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(icu2_mask & ~(npx0_imask >> 8))
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| (old_icu2_mask & (npx0_imask >> 8)));
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#endif
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#endif /* APIC_IO */
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idt[npx_intrno] = save_idt_npxintr;
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enable_intr(); /* back to usual state */
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#endif /* SMP */
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}
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#endif /* NNPX > 0 */
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