bhyve: Remove vmctx argument from PCI device model methods.
Most of these arguments were unused. Device models which do need access to the vmctx in one of these methods can obtain it from the pi_vmctx member of the pci_devinst argument instead. Reviewed by: corvink, markj Differential Revision: https://reviews.freebsd.org/D38096
This commit is contained in:
John Baldwin
parent
b36b14beda
commit
6a284cacb1
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@ -1491,7 +1491,7 @@ main(int argc, char *argv[])
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#ifdef BHYVE_SNAPSHOT
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if (restore_file != NULL) {
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fprintf(stdout, "Pausing pci devs...\r\n");
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if (vm_pause_user_devs(ctx) != 0) {
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if (vm_pause_user_devs() != 0) {
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fprintf(stderr, "Failed to pause PCI device state.\n");
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exit(1);
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}
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@ -1515,7 +1515,7 @@ main(int argc, char *argv[])
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}
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fprintf(stdout, "Resuming pci devs...\r\n");
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if (vm_resume_user_devs(ctx) != 0) {
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if (vm_resume_user_devs() != 0) {
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fprintf(stderr, "Failed to resume PCI device state.\n");
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exit(1);
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}
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@ -2197,8 +2197,7 @@ pci_ahci_host_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value)
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}
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static void
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pci_ahci_write(struct vmctx *ctx __unused,
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struct pci_devinst *pi, int baridx, uint64_t offset, int size,
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pci_ahci_write(struct pci_devinst *pi, int baridx, uint64_t offset, int size,
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uint64_t value)
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{
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struct pci_ahci_softc *sc = pi->pi_arg;
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@ -2292,8 +2291,7 @@ pci_ahci_port_read(struct pci_ahci_softc *sc, uint64_t offset)
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}
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static uint64_t
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pci_ahci_read(struct vmctx *ctx __unused,
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struct pci_devinst *pi, int baridx, uint64_t regoff, int size)
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pci_ahci_read(struct pci_devinst *pi, int baridx, uint64_t regoff, int size)
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{
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struct pci_ahci_softc *sc = pi->pi_arg;
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uint64_t offset;
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@ -2420,7 +2418,7 @@ pci_ahci_hd_legacy_config(nvlist_t *nvl, const char *opts)
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}
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static int
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pci_ahci_init(struct vmctx *ctx __unused, struct pci_devinst *pi, nvlist_t *nvl)
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pci_ahci_init(struct pci_devinst *pi, nvlist_t *nvl)
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{
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char bident[sizeof("XXX:XXX:XXX")];
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char node_name[sizeof("XX")];
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@ -2668,7 +2666,7 @@ done:
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}
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static int
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pci_ahci_pause(struct vmctx *ctx __unused, struct pci_devinst *pi)
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pci_ahci_pause(struct pci_devinst *pi)
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{
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struct pci_ahci_softc *sc;
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struct blockif_ctxt *bctxt;
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@ -2688,7 +2686,7 @@ pci_ahci_pause(struct vmctx *ctx __unused, struct pci_devinst *pi)
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}
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static int
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pci_ahci_resume(struct vmctx *ctx __unused, struct pci_devinst *pi)
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pci_ahci_resume(struct pci_devinst *pi)
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{
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struct pci_ahci_softc *sc;
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struct blockif_ctxt *bctxt;
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@ -2112,8 +2112,7 @@ e82545_read_register(struct e82545_softc *sc, uint32_t offset)
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}
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static void
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e82545_write(struct vmctx *ctx __unused,
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struct pci_devinst *pi, int baridx, uint64_t offset, int size,
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e82545_write(struct pci_devinst *pi, int baridx, uint64_t offset, int size,
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uint64_t value)
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{
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struct e82545_softc *sc;
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@ -2163,8 +2162,7 @@ e82545_write(struct vmctx *ctx __unused,
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}
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static uint64_t
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e82545_read(struct vmctx *ctx __unused,
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struct pci_devinst *pi, int baridx, uint64_t offset, int size)
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e82545_read(struct pci_devinst *pi, int baridx, uint64_t offset, int size)
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{
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struct e82545_softc *sc;
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uint64_t retval;
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@ -2307,7 +2305,7 @@ e82545_reset(struct e82545_softc *sc, int drvr)
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}
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static int
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e82545_init(struct vmctx *ctx, struct pci_devinst *pi, nvlist_t *nvl)
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e82545_init(struct pci_devinst *pi, nvlist_t *nvl)
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{
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char nstr[80];
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struct e82545_softc *sc;
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@ -2319,7 +2317,7 @@ e82545_init(struct vmctx *ctx, struct pci_devinst *pi, nvlist_t *nvl)
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pi->pi_arg = sc;
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sc->esc_pi = pi;
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sc->esc_ctx = ctx;
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sc->esc_ctx = pi->pi_vmctx;
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pthread_mutex_init(&sc->esc_mtx, NULL);
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pthread_cond_init(&sc->esc_rx_cond, NULL);
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@ -140,8 +140,8 @@ SYSRES_MEM(PCI_EMUL_ECFG_BASE, PCI_EMUL_ECFG_SIZE);
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static struct pci_devemu *pci_emul_finddev(const char *name);
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static void pci_lintr_route(struct pci_devinst *pi);
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static void pci_lintr_update(struct pci_devinst *pi);
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static void pci_cfgrw(struct vmctx *ctx, int in, int bus, int slot,
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int func, int coff, int bytes, uint32_t *val);
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static void pci_cfgrw(int in, int bus, int slot, int func, int coff,
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int bytes, uint32_t *val);
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static __inline void
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CFGWRITE(struct pci_devinst *pi, int coff, uint32_t val, int bytes)
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@ -447,7 +447,7 @@ pci_msix_pba_bar(struct pci_devinst *pi)
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}
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static int
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pci_emul_io_handler(struct vmctx *ctx, int in, int port,
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pci_emul_io_handler(struct vmctx *ctx __unused, int in, int port,
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int bytes, uint32_t *eax, void *arg)
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{
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struct pci_devinst *pdi = arg;
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@ -464,10 +464,10 @@ pci_emul_io_handler(struct vmctx *ctx, int in, int port,
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pdi->pi_bar[i].addr + pdi->pi_bar[i].size) {
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offset = port - pdi->pi_bar[i].addr;
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if (in)
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*eax = (*pe->pe_barread)(ctx, pdi, i,
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*eax = (*pe->pe_barread)(pdi, i,
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offset, bytes);
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else
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(*pe->pe_barwrite)(ctx, pdi, i, offset,
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(*pe->pe_barwrite)(pdi, i, offset,
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bytes, *eax);
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return (0);
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}
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@ -476,7 +476,7 @@ pci_emul_io_handler(struct vmctx *ctx, int in, int port,
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}
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static int
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pci_emul_mem_handler(struct vmctx *ctx, int vcpu __unused, int dir,
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pci_emul_mem_handler(struct vmctx *ctx __unused, int vcpu __unused, int dir,
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uint64_t addr, int size, uint64_t *val, void *arg1, long arg2)
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{
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struct pci_devinst *pdi = arg1;
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@ -494,22 +494,22 @@ pci_emul_mem_handler(struct vmctx *ctx, int vcpu __unused, int dir,
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if (dir == MEM_F_WRITE) {
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if (size == 8) {
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(*pe->pe_barwrite)(ctx, pdi, bidx, offset,
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(*pe->pe_barwrite)(pdi, bidx, offset,
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4, *val & 0xffffffff);
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(*pe->pe_barwrite)(ctx, pdi, bidx, offset + 4,
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(*pe->pe_barwrite)(pdi, bidx, offset + 4,
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4, *val >> 32);
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} else {
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(*pe->pe_barwrite)(ctx, pdi, bidx, offset,
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(*pe->pe_barwrite)(pdi, bidx, offset,
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size, *val);
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}
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} else {
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if (size == 8) {
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*val = (*pe->pe_barread)(ctx, pdi, bidx,
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*val = (*pe->pe_barread)(pdi, bidx,
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offset, 4);
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*val |= (*pe->pe_barread)(ctx, pdi, bidx,
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*val |= (*pe->pe_barread)(pdi, bidx,
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offset + 4, 4) << 32;
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} else {
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*val = (*pe->pe_barread)(ctx, pdi, bidx,
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*val = (*pe->pe_barread)(pdi, bidx,
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offset, size);
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}
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}
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@ -563,7 +563,7 @@ modify_bar_registration(struct pci_devinst *pi, int idx, int registration)
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} else
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error = unregister_inout(&iop);
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if (pe->pe_baraddr != NULL)
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(*pe->pe_baraddr)(pi->pi_vmctx, pi, idx, registration,
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(*pe->pe_baraddr)(pi, idx, registration,
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pi->pi_bar[idx].addr);
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break;
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case PCIBAR_MEM32:
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@ -581,13 +581,13 @@ modify_bar_registration(struct pci_devinst *pi, int idx, int registration)
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} else
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error = unregister_mem(&mr);
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if (pe->pe_baraddr != NULL)
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(*pe->pe_baraddr)(pi->pi_vmctx, pi, idx, registration,
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(*pe->pe_baraddr)(pi, idx, registration,
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pi->pi_bar[idx].addr);
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break;
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case PCIBAR_ROM:
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error = 0;
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if (pe->pe_baraddr != NULL)
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(*pe->pe_baraddr)(pi->pi_vmctx, pi, idx, registration,
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(*pe->pe_baraddr)(pi, idx, registration,
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pi->pi_bar[idx].addr);
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break;
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default:
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@ -993,7 +993,7 @@ pci_emul_init(struct vmctx *ctx, struct pci_devemu *pde, int bus, int slot,
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pci_set_cfgdata8(pdi, PCIR_COMMAND, PCIM_CMD_BUSMASTEREN);
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err = (*pde->pe_init)(ctx, pdi, fi->fi_config);
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err = (*pde->pe_init)(pdi, fi->fi_config);
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if (err == 0)
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fi->fi_devi = pdi;
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else
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@ -1294,7 +1294,7 @@ pci_emul_fallback_handler(struct vmctx *ctx __unused, int vcpu __unused,
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}
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static int
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pci_emul_ecfg_handler(struct vmctx *ctx, int vcpu __unused, int dir,
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pci_emul_ecfg_handler(struct vmctx *ctx __unused, int vcpu __unused, int dir,
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uint64_t addr, int bytes, uint64_t *val, void *arg1 __unused,
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long arg2 __unused)
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{
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@ -1307,7 +1307,7 @@ pci_emul_ecfg_handler(struct vmctx *ctx, int vcpu __unused, int dir,
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in = (dir == MEM_F_READ);
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if (in)
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*val = ~0UL;
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pci_cfgrw(ctx, in, bus, slot, func, coff, bytes, (uint32_t *)val);
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pci_cfgrw(in, bus, slot, func, coff, bytes, (uint32_t *)val);
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return (0);
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}
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@ -2054,8 +2054,8 @@ pci_emul_cmdsts_write(struct pci_devinst *pi, int coff, uint32_t new, int bytes)
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}
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static void
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pci_cfgrw(struct vmctx *ctx, int in, int bus, int slot, int func,
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int coff, int bytes, uint32_t *eax)
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pci_cfgrw(int in, int bus, int slot, int func, int coff, int bytes,
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uint32_t *eax)
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{
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struct businfo *bi;
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struct slotinfo *si;
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@ -2108,7 +2108,7 @@ pci_cfgrw(struct vmctx *ctx, int in, int bus, int slot, int func,
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if (in) {
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/* Let the device emulation override the default handler */
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if (pe->pe_cfgread != NULL) {
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needcfg = pe->pe_cfgread(ctx, pi, coff, bytes, eax);
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needcfg = pe->pe_cfgread(pi, coff, bytes, eax);
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} else {
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needcfg = 1;
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}
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@ -2120,7 +2120,7 @@ pci_cfgrw(struct vmctx *ctx, int in, int bus, int slot, int func,
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} else {
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/* Let the device emulation override the default handler */
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if (pe->pe_cfgwrite != NULL &&
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(*pe->pe_cfgwrite)(ctx, pi, coff, bytes, *eax) == 0)
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(*pe->pe_cfgwrite)(pi, coff, bytes, *eax) == 0)
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return;
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/*
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@ -2247,7 +2247,7 @@ pci_emul_cfgaddr(struct vmctx *ctx __unused, int in,
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INOUT_PORT(pci_cfgaddr, CONF1_ADDR_PORT, IOPORT_F_INOUT, pci_emul_cfgaddr);
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static int
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pci_emul_cfgdata(struct vmctx *ctx, int in, int port,
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pci_emul_cfgdata(struct vmctx *ctx __unused, int in, int port,
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int bytes, uint32_t *eax, void *arg __unused)
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{
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int coff;
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@ -2256,8 +2256,7 @@ pci_emul_cfgdata(struct vmctx *ctx, int in, int port,
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coff = cfgoff + (port - CONF1_DATA_PORT);
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if (cfgenable) {
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pci_cfgrw(ctx, in, cfgbus, cfgslot, cfgfunc, coff, bytes,
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eax);
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pci_cfgrw(in, cfgbus, cfgslot, cfgfunc, coff, bytes, eax);
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} else {
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/* Ignore accesses to cfgdata if not enabled by cfgaddr */
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if (in)
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@ -2395,7 +2394,7 @@ pci_snapshot(struct vm_snapshot_meta *meta)
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}
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int
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pci_pause(struct vmctx *ctx, const char *dev_name)
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pci_pause(const char *dev_name)
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{
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struct pci_devemu *pde;
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struct pci_devinst *pdi;
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@ -2420,11 +2419,11 @@ pci_pause(struct vmctx *ctx, const char *dev_name)
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return (0);
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}
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return (*pde->pe_pause)(ctx, pdi);
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return (*pde->pe_pause)(pdi);
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}
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int
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pci_resume(struct vmctx *ctx, const char *dev_name)
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pci_resume(const char *dev_name)
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{
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struct pci_devemu *pde;
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struct pci_devinst *pdi;
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@ -2449,7 +2448,7 @@ pci_resume(struct vmctx *ctx, const char *dev_name)
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return (0);
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}
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return (*pde->pe_resume)(ctx, pdi);
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return (*pde->pe_resume)(pdi);
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}
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#endif
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@ -2469,8 +2468,7 @@ struct pci_emul_dsoftc {
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#define PCI_EMUL_MSIX_MSGS 16
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static int
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pci_emul_dinit(struct vmctx *ctx __unused, struct pci_devinst *pi,
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nvlist_t *nvl __unused)
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pci_emul_dinit(struct pci_devinst *pi, nvlist_t *nvl __unused)
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{
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int error;
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struct pci_emul_dsoftc *sc;
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@ -2499,8 +2497,7 @@ pci_emul_dinit(struct vmctx *ctx __unused, struct pci_devinst *pi,
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}
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static void
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pci_emul_diow(struct vmctx *ctx __unused,
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struct pci_devinst *pi, int baridx, uint64_t offset, int size,
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pci_emul_diow(struct pci_devinst *pi, int baridx, uint64_t offset, int size,
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uint64_t value)
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{
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int i;
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@ -2567,8 +2564,7 @@ pci_emul_diow(struct vmctx *ctx __unused,
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}
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static uint64_t
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pci_emul_dior(struct vmctx *ctx __unused,
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struct pci_devinst *pi, int baridx, uint64_t offset, int size)
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pci_emul_dior(struct pci_devinst *pi, int baridx, uint64_t offset, int size)
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{
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struct pci_emul_dsoftc *sc = pi->pi_arg;
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uint32_t value;
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@ -54,8 +54,7 @@ struct pci_devemu {
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const char *pe_emu; /* Name of device emulation */
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/* instance creation */
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int (*pe_init)(struct vmctx *, struct pci_devinst *,
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nvlist_t *);
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int (*pe_init)(struct pci_devinst *, nvlist_t *);
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int (*pe_legacy_config)(nvlist_t *, const char *);
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const char *pe_alias;
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@ -63,28 +62,24 @@ struct pci_devemu {
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void (*pe_write_dsdt)(struct pci_devinst *);
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/* config space read/write callbacks */
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int (*pe_cfgwrite)(struct vmctx *ctx,
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struct pci_devinst *pi, int offset,
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int (*pe_cfgwrite)(struct pci_devinst *pi, int offset,
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int bytes, uint32_t val);
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int (*pe_cfgread)(struct vmctx *ctx,
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struct pci_devinst *pi, int offset,
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int (*pe_cfgread)(struct pci_devinst *pi, int offset,
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int bytes, uint32_t *retval);
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/* BAR read/write callbacks */
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void (*pe_barwrite)(struct vmctx *ctx,
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struct pci_devinst *pi, int baridx,
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void (*pe_barwrite)(struct pci_devinst *pi, int baridx,
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uint64_t offset, int size, uint64_t value);
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uint64_t (*pe_barread)(struct vmctx *ctx,
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struct pci_devinst *pi, int baridx,
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uint64_t (*pe_barread)(struct pci_devinst *pi, int baridx,
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uint64_t offset, int size);
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void (*pe_baraddr)(struct vmctx *ctx, struct pci_devinst *pi,
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void (*pe_baraddr)(struct pci_devinst *pi,
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int baridx, int enabled, uint64_t address);
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/* Save/restore device state */
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int (*pe_snapshot)(struct vm_snapshot_meta *meta);
|
||||
int (*pe_pause)(struct vmctx *ctx, struct pci_devinst *pi);
|
||||
int (*pe_resume)(struct vmctx *ctx, struct pci_devinst *pi);
|
||||
int (*pe_pause)(struct pci_devinst *pi);
|
||||
int (*pe_resume)(struct pci_devinst *pi);
|
||||
|
||||
};
|
||||
#define PCI_EMUL_SET(x) DATA_SET(pci_devemu_set, x);
|
||||
|
|
@ -266,8 +261,8 @@ uint64_t pci_ecfg_base(void);
|
|||
int pci_bus_configured(int bus);
|
||||
#ifdef BHYVE_SNAPSHOT
|
||||
int pci_snapshot(struct vm_snapshot_meta *meta);
|
||||
int pci_pause(struct vmctx *ctx, const char *dev_name);
|
||||
int pci_resume(struct vmctx *ctx, const char *dev_name);
|
||||
int pci_pause(const char *dev_name);
|
||||
int pci_resume(const char *dev_name);
|
||||
#endif
|
||||
|
||||
static __inline void
|
||||
|
|
|
|||
|
|
@ -117,8 +117,7 @@ static struct pci_fbuf_softc *fbuf_sc;
|
|||
#define PCI_FBUF_MSI_MSGS 4
|
||||
|
||||
static void
|
||||
pci_fbuf_write(struct vmctx *ctx __unused,
|
||||
struct pci_devinst *pi, int baridx, uint64_t offset, int size,
|
||||
pci_fbuf_write(struct pci_devinst *pi, int baridx, uint64_t offset, int size,
|
||||
uint64_t value)
|
||||
{
|
||||
struct pci_fbuf_softc *sc;
|
||||
|
|
@ -172,8 +171,7 @@ pci_fbuf_write(struct vmctx *ctx __unused,
|
|||
}
|
||||
|
||||
static uint64_t
|
||||
pci_fbuf_read(struct vmctx *ctx __unused,
|
||||
struct pci_devinst *pi, int baridx, uint64_t offset, int size)
|
||||
pci_fbuf_read(struct pci_devinst *pi, int baridx, uint64_t offset, int size)
|
||||
{
|
||||
struct pci_fbuf_softc *sc;
|
||||
uint8_t *p;
|
||||
|
|
@ -218,8 +216,8 @@ pci_fbuf_read(struct vmctx *ctx __unused,
|
|||
}
|
||||
|
||||
static void
|
||||
pci_fbuf_baraddr(struct vmctx *ctx, struct pci_devinst *pi, int baridx,
|
||||
int enabled, uint64_t address)
|
||||
pci_fbuf_baraddr(struct pci_devinst *pi, int baridx, int enabled,
|
||||
uint64_t address)
|
||||
{
|
||||
struct pci_fbuf_softc *sc;
|
||||
int prot;
|
||||
|
|
@ -229,12 +227,13 @@ pci_fbuf_baraddr(struct vmctx *ctx, struct pci_devinst *pi, int baridx,
|
|||
|
||||
sc = pi->pi_arg;
|
||||
if (!enabled) {
|
||||
if (vm_munmap_memseg(ctx, sc->fbaddr, FB_SIZE) != 0)
|
||||
if (vm_munmap_memseg(pi->pi_vmctx, sc->fbaddr, FB_SIZE) != 0)
|
||||
EPRINTLN("pci_fbuf: munmap_memseg failed");
|
||||
sc->fbaddr = 0;
|
||||
} else {
|
||||
prot = PROT_READ | PROT_WRITE;
|
||||
if (vm_mmap_memseg(ctx, address, VM_FRAMEBUFFER, 0, FB_SIZE, prot) != 0)
|
||||
if (vm_mmap_memseg(pi->pi_vmctx, address, VM_FRAMEBUFFER, 0,
|
||||
FB_SIZE, prot) != 0)
|
||||
EPRINTLN("pci_fbuf: mmap_memseg failed");
|
||||
sc->fbaddr = address;
|
||||
}
|
||||
|
|
@ -371,7 +370,7 @@ pci_fbuf_render(struct bhyvegc *gc, void *arg)
|
|||
}
|
||||
|
||||
static int
|
||||
pci_fbuf_init(struct vmctx *ctx, struct pci_devinst *pi, nvlist_t *nvl)
|
||||
pci_fbuf_init(struct pci_devinst *pi, nvlist_t *nvl)
|
||||
{
|
||||
int error;
|
||||
struct pci_fbuf_softc *sc;
|
||||
|
|
@ -391,8 +390,8 @@ pci_fbuf_init(struct vmctx *ctx, struct pci_devinst *pi, nvlist_t *nvl)
|
|||
pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_DISPLAY);
|
||||
pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_DISPLAY_VGA);
|
||||
|
||||
sc->fb_base = vm_create_devmem(
|
||||
ctx, VM_FRAMEBUFFER, "framebuffer", FB_SIZE);
|
||||
sc->fb_base = vm_create_devmem(pi->pi_vmctx, VM_FRAMEBUFFER,
|
||||
"framebuffer", FB_SIZE);
|
||||
if (sc->fb_base == MAP_FAILED) {
|
||||
error = -1;
|
||||
goto done;
|
||||
|
|
|
|||
|
|
@ -209,11 +209,11 @@ static uint64_t hda_get_clock_ns(void);
|
|||
/*
|
||||
* PCI HDA function declarations
|
||||
*/
|
||||
static int pci_hda_init(struct vmctx *ctx, struct pci_devinst *pi, nvlist_t *nvl);
|
||||
static void pci_hda_write(struct vmctx *ctx, struct pci_devinst *pi,
|
||||
int baridx, uint64_t offset, int size, uint64_t value);
|
||||
static uint64_t pci_hda_read(struct vmctx *ctx, struct pci_devinst *pi,
|
||||
int baridx, uint64_t offset, int size);
|
||||
static int pci_hda_init(struct pci_devinst *pi, nvlist_t *nvl);
|
||||
static void pci_hda_write(struct pci_devinst *pi, int baridx, uint64_t offset,
|
||||
int size, uint64_t value);
|
||||
static uint64_t pci_hda_read(struct pci_devinst *pi, int baridx,
|
||||
uint64_t offset, int size);
|
||||
/*
|
||||
* HDA global data
|
||||
*/
|
||||
|
|
@ -1223,11 +1223,10 @@ static uint64_t hda_get_clock_ns(void)
|
|||
* PCI HDA function definitions
|
||||
*/
|
||||
static int
|
||||
pci_hda_init(struct vmctx *ctx, struct pci_devinst *pi, nvlist_t *nvl)
|
||||
pci_hda_init(struct pci_devinst *pi, nvlist_t *nvl)
|
||||
{
|
||||
struct hda_softc *sc = NULL;
|
||||
|
||||
assert(ctx != NULL);
|
||||
assert(pi != NULL);
|
||||
|
||||
pci_set_cfgdata16(pi, PCIR_VENDOR, INTEL_VENDORID);
|
||||
|
|
@ -1256,8 +1255,7 @@ pci_hda_init(struct vmctx *ctx, struct pci_devinst *pi, nvlist_t *nvl)
|
|||
}
|
||||
|
||||
static void
|
||||
pci_hda_write(struct vmctx *ctx __unused,
|
||||
struct pci_devinst *pi, int baridx, uint64_t offset, int size,
|
||||
pci_hda_write(struct pci_devinst *pi, int baridx, uint64_t offset, int size,
|
||||
uint64_t value)
|
||||
{
|
||||
struct hda_softc *sc = pi->pi_arg;
|
||||
|
|
@ -1274,8 +1272,7 @@ pci_hda_write(struct vmctx *ctx __unused,
|
|||
}
|
||||
|
||||
static uint64_t
|
||||
pci_hda_read(struct vmctx *ctx __unused,
|
||||
struct pci_devinst *pi, int baridx, uint64_t offset, int size)
|
||||
pci_hda_read(struct pci_devinst *pi, int baridx, uint64_t offset, int size)
|
||||
{
|
||||
struct hda_softc *sc = pi->pi_arg;
|
||||
uint64_t value = 0;
|
||||
|
|
|
|||
|
|
@ -37,8 +37,7 @@ __FBSDID("$FreeBSD$");
|
|||
#include "pci_emul.h"
|
||||
|
||||
static int
|
||||
pci_hostbridge_init(struct vmctx *ctx __unused, struct pci_devinst *pi,
|
||||
nvlist_t *nvl)
|
||||
pci_hostbridge_init(struct pci_devinst *pi, nvlist_t *nvl)
|
||||
{
|
||||
const char *value;
|
||||
u_int vendor, device;
|
||||
|
|
|
|||
|
|
@ -398,8 +398,7 @@ pci_lpc_uart_dsdt(void)
|
|||
LPC_DSDT(pci_lpc_uart_dsdt);
|
||||
|
||||
static int
|
||||
pci_lpc_cfgwrite(struct vmctx *ctx, struct pci_devinst *pi,
|
||||
int coff, int bytes, uint32_t val)
|
||||
pci_lpc_cfgwrite(struct pci_devinst *pi, int coff, int bytes, uint32_t val)
|
||||
{
|
||||
int pirq_pin;
|
||||
|
||||
|
|
@ -410,7 +409,7 @@ pci_lpc_cfgwrite(struct vmctx *ctx, struct pci_devinst *pi,
|
|||
if (coff >= 0x68 && coff <= 0x6b)
|
||||
pirq_pin = coff - 0x68 + 5;
|
||||
if (pirq_pin != 0) {
|
||||
pirq_write(ctx, pirq_pin, val);
|
||||
pirq_write(pi->pi_vmctx, pirq_pin, val);
|
||||
pci_set_cfgdata8(pi, coff, pirq_read(pirq_pin));
|
||||
return (0);
|
||||
}
|
||||
|
|
@ -419,16 +418,14 @@ pci_lpc_cfgwrite(struct vmctx *ctx, struct pci_devinst *pi,
|
|||
}
|
||||
|
||||
static void
|
||||
pci_lpc_write(struct vmctx *ctx __unused,
|
||||
struct pci_devinst *pi __unused, int baridx __unused,
|
||||
pci_lpc_write(struct pci_devinst *pi __unused, int baridx __unused,
|
||||
uint64_t offset __unused, int size __unused, uint64_t value __unused)
|
||||
{
|
||||
}
|
||||
|
||||
static uint64_t
|
||||
pci_lpc_read(struct vmctx *ctx __unused,
|
||||
struct pci_devinst *pi __unused, int baridx __unused, uint64_t offset __unused,
|
||||
int size __unused)
|
||||
pci_lpc_read(struct pci_devinst *pi __unused, int baridx __unused,
|
||||
uint64_t offset __unused, int size __unused)
|
||||
{
|
||||
return (0);
|
||||
}
|
||||
|
|
@ -437,7 +434,7 @@ pci_lpc_read(struct vmctx *ctx __unused,
|
|||
#define LPC_VENDOR 0x8086
|
||||
|
||||
static int
|
||||
pci_lpc_init(struct vmctx *ctx, struct pci_devinst *pi, nvlist_t *nvl __unused)
|
||||
pci_lpc_init(struct pci_devinst *pi, nvlist_t *nvl __unused)
|
||||
{
|
||||
/*
|
||||
* Do not allow more than one LPC bridge to be configured.
|
||||
|
|
@ -457,7 +454,7 @@ pci_lpc_init(struct vmctx *ctx, struct pci_devinst *pi, nvlist_t *nvl __unused)
|
|||
return (-1);
|
||||
}
|
||||
|
||||
if (lpc_init(ctx) != 0)
|
||||
if (lpc_init(pi->pi_vmctx) != 0)
|
||||
return (-1);
|
||||
|
||||
/* initialize config space */
|
||||
|
|
|
|||
|
|
@ -1100,7 +1100,7 @@ pci_nvme_reset(struct pci_nvme_softc *sc)
|
|||
}
|
||||
|
||||
static int
|
||||
pci_nvme_init_controller(struct vmctx *ctx, struct pci_nvme_softc *sc)
|
||||
pci_nvme_init_controller(struct pci_nvme_softc *sc)
|
||||
{
|
||||
uint16_t acqs, asqs;
|
||||
|
||||
|
|
@ -1119,8 +1119,8 @@ pci_nvme_init_controller(struct vmctx *ctx, struct pci_nvme_softc *sc)
|
|||
return (-1);
|
||||
}
|
||||
sc->submit_queues[0].size = asqs;
|
||||
sc->submit_queues[0].qbase = vm_map_gpa(ctx, sc->regs.asq,
|
||||
sizeof(struct nvme_command) * asqs);
|
||||
sc->submit_queues[0].qbase = vm_map_gpa(sc->nsc_pi->pi_vmctx,
|
||||
sc->regs.asq, sizeof(struct nvme_command) * asqs);
|
||||
if (sc->submit_queues[0].qbase == NULL) {
|
||||
EPRINTLN("%s: ASQ vm_map_gpa(%lx) failed", __func__,
|
||||
sc->regs.asq);
|
||||
|
|
@ -1140,8 +1140,8 @@ pci_nvme_init_controller(struct vmctx *ctx, struct pci_nvme_softc *sc)
|
|||
return (-1);
|
||||
}
|
||||
sc->compl_queues[0].size = acqs;
|
||||
sc->compl_queues[0].qbase = vm_map_gpa(ctx, sc->regs.acq,
|
||||
sizeof(struct nvme_completion) * acqs);
|
||||
sc->compl_queues[0].qbase = vm_map_gpa(sc->nsc_pi->pi_vmctx,
|
||||
sc->regs.acq, sizeof(struct nvme_completion) * acqs);
|
||||
if (sc->compl_queues[0].qbase == NULL) {
|
||||
EPRINTLN("%s: ACQ vm_map_gpa(%lx) failed", __func__,
|
||||
sc->regs.acq);
|
||||
|
|
@ -2930,8 +2930,8 @@ pci_nvme_bar0_reg_dumps(const char *func, uint64_t offset, int iswrite)
|
|||
}
|
||||
|
||||
static void
|
||||
pci_nvme_write_bar_0(struct vmctx *ctx, struct pci_nvme_softc* sc,
|
||||
uint64_t offset, int size, uint64_t value)
|
||||
pci_nvme_write_bar_0(struct pci_nvme_softc *sc, uint64_t offset, int size,
|
||||
uint64_t value)
|
||||
{
|
||||
uint32_t ccreg;
|
||||
|
||||
|
|
@ -3014,7 +3014,7 @@ pci_nvme_write_bar_0(struct vmctx *ctx, struct pci_nvme_softc* sc,
|
|||
/* transition 1-> causes controller reset */
|
||||
pci_nvme_reset_locked(sc);
|
||||
else
|
||||
pci_nvme_init_controller(ctx, sc);
|
||||
pci_nvme_init_controller(sc);
|
||||
}
|
||||
|
||||
/* Insert the iocqes, iosqes and en bits from the write */
|
||||
|
|
@ -3062,8 +3062,8 @@ pci_nvme_write_bar_0(struct vmctx *ctx, struct pci_nvme_softc* sc,
|
|||
}
|
||||
|
||||
static void
|
||||
pci_nvme_write(struct vmctx *ctx, struct pci_devinst *pi,
|
||||
int baridx, uint64_t offset, int size, uint64_t value)
|
||||
pci_nvme_write(struct pci_devinst *pi, int baridx, uint64_t offset, int size,
|
||||
uint64_t value)
|
||||
{
|
||||
struct pci_nvme_softc* sc = pi->pi_arg;
|
||||
|
||||
|
|
@ -3078,7 +3078,7 @@ pci_nvme_write(struct vmctx *ctx, struct pci_devinst *pi,
|
|||
|
||||
switch (baridx) {
|
||||
case 0:
|
||||
pci_nvme_write_bar_0(ctx, sc, offset, size, value);
|
||||
pci_nvme_write_bar_0(sc, offset, size, value);
|
||||
break;
|
||||
|
||||
default:
|
||||
|
|
@ -3125,8 +3125,7 @@ static uint64_t pci_nvme_read_bar_0(struct pci_nvme_softc* sc,
|
|||
|
||||
|
||||
static uint64_t
|
||||
pci_nvme_read(struct vmctx *ctx __unused,
|
||||
struct pci_devinst *pi, int baridx, uint64_t offset, int size)
|
||||
pci_nvme_read(struct pci_devinst *pi, int baridx, uint64_t offset, int size)
|
||||
{
|
||||
struct pci_nvme_softc* sc = pi->pi_arg;
|
||||
|
||||
|
|
@ -3276,7 +3275,7 @@ pci_nvme_resized(struct blockif_ctxt *bctxt __unused, void *arg,
|
|||
}
|
||||
|
||||
static int
|
||||
pci_nvme_init(struct vmctx *ctx __unused, struct pci_devinst *pi, nvlist_t *nvl)
|
||||
pci_nvme_init(struct pci_devinst *pi, nvlist_t *nvl)
|
||||
{
|
||||
struct pci_nvme_softc *sc;
|
||||
uint32_t pci_membar_sz;
|
||||
|
|
|
|||
|
|
@ -386,8 +386,8 @@ msix_table_read(struct passthru_softc *sc, uint64_t offset, int size)
|
|||
}
|
||||
|
||||
static void
|
||||
msix_table_write(struct vmctx *ctx, struct passthru_softc *sc,
|
||||
uint64_t offset, int size, uint64_t data)
|
||||
msix_table_write(struct passthru_softc *sc, uint64_t offset, int size,
|
||||
uint64_t data)
|
||||
{
|
||||
struct pci_devinst *pi;
|
||||
struct msix_table_entry *entry;
|
||||
|
|
@ -445,7 +445,7 @@ msix_table_write(struct vmctx *ctx, struct passthru_softc *sc,
|
|||
/* If the entry is masked, don't set it up */
|
||||
if ((entry->vector_control & PCIM_MSIX_VCTRL_MASK) == 0 ||
|
||||
(vector_control & PCIM_MSIX_VCTRL_MASK) == 0) {
|
||||
(void)vm_setup_pptdev_msix(ctx, 0,
|
||||
(void)vm_setup_pptdev_msix(sc->psc_pi->pi_vmctx, 0,
|
||||
sc->psc_sel.pc_bus, sc->psc_sel.pc_dev,
|
||||
sc->psc_sel.pc_func, index, entry->addr,
|
||||
entry->msg_data, entry->vector_control);
|
||||
|
|
@ -454,7 +454,7 @@ msix_table_write(struct vmctx *ctx, struct passthru_softc *sc,
|
|||
}
|
||||
|
||||
static int
|
||||
init_msix_table(struct vmctx *ctx __unused, struct passthru_softc *sc)
|
||||
init_msix_table(struct passthru_softc *sc)
|
||||
{
|
||||
struct pci_devinst *pi = sc->psc_pi;
|
||||
struct pci_bar_mmap pbm;
|
||||
|
|
@ -515,7 +515,7 @@ init_msix_table(struct vmctx *ctx __unused, struct passthru_softc *sc)
|
|||
}
|
||||
|
||||
static int
|
||||
cfginitbar(struct vmctx *ctx __unused, struct passthru_softc *sc)
|
||||
cfginitbar(struct passthru_softc *sc)
|
||||
{
|
||||
int i, error;
|
||||
struct pci_devinst *pi;
|
||||
|
|
@ -596,7 +596,7 @@ cfginitbar(struct vmctx *ctx __unused, struct passthru_softc *sc)
|
|||
}
|
||||
|
||||
static int
|
||||
cfginit(struct vmctx *ctx, struct pci_devinst *pi, int bus, int slot, int func)
|
||||
cfginit(struct pci_devinst *pi, int bus, int slot, int func)
|
||||
{
|
||||
int error;
|
||||
struct passthru_softc *sc;
|
||||
|
|
@ -615,7 +615,7 @@ cfginit(struct vmctx *ctx, struct pci_devinst *pi, int bus, int slot, int func)
|
|||
goto done;
|
||||
}
|
||||
|
||||
if (cfginitbar(ctx, sc) != 0) {
|
||||
if (cfginitbar(sc) != 0) {
|
||||
warnx("failed to initialize BARs for PCI %d/%d/%d",
|
||||
bus, slot, func);
|
||||
goto done;
|
||||
|
|
@ -629,7 +629,7 @@ cfginit(struct vmctx *ctx, struct pci_devinst *pi, int bus, int slot, int func)
|
|||
* a BAR was enabled, as otherwise the PCIOCBARMMAP might fail on us.
|
||||
*/
|
||||
if (pci_msix_table_bar(pi) >= 0) {
|
||||
error = init_msix_table(ctx, sc);
|
||||
error = init_msix_table(sc);
|
||||
if (error != 0) {
|
||||
warnx(
|
||||
"failed to initialize MSI-X table for PCI %d/%d/%d: %d",
|
||||
|
|
@ -682,8 +682,7 @@ passthru_legacy_config(nvlist_t *nvl, const char *opts)
|
|||
}
|
||||
|
||||
static int
|
||||
passthru_init_rom(struct vmctx *const ctx __unused,
|
||||
struct passthru_softc *const sc, const char *const romfile)
|
||||
passthru_init_rom(struct passthru_softc *const sc, const char *const romfile)
|
||||
{
|
||||
if (romfile == NULL) {
|
||||
return (0);
|
||||
|
|
@ -799,7 +798,7 @@ passthru_lookup_pptdev(const char *name, int *bus, int *slot, int *func)
|
|||
}
|
||||
|
||||
static int
|
||||
passthru_init(struct vmctx *ctx, struct pci_devinst *pi, nvlist_t *nvl)
|
||||
passthru_init(struct pci_devinst *pi, nvlist_t *nvl)
|
||||
{
|
||||
int bus, slot, func, error, memflags;
|
||||
struct passthru_softc *sc;
|
||||
|
|
@ -808,7 +807,7 @@ passthru_init(struct vmctx *ctx, struct pci_devinst *pi, nvlist_t *nvl)
|
|||
sc = NULL;
|
||||
error = 1;
|
||||
|
||||
memflags = vm_get_memflags(ctx);
|
||||
memflags = vm_get_memflags(pi->pi_vmctx);
|
||||
if (!(memflags & VM_MEM_F_WIRED)) {
|
||||
warnx("passthru requires guest memory to be wired");
|
||||
return (error);
|
||||
|
|
@ -837,7 +836,7 @@ passthru_init(struct vmctx *ctx, struct pci_devinst *pi, nvlist_t *nvl)
|
|||
GET_INT_CONFIG(func, "func");
|
||||
}
|
||||
|
||||
if (vm_assign_pptdev(ctx, bus, slot, func) != 0) {
|
||||
if (vm_assign_pptdev(pi->pi_vmctx, bus, slot, func) != 0) {
|
||||
warnx("PCI device at %d/%d/%d is not using the ppt(4) driver",
|
||||
bus, slot, func);
|
||||
goto done;
|
||||
|
|
@ -849,11 +848,11 @@ passthru_init(struct vmctx *ctx, struct pci_devinst *pi, nvlist_t *nvl)
|
|||
sc->psc_pi = pi;
|
||||
|
||||
/* initialize config space */
|
||||
if ((error = cfginit(ctx, pi, bus, slot, func)) != 0)
|
||||
if ((error = cfginit(pi, bus, slot, func)) != 0)
|
||||
goto done;
|
||||
|
||||
/* initialize ROM */
|
||||
if ((error = passthru_init_rom(ctx, sc,
|
||||
if ((error = passthru_init_rom(sc,
|
||||
get_config_value_node(nvl, "rom"))) != 0)
|
||||
goto done;
|
||||
|
||||
|
|
@ -861,7 +860,7 @@ passthru_init(struct vmctx *ctx, struct pci_devinst *pi, nvlist_t *nvl)
|
|||
done:
|
||||
if (error) {
|
||||
free(sc);
|
||||
vm_unassign_pptdev(ctx, bus, slot, func);
|
||||
vm_unassign_pptdev(pi->pi_vmctx, bus, slot, func);
|
||||
}
|
||||
return (error);
|
||||
}
|
||||
|
|
@ -903,8 +902,7 @@ msixcap_access(struct passthru_softc *sc, int coff)
|
|||
}
|
||||
|
||||
static int
|
||||
passthru_cfgread(struct vmctx *ctx __unused, struct pci_devinst *pi, int coff,
|
||||
int bytes, uint32_t *rv)
|
||||
passthru_cfgread(struct pci_devinst *pi, int coff, int bytes, uint32_t *rv)
|
||||
{
|
||||
struct passthru_softc *sc;
|
||||
|
||||
|
|
@ -948,8 +946,7 @@ passthru_cfgread(struct vmctx *ctx __unused, struct pci_devinst *pi, int coff,
|
|||
}
|
||||
|
||||
static int
|
||||
passthru_cfgwrite(struct vmctx *ctx, struct pci_devinst *pi, int coff,
|
||||
int bytes, uint32_t val)
|
||||
passthru_cfgwrite(struct pci_devinst *pi, int coff, int bytes, uint32_t val)
|
||||
{
|
||||
int error, msix_table_entries, i;
|
||||
struct passthru_softc *sc;
|
||||
|
|
@ -969,7 +966,7 @@ passthru_cfgwrite(struct vmctx *ctx, struct pci_devinst *pi, int coff,
|
|||
if (msicap_access(sc, coff)) {
|
||||
pci_emul_capwrite(pi, coff, bytes, val, sc->psc_msi.capoff,
|
||||
PCIY_MSI);
|
||||
error = vm_setup_pptdev_msi(ctx, 0, sc->psc_sel.pc_bus,
|
||||
error = vm_setup_pptdev_msi(pi->pi_vmctx, 0, sc->psc_sel.pc_bus,
|
||||
sc->psc_sel.pc_dev, sc->psc_sel.pc_func,
|
||||
pi->pi_msi.addr, pi->pi_msi.msg_data,
|
||||
pi->pi_msi.maxmsgnum);
|
||||
|
|
@ -984,7 +981,7 @@ passthru_cfgwrite(struct vmctx *ctx, struct pci_devinst *pi, int coff,
|
|||
if (pi->pi_msix.enabled) {
|
||||
msix_table_entries = pi->pi_msix.table_count;
|
||||
for (i = 0; i < msix_table_entries; i++) {
|
||||
error = vm_setup_pptdev_msix(ctx, 0,
|
||||
error = vm_setup_pptdev_msix(pi->pi_vmctx, 0,
|
||||
sc->psc_sel.pc_bus, sc->psc_sel.pc_dev,
|
||||
sc->psc_sel.pc_func, i,
|
||||
pi->pi_msix.table[i].addr,
|
||||
|
|
@ -995,8 +992,9 @@ passthru_cfgwrite(struct vmctx *ctx, struct pci_devinst *pi, int coff,
|
|||
err(1, "vm_setup_pptdev_msix");
|
||||
}
|
||||
} else {
|
||||
error = vm_disable_pptdev_msix(ctx, sc->psc_sel.pc_bus,
|
||||
sc->psc_sel.pc_dev, sc->psc_sel.pc_func);
|
||||
error = vm_disable_pptdev_msix(pi->pi_vmctx,
|
||||
sc->psc_sel.pc_bus, sc->psc_sel.pc_dev,
|
||||
sc->psc_sel.pc_func);
|
||||
if (error)
|
||||
err(1, "vm_disable_pptdev_msix");
|
||||
}
|
||||
|
|
@ -1029,8 +1027,8 @@ passthru_cfgwrite(struct vmctx *ctx, struct pci_devinst *pi, int coff,
|
|||
}
|
||||
|
||||
static void
|
||||
passthru_write(struct vmctx *ctx, struct pci_devinst *pi, int baridx,
|
||||
uint64_t offset, int size, uint64_t value)
|
||||
passthru_write(struct pci_devinst *pi, int baridx, uint64_t offset, int size,
|
||||
uint64_t value)
|
||||
{
|
||||
struct passthru_softc *sc;
|
||||
struct pci_bar_ioreq pio;
|
||||
|
|
@ -1038,7 +1036,7 @@ passthru_write(struct vmctx *ctx, struct pci_devinst *pi, int baridx,
|
|||
sc = pi->pi_arg;
|
||||
|
||||
if (baridx == pci_msix_table_bar(pi)) {
|
||||
msix_table_write(ctx, sc, offset, size, value);
|
||||
msix_table_write(sc, offset, size, value);
|
||||
} else {
|
||||
assert(pi->pi_bar[baridx].type == PCIBAR_IO);
|
||||
assert(size == 1 || size == 2 || size == 4);
|
||||
|
|
@ -1057,8 +1055,7 @@ passthru_write(struct vmctx *ctx, struct pci_devinst *pi, int baridx,
|
|||
}
|
||||
|
||||
static uint64_t
|
||||
passthru_read(struct vmctx *ctx __unused, struct pci_devinst *pi, int baridx,
|
||||
uint64_t offset, int size)
|
||||
passthru_read(struct pci_devinst *pi, int baridx, uint64_t offset, int size)
|
||||
{
|
||||
struct passthru_softc *sc;
|
||||
struct pci_bar_ioreq pio;
|
||||
|
|
@ -1089,8 +1086,8 @@ passthru_read(struct vmctx *ctx __unused, struct pci_devinst *pi, int baridx,
|
|||
}
|
||||
|
||||
static void
|
||||
passthru_msix_addr(struct vmctx *ctx, struct pci_devinst *pi, int baridx,
|
||||
int enabled, uint64_t address)
|
||||
passthru_msix_addr(struct pci_devinst *pi, int baridx, int enabled,
|
||||
uint64_t address)
|
||||
{
|
||||
struct passthru_softc *sc;
|
||||
size_t remaining;
|
||||
|
|
@ -1100,13 +1097,14 @@ passthru_msix_addr(struct vmctx *ctx, struct pci_devinst *pi, int baridx,
|
|||
table_offset = rounddown2(pi->pi_msix.table_offset, 4096);
|
||||
if (table_offset > 0) {
|
||||
if (!enabled) {
|
||||
if (vm_unmap_pptdev_mmio(ctx, sc->psc_sel.pc_bus,
|
||||
if (vm_unmap_pptdev_mmio(pi->pi_vmctx,
|
||||
sc->psc_sel.pc_bus,
|
||||
sc->psc_sel.pc_dev,
|
||||
sc->psc_sel.pc_func, address,
|
||||
table_offset) != 0)
|
||||
warnx("pci_passthru: unmap_pptdev_mmio failed");
|
||||
} else {
|
||||
if (vm_map_pptdev_mmio(ctx, sc->psc_sel.pc_bus,
|
||||
if (vm_map_pptdev_mmio(pi->pi_vmctx, sc->psc_sel.pc_bus,
|
||||
sc->psc_sel.pc_dev,
|
||||
sc->psc_sel.pc_func, address,
|
||||
table_offset,
|
||||
|
|
@ -1121,13 +1119,14 @@ passthru_msix_addr(struct vmctx *ctx, struct pci_devinst *pi, int baridx,
|
|||
if (remaining > 0) {
|
||||
address += table_offset + table_size;
|
||||
if (!enabled) {
|
||||
if (vm_unmap_pptdev_mmio(ctx, sc->psc_sel.pc_bus,
|
||||
if (vm_unmap_pptdev_mmio(pi->pi_vmctx,
|
||||
sc->psc_sel.pc_bus,
|
||||
sc->psc_sel.pc_dev,
|
||||
sc->psc_sel.pc_func, address,
|
||||
remaining) != 0)
|
||||
warnx("pci_passthru: unmap_pptdev_mmio failed");
|
||||
} else {
|
||||
if (vm_map_pptdev_mmio(ctx, sc->psc_sel.pc_bus,
|
||||
if (vm_map_pptdev_mmio(pi->pi_vmctx, sc->psc_sel.pc_bus,
|
||||
sc->psc_sel.pc_dev,
|
||||
sc->psc_sel.pc_func, address,
|
||||
remaining,
|
||||
|
|
@ -1139,20 +1138,20 @@ passthru_msix_addr(struct vmctx *ctx, struct pci_devinst *pi, int baridx,
|
|||
}
|
||||
|
||||
static void
|
||||
passthru_mmio_addr(struct vmctx *ctx, struct pci_devinst *pi, int baridx,
|
||||
int enabled, uint64_t address)
|
||||
passthru_mmio_addr(struct pci_devinst *pi, int baridx, int enabled,
|
||||
uint64_t address)
|
||||
{
|
||||
struct passthru_softc *sc;
|
||||
|
||||
sc = pi->pi_arg;
|
||||
if (!enabled) {
|
||||
if (vm_unmap_pptdev_mmio(ctx, sc->psc_sel.pc_bus,
|
||||
if (vm_unmap_pptdev_mmio(pi->pi_vmctx, sc->psc_sel.pc_bus,
|
||||
sc->psc_sel.pc_dev,
|
||||
sc->psc_sel.pc_func, address,
|
||||
sc->psc_bar[baridx].size) != 0)
|
||||
warnx("pci_passthru: unmap_pptdev_mmio failed");
|
||||
} else {
|
||||
if (vm_map_pptdev_mmio(ctx, sc->psc_sel.pc_bus,
|
||||
if (vm_map_pptdev_mmio(pi->pi_vmctx, sc->psc_sel.pc_bus,
|
||||
sc->psc_sel.pc_dev,
|
||||
sc->psc_sel.pc_func, address,
|
||||
sc->psc_bar[baridx].size,
|
||||
|
|
@ -1184,8 +1183,7 @@ passthru_addr_rom(struct pci_devinst *const pi, const int idx,
|
|||
}
|
||||
|
||||
static void
|
||||
passthru_addr(struct vmctx *ctx, struct pci_devinst *pi, int baridx,
|
||||
int enabled, uint64_t address)
|
||||
passthru_addr(struct pci_devinst *pi, int baridx, int enabled, uint64_t address)
|
||||
{
|
||||
switch (pi->pi_bar[baridx].type) {
|
||||
case PCIBAR_IO:
|
||||
|
|
@ -1197,9 +1195,9 @@ passthru_addr(struct vmctx *ctx, struct pci_devinst *pi, int baridx,
|
|||
case PCIBAR_MEM32:
|
||||
case PCIBAR_MEM64:
|
||||
if (baridx == pci_msix_table_bar(pi))
|
||||
passthru_msix_addr(ctx, pi, baridx, enabled, address);
|
||||
passthru_msix_addr(pi, baridx, enabled, address);
|
||||
else
|
||||
passthru_mmio_addr(ctx, pi, baridx, enabled, address);
|
||||
passthru_mmio_addr(pi, baridx, enabled, address);
|
||||
break;
|
||||
default:
|
||||
errx(4, "%s: invalid BAR type %d", __func__,
|
||||
|
|
|
|||
|
|
@ -66,8 +66,7 @@ pci_uart_intr_deassert(void *arg)
|
|||
}
|
||||
|
||||
static void
|
||||
pci_uart_write(struct vmctx *ctx __unused,
|
||||
struct pci_devinst *pi, int baridx, uint64_t offset, int size,
|
||||
pci_uart_write(struct pci_devinst *pi, int baridx, uint64_t offset, int size,
|
||||
uint64_t value)
|
||||
{
|
||||
assert(baridx == 0);
|
||||
|
|
@ -77,8 +76,7 @@ pci_uart_write(struct vmctx *ctx __unused,
|
|||
}
|
||||
|
||||
static uint64_t
|
||||
pci_uart_read(struct vmctx *ctx __unused,
|
||||
struct pci_devinst *pi, int baridx, uint64_t offset, int size)
|
||||
pci_uart_read(struct pci_devinst *pi, int baridx, uint64_t offset, int size)
|
||||
{
|
||||
uint8_t val;
|
||||
|
||||
|
|
@ -99,7 +97,7 @@ pci_uart_legacy_config(nvlist_t *nvl, const char *opts)
|
|||
}
|
||||
|
||||
static int
|
||||
pci_uart_init(struct vmctx *ctx __unused, struct pci_devinst *pi, nvlist_t *nvl)
|
||||
pci_uart_init(struct pci_devinst *pi, nvlist_t *nvl)
|
||||
{
|
||||
struct uart_softc *sc;
|
||||
const char *device;
|
||||
|
|
|
|||
|
|
@ -248,7 +248,7 @@ pci_vt9p_legacy_config(nvlist_t *nvl, const char *opts)
|
|||
}
|
||||
|
||||
static int
|
||||
pci_vt9p_init(struct vmctx *ctx __unused, struct pci_devinst *pi, nvlist_t *nvl)
|
||||
pci_vt9p_init(struct pci_devinst *pi, nvlist_t *nvl)
|
||||
{
|
||||
struct pci_vt9p_softc *sc;
|
||||
const char *value;
|
||||
|
|
|
|||
|
|
@ -450,8 +450,7 @@ pci_vtblk_resized(struct blockif_ctxt *bctxt __unused, void *arg,
|
|||
}
|
||||
|
||||
static int
|
||||
pci_vtblk_init(struct vmctx *ctx __unused, struct pci_devinst *pi,
|
||||
nvlist_t *nvl)
|
||||
pci_vtblk_init(struct pci_devinst *pi, nvlist_t *nvl)
|
||||
{
|
||||
char bident[sizeof("XXX:XXX")];
|
||||
struct blockif_ctxt *bctxt;
|
||||
|
|
|
|||
|
|
@ -684,8 +684,7 @@ pci_vtcon_legacy_config(nvlist_t *nvl, const char *opts)
|
|||
}
|
||||
|
||||
static int
|
||||
pci_vtcon_init(struct vmctx *ctx __unused, struct pci_devinst *pi,
|
||||
nvlist_t *nvl)
|
||||
pci_vtcon_init(struct pci_devinst *pi, nvlist_t *nvl)
|
||||
{
|
||||
struct pci_vtcon_softc *sc;
|
||||
nvlist_t *ports_nvl;
|
||||
|
|
|
|||
|
|
@ -638,8 +638,7 @@ pci_vtinput_legacy_config(nvlist_t *nvl, const char *opts)
|
|||
}
|
||||
|
||||
static int
|
||||
pci_vtinput_init(struct vmctx *ctx __unused, struct pci_devinst *pi,
|
||||
nvlist_t *nvl)
|
||||
pci_vtinput_init(struct pci_devinst *pi, nvlist_t *nvl)
|
||||
{
|
||||
struct pci_vtinput_softc *sc;
|
||||
|
||||
|
|
|
|||
|
|
@ -560,8 +560,7 @@ pci_vtnet_ping_ctlq(void *vsc, struct vqueue_info *vq)
|
|||
#endif
|
||||
|
||||
static int
|
||||
pci_vtnet_init(struct vmctx *ctx __unused, struct pci_devinst *pi,
|
||||
nvlist_t *nvl)
|
||||
pci_vtnet_init(struct pci_devinst *pi, nvlist_t *nvl)
|
||||
{
|
||||
struct pci_vtnet_softc *sc;
|
||||
const char *value;
|
||||
|
|
|
|||
|
|
@ -140,8 +140,7 @@ pci_vtrnd_notify(void *vsc, struct vqueue_info *vq)
|
|||
|
||||
|
||||
static int
|
||||
pci_vtrnd_init(struct vmctx *ctx __unused, struct pci_devinst *pi,
|
||||
nvlist_t *nvl __unused)
|
||||
pci_vtrnd_init(struct pci_devinst *pi, nvlist_t *nvl __unused)
|
||||
{
|
||||
struct pci_vtrnd_softc *sc;
|
||||
int fd;
|
||||
|
|
|
|||
|
|
@ -245,7 +245,7 @@ static void pci_vtscsi_eventq_notify(void *, struct vqueue_info *);
|
|||
static void pci_vtscsi_requestq_notify(void *, struct vqueue_info *);
|
||||
static int pci_vtscsi_init_queue(struct pci_vtscsi_softc *,
|
||||
struct pci_vtscsi_queue *, int);
|
||||
static int pci_vtscsi_init(struct vmctx *, struct pci_devinst *, nvlist_t *);
|
||||
static int pci_vtscsi_init(struct pci_devinst *, nvlist_t *);
|
||||
|
||||
static struct virtio_consts vtscsi_vi_consts = {
|
||||
.vc_name = "vtscsi",
|
||||
|
|
@ -698,8 +698,7 @@ pci_vtscsi_legacy_config(nvlist_t *nvl, const char *opts)
|
|||
}
|
||||
|
||||
static int
|
||||
pci_vtscsi_init(struct vmctx *ctx __unused, struct pci_devinst *pi,
|
||||
nvlist_t *nvl)
|
||||
pci_vtscsi_init(struct pci_devinst *pi, nvlist_t *nvl)
|
||||
{
|
||||
struct pci_vtscsi_softc *sc;
|
||||
const char *devname, *value;
|
||||
|
|
|
|||
|
|
@ -2267,9 +2267,8 @@ pci_xhci_hostop_write(struct pci_xhci_softc *sc, uint64_t offset,
|
|||
|
||||
|
||||
static void
|
||||
pci_xhci_write(struct vmctx *ctx __unused,
|
||||
struct pci_devinst *pi, int baridx, uint64_t offset, int size __unused,
|
||||
uint64_t value)
|
||||
pci_xhci_write(struct pci_devinst *pi, int baridx, uint64_t offset,
|
||||
int size __unused, uint64_t value)
|
||||
{
|
||||
struct pci_xhci_softc *sc;
|
||||
|
||||
|
|
@ -2489,8 +2488,7 @@ pci_xhci_xecp_read(struct pci_xhci_softc *sc, uint64_t offset)
|
|||
|
||||
|
||||
static uint64_t
|
||||
pci_xhci_read(struct vmctx *ctx __unused,
|
||||
struct pci_devinst *pi, int baridx, uint64_t offset, int size)
|
||||
pci_xhci_read(struct pci_devinst *pi, int baridx, uint64_t offset, int size)
|
||||
{
|
||||
struct pci_xhci_softc *sc;
|
||||
uint32_t value;
|
||||
|
|
@ -2853,7 +2851,7 @@ bad:
|
|||
}
|
||||
|
||||
static int
|
||||
pci_xhci_init(struct vmctx *ctx __unused, struct pci_devinst *pi, nvlist_t *nvl)
|
||||
pci_xhci_init(struct pci_devinst *pi, nvlist_t *nvl)
|
||||
{
|
||||
struct pci_xhci_softc *sc;
|
||||
int error;
|
||||
|
|
|
|||
|
|
@ -990,7 +990,7 @@ vm_restore_user_devs(struct vmctx *ctx, struct restore_state *rstate)
|
|||
}
|
||||
|
||||
int
|
||||
vm_pause_user_devs(struct vmctx *ctx)
|
||||
vm_pause_user_devs(void)
|
||||
{
|
||||
const struct vm_snapshot_dev_info *info;
|
||||
size_t i;
|
||||
|
|
@ -1001,7 +1001,7 @@ vm_pause_user_devs(struct vmctx *ctx)
|
|||
if (info->pause_cb == NULL)
|
||||
continue;
|
||||
|
||||
ret = info->pause_cb(ctx, info->dev_name);
|
||||
ret = info->pause_cb(info->dev_name);
|
||||
if (ret != 0)
|
||||
return (ret);
|
||||
}
|
||||
|
|
@ -1010,7 +1010,7 @@ vm_pause_user_devs(struct vmctx *ctx)
|
|||
}
|
||||
|
||||
int
|
||||
vm_resume_user_devs(struct vmctx *ctx)
|
||||
vm_resume_user_devs(void)
|
||||
{
|
||||
const struct vm_snapshot_dev_info *info;
|
||||
size_t i;
|
||||
|
|
@ -1021,7 +1021,7 @@ vm_resume_user_devs(struct vmctx *ctx)
|
|||
if (info->resume_cb == NULL)
|
||||
continue;
|
||||
|
||||
ret = info->resume_cb(ctx, info->dev_name);
|
||||
ret = info->resume_cb(info->dev_name);
|
||||
if (ret != 0)
|
||||
return (ret);
|
||||
}
|
||||
|
|
@ -1367,7 +1367,7 @@ vm_checkpoint(struct vmctx *ctx, const char *checkpoint_file, bool stop_vm)
|
|||
|
||||
vm_vcpu_pause(ctx);
|
||||
|
||||
ret = vm_pause_user_devs(ctx);
|
||||
ret = vm_pause_user_devs();
|
||||
if (ret != 0) {
|
||||
fprintf(stderr, "Could not pause devices\r\n");
|
||||
error = ret;
|
||||
|
|
@ -1411,7 +1411,7 @@ vm_checkpoint(struct vmctx *ctx, const char *checkpoint_file, bool stop_vm)
|
|||
}
|
||||
|
||||
done:
|
||||
ret = vm_resume_user_devs(ctx);
|
||||
ret = vm_resume_user_devs();
|
||||
if (ret != 0)
|
||||
fprintf(stderr, "Could not resume devices\r\n");
|
||||
vm_vcpu_resume(ctx);
|
||||
|
|
|
|||
|
|
@ -66,8 +66,8 @@ struct checkpoint_thread_info {
|
|||
};
|
||||
|
||||
typedef int (*vm_snapshot_dev_cb)(struct vm_snapshot_meta *);
|
||||
typedef int (*vm_pause_dev_cb) (struct vmctx *, const char *);
|
||||
typedef int (*vm_resume_dev_cb) (struct vmctx *, const char *);
|
||||
typedef int (*vm_pause_dev_cb) (const char *);
|
||||
typedef int (*vm_resume_dev_cb) (const char *);
|
||||
|
||||
struct vm_snapshot_dev_info {
|
||||
const char *dev_name; /* device name */
|
||||
|
|
@ -96,8 +96,8 @@ int restore_vm_mem(struct vmctx *ctx, struct restore_state *rstate);
|
|||
int vm_restore_kern_structs(struct vmctx *ctx, struct restore_state *rstate);
|
||||
|
||||
int vm_restore_user_devs(struct vmctx *ctx, struct restore_state *rstate);
|
||||
int vm_pause_user_devs(struct vmctx *ctx);
|
||||
int vm_resume_user_devs(struct vmctx *ctx);
|
||||
int vm_pause_user_devs(void);
|
||||
int vm_resume_user_devs(void);
|
||||
|
||||
int get_checkpoint_msg(int conn_fd, struct vmctx *ctx);
|
||||
void *checkpoint_thread(void *param);
|
||||
|
|
|
|||
|
|
@ -558,8 +558,7 @@ vi_find_cr(int offset) {
|
|||
* Otherwise dispatch to the actual driver.
|
||||
*/
|
||||
uint64_t
|
||||
vi_pci_read(struct vmctx *ctx __unused,
|
||||
struct pci_devinst *pi, int baridx, uint64_t offset, int size)
|
||||
vi_pci_read(struct pci_devinst *pi, int baridx, uint64_t offset, int size)
|
||||
{
|
||||
struct virtio_softc *vs = pi->pi_arg;
|
||||
struct virtio_consts *vc;
|
||||
|
|
@ -678,8 +677,7 @@ done:
|
|||
* Otherwise dispatch to the actual driver.
|
||||
*/
|
||||
void
|
||||
vi_pci_write(struct vmctx *ctx __unused,
|
||||
struct pci_devinst *pi, int baridx, uint64_t offset, int size,
|
||||
vi_pci_write(struct pci_devinst *pi, int baridx, uint64_t offset, int size,
|
||||
uint64_t value)
|
||||
{
|
||||
struct virtio_softc *vs = pi->pi_arg;
|
||||
|
|
@ -815,7 +813,7 @@ done:
|
|||
|
||||
#ifdef BHYVE_SNAPSHOT
|
||||
int
|
||||
vi_pci_pause(struct vmctx *ctx __unused, struct pci_devinst *pi)
|
||||
vi_pci_pause(struct pci_devinst *pi)
|
||||
{
|
||||
struct virtio_softc *vs;
|
||||
struct virtio_consts *vc;
|
||||
|
|
@ -831,7 +829,7 @@ vi_pci_pause(struct vmctx *ctx __unused, struct pci_devinst *pi)
|
|||
}
|
||||
|
||||
int
|
||||
vi_pci_resume(struct vmctx *ctx __unused, struct pci_devinst *pi)
|
||||
vi_pci_resume(struct pci_devinst *pi)
|
||||
{
|
||||
struct virtio_softc *vs;
|
||||
struct virtio_consts *vc;
|
||||
|
|
|
|||
|
|
@ -195,7 +195,6 @@ vring_size_aligned(u_int qsz)
|
|||
return (roundup2(vring_size(qsz, VRING_ALIGN), VRING_ALIGN));
|
||||
}
|
||||
|
||||
struct vmctx;
|
||||
struct pci_devinst;
|
||||
struct vqueue_info;
|
||||
struct vm_snapshot_meta;
|
||||
|
|
@ -426,13 +425,13 @@ void vq_relchain_publish(struct vqueue_info *vq);
|
|||
void vq_relchain(struct vqueue_info *vq, uint16_t idx, uint32_t iolen);
|
||||
void vq_endchains(struct vqueue_info *vq, int used_all_avail);
|
||||
|
||||
uint64_t vi_pci_read(struct vmctx *ctx, struct pci_devinst *pi,
|
||||
int baridx, uint64_t offset, int size);
|
||||
void vi_pci_write(struct vmctx *ctx, struct pci_devinst *pi,
|
||||
int baridx, uint64_t offset, int size, uint64_t value);
|
||||
uint64_t vi_pci_read(struct pci_devinst *pi, int baridx, uint64_t offset,
|
||||
int size);
|
||||
void vi_pci_write(struct pci_devinst *pi, int baridx, uint64_t offset,
|
||||
int size, uint64_t value);
|
||||
#ifdef BHYVE_SNAPSHOT
|
||||
int vi_pci_snapshot(struct vm_snapshot_meta *meta);
|
||||
int vi_pci_pause(struct vmctx *ctx, struct pci_devinst *pi);
|
||||
int vi_pci_resume(struct vmctx *ctx, struct pci_devinst *pi);
|
||||
int vi_pci_pause(struct pci_devinst *pi);
|
||||
int vi_pci_resume(struct pci_devinst *pi);
|
||||
#endif
|
||||
#endif /* _BHYVE_VIRTIO_H_ */
|
||||
|
|
|
|||
Loading…
Reference in New Issue