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aic7xxx.seq: 

Add the same type of safeguards we use in the mesg_in phase to the mesg_out
phase.

aic7xxx_reg.h:
Add definitions for the DSCommand register for PCI adapters.
This commit is contained in:
Justin T. Gibbs 1996-01-07 19:18:28 +00:00
parent ac4b78d280
commit 78aeaf6139
2 changed files with 21 additions and 10 deletions
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19
sys/dev/aic7xxx/aic7xxx.seq
View File

@ -41,7 +41,7 @@
*
*-M************************************************************************/
VERSION AIC7XXX_SEQ_VER "$Id: aic7xxx.seq,v 1.24 1995/11/07 05:31:28 gibbs Exp $"
VERSION AIC7XXX_SEQ_VER "$Id: aic7xxx.seq,v 1.26 1996/01/05 16:11:49 gibbs Exp $"
#include "../../dev/aic7xxx/aic7xxx_reg.h"
@ -507,13 +507,18 @@ p_mesgout_start:
* a MESSAGE REJECT.
*/
p_mesgout_loop:
test SSTAT1,PHASEMIS jnz p_mesgout_phasemis
test SSTAT0,SPIORDY jz p_mesgout_loop
cmp DINDEX,1 jne p_mesgout_outb /* last byte? */
mvi CLRSINT1,CLRATNO /* drop ATN */
p_mesgout_outb:
test SSTAT1,PHASEMIS jnz p_mesgout_phasemis
or SXFRCTL0, CLRSTCNT
mvi STCNT0, 1
dec DINDEX
mov SCSIDATL,SINDIR
p_mesgout_outb_wait:
test SSTAT0,SDONE jz p_mesgout_outb_wait
p_mesgout4:
test DINDEX,0xff jnz p_mesgout_loop
@ -881,23 +886,19 @@ mk_mesg1:
inb_next:
call inb_last
inb_next_wait:
test SSTAT1,PHASEMIS jnz mesgin_phasemis
test SSTAT0,SPIORDY jz inb_next_wait /* wait for next byte */
inb_first:
test SSTAT1,PHASEMIS jnz mesgin_phasemis
test SSTAT0,SPIORDY jz inb_first /* wait for next byte */
mov DINDEX,SINDEX
mov DINDIR,SCSIBUSL ret /*read byte directly from bus*/
inb_last:
clr STCNT2
clr STCNT1
or SXFRCTL0,CLRSTCNT
mvi STCNT0,0x01
mov NONE,SCSIDATL /*dummy read from latch to ACK*/
inb_last_wait:
test SSTAT0,SDONE jz inb_last_wait /* Wait for completion */
ret
mesgin_phasemis:
/*
* We expected to receive another byte, but the target changed phase

12
sys/dev/aic7xxx/aic7xxx_reg.h
View File

@ -18,7 +18,7 @@
* 4. Modifications may be freely made to this file if the above conditions
* are met.
*
* $Id: aic7xxx_reg.h,v 1.1 1995/11/05 04:37:25 gibbs Exp $
* $Id: aic7xxx_reg.h,v 1.2 1996/01/03 06:25:32 gibbs Exp $
*/
/*
@ -355,6 +355,16 @@
/* RSVD 0x06 */
#define ENABLE 0x01
/*
* On the aic78X0 chips, Board Control is replaced by the DSCommand
* register (p. 4-64)
*/
#define DSCOMMAND 0x084
#define CACHETHEN 0x80 /* Cache Threshold enable */
#define DPARCKEN 0x40 /* Data Parity Check Enable */
#define MPARCKEN 0x20 /* Memory Parity Check Enable */
#define EXTREQLCK 0x10 /* External Request Lock */
/*
* Bus On/Off Time (p. 3-44)
*/