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Close PR #27742: allow the xl driver to receive VLAN tagged frames by 

setting the 'max packet size' register in window 3. This only
works for cards based on the cyclone or newer chipsets (i.e. it
won't work with the original 3c905/boomerang cards).

There is a trick which will work with the boomerang, which is to turn
on the 'large packets ok' bit in the MAC control register, however this
lets the chip accept any frame up to 4K in length, which is larger than
the mbuf cluster buffers we use to receive frames. If somebody sends us
such a frame and the chip DMAs it to us, it could write past the end
of the cluster buffer and clobber something.

PR: kern/27742
This commit is contained in:
Bill Paul 2001-05-31 22:08:45 +00:00
parent cf7e5998d7
commit 7d1b125b93
2 changed files with 16 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

16
sys/pci/if_xl.c
View File

@ -610,7 +610,8 @@ static void xl_miibus_statchg(dev)
/* Set ASIC's duplex mode to match the PHY. */
XL_SEL_WIN(3);
if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX)
CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
(CSR_READ_1(sc, XL_W3_MAC_CTRL) | XL_MACCTRL_DUPLEX));
else
CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
(CSR_READ_1(sc, XL_W3_MAC_CTRL) & ~XL_MACCTRL_DUPLEX));
@ -993,7 +994,8 @@ static void xl_setmode(sc, media)
IFM_SUBTYPE(media) == IFM_100_FX) {
printf("full duplex\n");
XL_SEL_WIN(3);
CSR_WRITE_1(sc, XL_W3_MAC_CTRL, XL_MACCTRL_DUPLEX);
CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
(CSR_READ_1(sc, XL_W3_MAC_CTRL) | XL_MACCTRL_DUPLEX));
} else {
printf("half duplex\n");
XL_SEL_WIN(3);
@ -2651,6 +2653,16 @@ static void xl_init(xsc)
else
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_COAX_STOP);
/*
* Allow reception of large packets to make
* people who use 802.1q VLANs happy.
*/
CSR_WRITE_1(sc, XL_W3_MAC_CTRL,
(CSR_READ_1(sc, XL_W3_MAC_CTRL) | XL_MACCTRL_LARGE_PACK));
/* increase packet size to allow reception of 802.1q or ISL packets */
if (sc->xl_type == XL_TYPE_905B)
CSR_WRITE_2(sc, XL_W3_MAXPKTSIZE, XL_PACKET_SIZE);
/* Clear out the stats counters. */
CSR_WRITE_2(sc, XL_COMMAND, XL_CMD_STATS_DISABLE);
sc->xl_stats_no_timeout = 1;

3
sys/pci/if_xlreg.h
View File

@ -81,7 +81,7 @@
#define XL_CAPS_100MBPS 0x1000
#define XL_CAPS_PWRMGMT 0x2000
#define XL_PACKET_SIZE 1536
#define XL_PACKET_SIZE 1540
/*
* Register layouts.
@ -256,6 +256,7 @@
* Window 3 (fifo management)
*/
#define XL_W3_INTERNAL_CFG 0x00
#define XL_W3_MAXPKTSIZE 0x04 /* 3c905B only */
#define XL_W3_RESET_OPT 0x08
#define XL_W3_FREE_TX 0x0C
#define XL_W3_FREE_RX 0x0A