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arm64: rockchip: rk_clk_composite: Remove gate code 

It was a bad idea to have composite clock directly managing gates.
All clocks drivers have been rewrite to not use this functionality
and directly export the gate. We can now remove this code.
This commit is contained in:
Emmanuel Vadot 2023-09-21 16:56:16 +02:00
parent 829b06ad8f
commit db34f02028
2 changed files with 2 additions and 37 deletions
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31
sys/arm64/rockchip/clk/rk_clk_composite.c
View File

@ -48,9 +48,6 @@ struct rk_clk_composite_sc {
uint32_t div_width; uint32_t div_width;
uint32_t div_mask; uint32_t div_mask;
uint32_t gate_offset;
uint32_t gate_shift;
uint32_t flags; uint32_t flags;
struct syscon *grf; struct syscon *grf;
@ -145,30 +142,6 @@ rk_clk_composite_init(struct clknode *clk, device_t dev)
return (0); return (0);
} }
static int
rk_clk_composite_set_gate(struct clknode *clk, bool enable)
{
struct rk_clk_composite_sc *sc;
uint32_t val = 0;
sc = clknode_get_softc(clk);
if ((sc->flags & RK_CLK_COMPOSITE_HAVE_GATE) == 0)
return (0);
dprintf("%sabling gate\n", enable ? "En" : "Dis");
if (!enable)
val |= 1 << sc->gate_shift;
dprintf("sc->gate_shift: %x\n", sc->gate_shift);
val |= (1 << sc->gate_shift) << RK_CLK_COMPOSITE_MASK_SHIFT;
dprintf("Write: gate_offset=%x, val=%x\n", sc->gate_offset, val);
DEVICE_LOCK(clk);
WRITE4(clk, sc->gate_offset, val);
DEVICE_UNLOCK(clk);
return (0);
}
static int static int
rk_clk_composite_set_mux(struct clknode *clk, int index) rk_clk_composite_set_mux(struct clknode *clk, int index)
{ {
@ -320,7 +293,6 @@ rk_clk_composite_set_freq(struct clknode *clk, uint64_t fparent, uint64_t *fout,
static clknode_method_t rk_clk_composite_clknode_methods[] = { static clknode_method_t rk_clk_composite_clknode_methods[] = {
/* Device interface */ /* Device interface */
CLKNODEMETHOD(clknode_init, rk_clk_composite_init), CLKNODEMETHOD(clknode_init, rk_clk_composite_init),
CLKNODEMETHOD(clknode_set_gate, rk_clk_composite_set_gate),
CLKNODEMETHOD(clknode_set_mux, rk_clk_composite_set_mux), CLKNODEMETHOD(clknode_set_mux, rk_clk_composite_set_mux),
CLKNODEMETHOD(clknode_recalc_freq, rk_clk_composite_recalc), CLKNODEMETHOD(clknode_recalc_freq, rk_clk_composite_recalc),
CLKNODEMETHOD(clknode_set_freq, rk_clk_composite_set_freq), CLKNODEMETHOD(clknode_set_freq, rk_clk_composite_set_freq),
@ -355,9 +327,6 @@ rk_clk_composite_register(struct clkdom *clkdom,
sc->div_width = clkdef->div_width; sc->div_width = clkdef->div_width;
sc->div_mask = ((1 << clkdef->div_width) - 1) << sc->div_shift; sc->div_mask = ((1 << clkdef->div_width) - 1) << sc->div_shift;
sc->gate_offset = clkdef->gate_offset;
sc->gate_shift = clkdef->gate_shift;
sc->flags = clkdef->flags; sc->flags = clkdef->flags;
clknode_register(clkdom, clk); clknode_register(clkdom, clk);

8
sys/arm64/rockchip/clk/rk_clk_composite.h
View File

@ -41,17 +41,13 @@ struct rk_clk_composite_def {
uint32_t div_shift; uint32_t div_shift;
uint32_t div_width; uint32_t div_width;
uint32_t gate_offset;
uint32_t gate_shift;
uint32_t flags; uint32_t flags;
}; };
#define RK_CLK_COMPOSITE_HAVE_MUX 0x0001 #define RK_CLK_COMPOSITE_HAVE_MUX 0x0001
#define RK_CLK_COMPOSITE_HAVE_GATE 0x0002 #define RK_CLK_COMPOSITE_DIV_EXP 0x0002 /* Register 0, 1, 2, 2, ... */
#define RK_CLK_COMPOSITE_DIV_EXP 0x0004 /* Register 0, 1, 2, 2, ... */
/* Divider 1, 2, 4, 8, ... */ /* Divider 1, 2, 4, 8, ... */
#define RK_CLK_COMPOSITE_GRF 0x0008 /* Use syscon registers instead of CRU's */ #define RK_CLK_COMPOSITE_GRF 0x0004 /* Use syscon registers instead of CRU's */
int rk_clk_composite_register(struct clkdom *clkdom, int rk_clk_composite_register(struct clkdom *clkdom,
struct rk_clk_composite_def *clkdef); struct rk_clk_composite_def *clkdef);