824 lines
23 KiB
C
824 lines
23 KiB
C
/*
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* Copyright (c) 1997, 1998
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* Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. All advertising materials mentioning features or use of this software
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* must display the following acknowledgement:
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* This product includes software developed by Bill Paul.
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* 4. Neither the name of the author nor the names of any co-contributors
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* may be used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD
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* BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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* THE POSSIBILITY OF SUCH DAMAGE.
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*
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* $Id: if_tlreg.h,v 1.2 1998/05/21 16:24:05 jkh Exp $
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*/
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struct tl_type {
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u_int16_t tl_vid;
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u_int16_t tl_did;
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char *tl_name;
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};
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/*
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* ThunderLAN TX/RX list format. The TX and RX lists are pretty much
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* identical: the list begins with a 32-bit forward pointer which points
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* at the next list in the chain, followed by 16 bits for the total
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* frame size, and a 16 bit status field. This is followed by a series
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* of 10 32-bit data count/data address pairs that point to the fragments
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* that make up the complete frame.
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*/
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#define TL_MAXFRAGS 10
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#define TL_RX_LIST_CNT 10
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#define TL_TX_LIST_CNT 10
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#define TL_MIN_FRAMELEN 64
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struct tl_frag {
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u_int32_t tlist_dcnt;
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u_int32_t tlist_dadr;
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};
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struct tl_list {
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u_int32_t tlist_fptr; /* phys address of next list */
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u_int16_t tlist_cstat; /* status word */
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u_int16_t tlist_frsize; /* size of data in frame */
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struct tl_frag tl_frag[TL_MAXFRAGS];
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};
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/*
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* This is a special case of an RX list. By setting the One_Frag
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* bit in the NETCONFIG register, the driver can force the ThunderLAN
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* chip to use only one fragment when DMAing RX frames.
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*/
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struct tl_list_onefrag {
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u_int32_t tlist_fptr;
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u_int16_t tlist_cstat;
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u_int16_t tlist_frsize;
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struct tl_frag tl_frag;
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};
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struct tl_list_data {
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struct tl_list_onefrag tl_rx_list[TL_RX_LIST_CNT];
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struct tl_list tl_tx_list[TL_TX_LIST_CNT];
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unsigned char tl_pad[TL_MIN_FRAMELEN];
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};
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struct tl_chain {
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struct tl_list *tl_ptr;
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struct mbuf *tl_mbuf;
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struct tl_chain *tl_next;
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};
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struct tl_chain_data {
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struct tl_chain tl_rx_chain[TL_RX_LIST_CNT];
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struct tl_chain tl_tx_chain[TL_TX_LIST_CNT];
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struct tl_chain *tl_rx_head;
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struct tl_chain *tl_rx_tail;
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struct tl_chain *tl_tx_head;
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struct tl_chain *tl_tx_tail;
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struct tl_chain *tl_tx_free;
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};
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struct tl_iflist;
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struct tl_softc {
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struct arpcom arpcom; /* interface info */
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struct ifmedia ifmedia; /* media info */
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struct tl_csr *csr; /* pointer to register map */
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struct tl_type *tl_dinfo; /* ThunderLAN adapter info */
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struct tl_type *tl_pinfo; /* PHY info struct */
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u_int8_t tl_ctlr; /* chip number */
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u_int8_t tl_unit; /* interface number */
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u_int8_t tl_phy_addr; /* PHY address */
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u_int8_t tl_autoneg; /* autoneg in progress */
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u_int16_t tl_phy_sts; /* PHY status */
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u_int16_t tl_phy_vid; /* PHY vendor ID */
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u_int16_t tl_phy_did; /* PHY device ID */
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struct tl_iflist *tl_iflist; /* Pointer to controller list */
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caddr_t tl_ldata_ptr;
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struct tl_list_data *tl_ldata; /* TX/RX lists and mbufs */
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struct tl_chain_data tl_cdata;
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int tl_txeoc;
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struct callout_handle tl_stat_ch;
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};
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#define TX_THR 0x00000007
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#define TL_FLAG_FORCEDELAY 1
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#define TL_FLAG_SCHEDDELAY 2
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#define TL_FLAG_DELAYTIMEO 3
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/*
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* The ThunderLAN supports up to 32 PHYs.
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*/
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#define TL_PHYADDR_MIN 0x00
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#define TL_PHYADDR_MAX 0x1F
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#define PHY_UNKNOWN 6
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struct tl_iflist {
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struct tl_csr *csr; /* Register map */
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struct tl_type *tl_dinfo;
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int tl_active_phy; /* # of active PHY */
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int tlc_unit; /* TLAN chip # */
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struct tl_softc *tl_sc[TL_PHYADDR_MAX]; /* pointers to PHYs */
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pcici_t tl_config_id;
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struct tl_iflist *tl_next;
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};
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#define TL_PHYS_IDLE -1
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/*
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* General constants that are fun to know.
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*
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* The ThunderLAN controller is made by Texas Instruments. The
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* manual indicates that if the EEPROM checksum fails, the PCI
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* vendor and device ID registers will be loaded with TI-specific
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* values.
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*/
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#define TI_VENDORID 0x104C
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#define TI_DEVICEID_THUNDERLAN 0x0500
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/*
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* Known PHY Ids. According to the Level 1 documentation (which is
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* very nice, incidentally), here's how they work:
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*
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* The PHY identifier register #1 is composed of bits 3 through 18
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* of the OUI. (First 16-bit word.)
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* The PHY identifier register #2 is composed of bits 19 through 24
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* if the OUI.
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* This is followed by 6 bits containing the manufacturer's model
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* number.
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* Lastly, there are 4 bits for the manufacturer's revision number.
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*
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* Honestly, there are a lot of these that don't make any sense; the
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* only way to be really sure is to look at the data sheets.
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*/
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/*
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* Texas Instruments PHY identifiers
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*
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* The ThunderLAN manual has a curious and confusing error in it.
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* In chapter 7, which describes PHYs, it says that TI PHYs have
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* the following ID codes, where xx denotes a revision:
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*
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* 0x4000501xx internal 10baseT PHY
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* 0x4000502xx TNETE211 100VG-AnyLan PMI
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*
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* The problem here is that these are not valid 32-bit hex numbers:
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* there's one digit too many. My guess is that they mean the internal
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* 10baseT PHY is 0x4000501x and the TNETE211 is 0x4000502x since these
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* are the only numbers that make sense.
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*/
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#define TI_PHY_VENDORID 0x4000
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#define TI_PHY_10BT 0x501F
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#define TI_PHY_100VGPMI 0x502F
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/*
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* These ID values are for the NS DP83840A 10/100 PHY
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*/
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#define NS_PHY_VENDORID 0x2000
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#define NS_PHY_83840A 0x5C0F
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/*
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* Level 1 10/100 PHY
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*/
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#define LEVEL1_PHY_VENDORID 0x7810
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#define LEVEL1_PHY_LXT970 0x000F
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/*
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* Intel 82555 10/100 PHY
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*/
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#define INTEL_PHY_VENDORID 0x0A28
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#define INTEL_PHY_82555 0x015F
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/*
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* SEEQ 80220 10/100 PHY
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*/
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#define SEEQ_PHY_VENDORID 0x0016
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#define SEEQ_PHY_80220 0xF83F
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/*
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* These are the PCI vendor and device IDs for Compaq ethernet
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* adapters based on the ThunderLAN controller.
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*/
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#define COMPAQ_VENDORID 0x0E11
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#define COMPAQ_DEVICEID_NETEL_10_100 0xAE32
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#define COMPAQ_DEVICEID_NETEL_10 0xAE34
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#define COMPAQ_DEVICEID_NETFLEX_3P_INTEGRATED 0xAE35
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#define COMPAQ_DEVICEID_NETEL_10_100_DUAL 0xAE40
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#define COMPAQ_DEVICEID_NETEL_10_100_PROLIANT 0xAE43
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#define COMPAQ_DEVICEID_DESKPRO_4000_5233MMX 0xB011
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#define COMPAQ_DEVICEID_NETFLEX_3P 0xF130
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#define COMPAQ_DEVICEID_NETFLEX_3P_BNC 0xF150
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/*
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* PCI low memory base and low I/O base
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*/
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#define TL_PCI_LOIO 0x10
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#define TL_PCI_LOMEM 0x14
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/*
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* ThunderLAN host register layout
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*/
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struct tl_regbytes {
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volatile u_int8_t byte0;
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volatile u_int8_t byte1;
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volatile u_int8_t byte2;
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volatile u_int8_t byte3;
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};
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struct tl_regwords {
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volatile u_int16_t word0;
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volatile u_int16_t word1;
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};
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struct tl_csr {
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volatile u_int32_t tl_host_cmd;
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volatile u_int32_t tl_ch_parm;
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volatile u_int16_t tl_dio_addr;
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volatile u_int16_t tl_host_int;
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union {
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volatile u_int32_t tl_dio_data;
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volatile struct tl_regwords tl_dio_words;
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volatile struct tl_regbytes tl_dio_bytes;
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} u;
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};
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/*
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* The DIO access macros allow us to read and write the ThunderLAN's
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* internal registers. The ThunderLAN manual gives examples using PIO.
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* This driver uses memory mapped I/O, which allows us to totally avoid
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* the use of inb/outb & friends. Memory mapped registers are keen.
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*
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* Note that the set/clr macros go to the trouble of reading the registers
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* back after they've been written. During initial development of this
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* driver, I discovered that the EEPROM access routines wouldn't work
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* properly unless I did this. I'm not sure why, though I suspect it
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* may have something to do with defeating the cache on the processor.
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*/
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/* Select a register */
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#define DIO_SEL(x) csr->tl_dio_addr = (u_int16_t)x
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/*
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* Set/clear/get a bit in the selected byte register
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*/
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#define DIO_BYTE0_SET(x) { \
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int f; \
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csr->u.tl_dio_bytes.byte0 |= \
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(u_int8_t)x; \
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f = csr->u.tl_dio_bytes.byte0; \
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}
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#define DIO_BYTE0_CLR(x) { \
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int f; \
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csr->u.tl_dio_bytes.byte0 &= \
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(u_int8_t)~x; \
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f = csr->u.tl_dio_bytes.byte0; \
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}
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#define DIO_BYTE0_GET(x) csr->u.tl_dio_bytes.byte0 & (u_int8_t)x
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#define DIO_BYTE1_SET(x) { \
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int f; \
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csr->u.tl_dio_bytes.byte1 |= \
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(u_int8_t)x; \
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f = csr->u.tl_dio_bytes.byte1; \
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}
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#define DIO_BYTE1_CLR(x) { \
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int f; \
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csr->u.tl_dio_bytes.byte1 &= \
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(u_int8_t)~x; \
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f = csr->u.tl_dio_bytes.byte1; \
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}
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#define DIO_BYTE1_GET(x) csr->u.tl_dio_bytes.byte1 & (u_int8_t)x
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#define DIO_BYTE2_SET(x) { \
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int f; \
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csr->u.tl_dio_bytes.byte2 |= \
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(u_int8_t)x; \
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f = csr->u.tl_dio_bytes.byte2; \
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}
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#define DIO_BYTE2_CLR(x) { \
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int f; \
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csr->u.tl_dio_bytes.byte2 &= \
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(u_int8_t)~x; \
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f = csr->u.tl_dio_bytes.byte2; \
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}
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#define DIO_BYTE2_GET(x) csr->u.tl_dio_bytes.byte2 & (u_int8_t)x
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#define DIO_BYTE3_SET(x) { \
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int f; \
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csr->u.tl_dio_bytes.byte3 |= \
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(u_int8_t)x; \
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f = csr->u.tl_dio_bytes.byte3; \
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}
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#define DIO_BYTE3_CLR(x) { \
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int f; \
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csr->u.tl_dio_bytes.byte3 &= \
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(u_int8_t)~x; \
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f = csr->u.tl_dio_bytes.byte3; \
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}
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#define DIO_BYTE3_GET(x) csr->u.tl_dio_bytes.byte3 & (u_int8_t)x
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/*
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* Read/write 16-bit word
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*/
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#define DIO_WORD0_SET(x) { \
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int f; \
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csr->u.tl_dio_words.word0 |= \
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(u_int16_t)x; \
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f = csr->u.tl_dio_words.word0; \
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}
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#define DIO_WORD0_CLR(x) { \
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int f; \
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csr->u.tl_dio_words.word0 &= \
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~(u_int16_t)x; \
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f = csr->u.tl_dio_words.word0; \
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}
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#define DIO_WORD0_GET(x) (csr->u.tl_dio_words.word0 & x)
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#define DIO_WORD1_SET(x) { \
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int f; \
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csr->u.tl_dio_words.word1 |= \
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(u_int16_t)x; \
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f = csr->u.tl_dio_words.word1; \
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}
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#define DIO_WORD1_CLR(x) { \
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int f; \
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csr->u.tl_dio_words.word1 &= \
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~(u_int16_t)x; \
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f = csr->u.tl_dio_words.word1; \
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}
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#define DIO_WORD1_GET(x) (csr->u.tl_dio_words.word1 & x)
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/*
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* Read/write 32-bit word
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*/
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#define DIO_LONG_GET(x) x = csr->u.tl_dio_data
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#define DIO_LONG_PUT(x) csr->u.tl_dio_data = (u_int32_t)x
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#define TL_DIO_ADDR_INC 0x8000 /* Increment addr on each read */
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#define TL_DIO_RAM_SEL 0x4000 /* RAM address select */
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#define TL_DIO_ADDR_MASK 0x3FFF /* address bits mask */
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/*
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* Interrupt types
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*/
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#define TL_INTR_INVALID 0x0
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#define TL_INTR_TXEOF 0x1
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#define TL_INTR_STATOFLOW 0x2
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#define TL_INTR_RXEOF 0x3
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#define TL_INTR_DUMMY 0x4
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#define TL_INTR_TXEOC 0x5
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#define TL_INTR_ADCHK 0x6
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#define TL_INTR_RXEOC 0x7
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#define TL_INT_MASK 0x001C
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#define TL_VEC_MASK 0x1FE0
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/*
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* Host command register bits
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*/
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#define TL_CMD_GO 0x80000000
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#define TL_CMD_STOP 0x40000000
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#define TL_CMD_ACK 0x20000000
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#define TL_CMD_CHSEL7 0x10000000
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#define TL_CMD_CHSEL6 0x08000000
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#define TL_CMD_CHSEL5 0x04000000
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#define TL_CMD_CHSEL4 0x02000000
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#define TL_CMD_CHSEL3 0x01000000
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#define TL_CMD_CHSEL2 0x00800000
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#define TL_CMD_CHSEL1 0x00400000
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#define TL_CMD_CHSEL0 0x00200000
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#define TL_CMD_EOC 0x00100000
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#define TL_CMD_RT 0x00080000
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#define TL_CMD_NES 0x00040000
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#define TL_CMD_ZERO0 0x00020000
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#define TL_CMD_ZERO1 0x00010000
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#define TL_CMD_ADRST 0x00008000
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#define TL_CMD_LDTMR 0x00004000
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#define TL_CMD_LDTHR 0x00002000
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#define TL_CMD_REQINT 0x00001000
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#define TL_CMD_INTSOFF 0x00000800
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#define TL_CMD_INTSON 0x00000400
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#define TL_CMD_RSVD0 0x00000200
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#define TL_CMD_RSVD1 0x00000100
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#define TL_CMD_ACK7 0x00000080
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#define TL_CMD_ACK6 0x00000040
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#define TL_CMD_ACK5 0x00000020
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#define TL_CMD_ACK4 0x00000010
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#define TL_CMD_ACK3 0x00000008
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#define TL_CMD_ACK2 0x00000004
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#define TL_CMD_ACK1 0x00000002
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#define TL_CMD_ACK0 0x00000001
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#define TL_CMD_CHSEL_MASK 0x01FE0000
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#define TL_CMD_ACK_MASK 0xFF
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/*
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* EEPROM address where station address resides.
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*/
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#define TL_EEPROM_EADDR 0x83
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#define TL_EEPROM_EADDR2 0x99
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#define TL_EEPROM_EADDR3 0xAF
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/*
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* ThunderLAN host command register offsets.
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* (Can be accessed either by IO ports or memory map.)
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*/
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#define TL_HOSTCMD 0x00
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#define TL_CH_PARM 0x04
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#define TL_DIO_ADDR 0x08
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#define TL_HOST_INT 0x0A
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#define TL_DIO_DATA 0x0C
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/*
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* ThunderLAN internal registers
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*/
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#define TL_NETCMD 0x00
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#define TL_NETSIO 0x01
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#define TL_NETSTS 0x02
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#define TL_NETMASK 0x03
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|
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#define TL_NETCONFIG 0x04
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#define TL_MANTEST 0x06
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|
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#define TL_VENID_LSB 0x08
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#define TL_VENID_MSB 0x09
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#define TL_DEVID_LSB 0x0A
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#define TL_DEVID_MSB 0x0B
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|
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#define TL_REVISION 0x0C
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#define TL_SUBCLASS 0x0D
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#define TL_MINLAT 0x0E
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#define TL_MAXLAT 0x0F
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|
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#define TL_AREG0_B5 0x10
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#define TL_AREG0_B4 0x11
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#define TL_AREG0_B3 0x12
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#define TL_AREG0_B2 0x13
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#define TL_AREG0_B1 0x14
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#define TL_AREG0_B0 0x15
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#define TL_AREG1_B5 0x16
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#define TL_AREG1_B4 0x17
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#define TL_AREG1_B3 0x18
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#define TL_AREG1_B2 0x19
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#define TL_AREG1_B1 0x1A
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#define TL_AREG1_B0 0x1B
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#define TL_AREG2_B5 0x1C
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#define TL_AREG2_B4 0x1D
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#define TL_AREG2_B3 0x1E
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#define TL_AREG2_B2 0x1F
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#define TL_AREG2_B1 0x20
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#define TL_AREG2_B0 0x21
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#define TL_AREG3_B5 0x22
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#define TL_AREG3_B4 0x23
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#define TL_AREG3_B3 0x24
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#define TL_AREG3_B2 0x25
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#define TL_AREG3_B1 0x26
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#define TL_AREG3_B0 0x27
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|
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#define TL_HASH1 0x28
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#define TL_HASH2 0x2C
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#define TL_TXGOODFRAMES 0x30
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#define TL_TXUNDERRUN 0x33
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#define TL_RXGOODFRAMES 0x34
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#define TL_RXOVERRUN 0x37
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#define TL_DEFEREDTX 0x38
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#define TL_CRCERROR 0x3A
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#define TL_CODEERROR 0x3B
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#define TL_MULTICOLTX 0x3C
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#define TL_SINGLECOLTX 0x3E
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#define TL_EXCESSIVECOL 0x40
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#define TL_LATECOL 0x41
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#define TL_CARRIERLOSS 0x42
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#define TL_ACOMMIT 0x43
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#define TL_LDREG 0x44
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#define TL_BSIZEREG 0x45
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#define TL_MAXRX 0x46
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/*
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* ThunderLAN SIO register bits
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*/
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#define TL_SIO_MINTEN 0x80
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#define TL_SIO_ECLOK 0x40
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#define TL_SIO_ETXEN 0x20
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#define TL_SIO_EDATA 0x10
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#define TL_SIO_NMRST 0x08
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#define TL_SIO_MCLK 0x04
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#define TL_SIO_MTXEN 0x02
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#define TL_SIO_MDATA 0x01
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/*
|
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* Thunderlan NETCONFIG bits
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*/
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#define TL_CFG_RCLKTEST 0x8000
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#define TL_CFG_TCLKTEST 0x4000
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#define TL_CFG_BITRATE 0x2000
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#define TL_CFG_RXCRC 0x1000
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#define TL_CFG_PEF 0x0800
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#define TL_CFG_ONEFRAG 0x0400
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#define TL_CFG_ONECHAN 0x0200
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#define TL_CFG_MTEST 0x0100
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#define TL_CFG_PHYEN 0x0080
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#define TL_CFG_MACSEL6 0x0040
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#define TL_CFG_MACSEL5 0x0020
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#define TL_CFG_MACSEL4 0x0010
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#define TL_CFG_MACSEL3 0x0008
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#define TL_CFG_MACSEL2 0x0004
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#define TL_CFG_MACSEL1 0x0002
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#define TL_CFG_MACSEL0 0x0001
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|
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/*
|
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* ThunderLAN NETSTS bits
|
|
*/
|
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#define TL_STS_MIRQ 0x80
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#define TL_STS_HBEAT 0x40
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#define TL_STS_TXSTOP 0x20
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#define TL_STS_RXSTOP 0x10
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|
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/*
|
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* ThunderLAN NETCMD bits
|
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*/
|
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#define TL_CMD_NRESET 0x80
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#define TL_CMD_NWRAP 0x40
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#define TL_CMD_CSF 0x20
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#define TL_CMD_CAF 0x10
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#define TL_CMD_NOBRX 0x08
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#define TL_CMD_DUPLEX 0x04
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#define TL_CMD_TRFRAM 0x02
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#define TL_CMD_TXPACE 0x01
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|
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/*
|
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* ThunderLAN NETMASK bits
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*/
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#define TL_MASK_MASK7 0x80
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#define TL_MASK_MASK6 0x40
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#define TL_MASK_MASK5 0x20
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#define TL_MASK_MASK4 0x10
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|
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/*
|
|
* MII frame format
|
|
*/
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#ifdef ANSI_DOESNT_ALLOW_BITFIELDS
|
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struct tl_mii_frame {
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u_int16_t mii_stdelim:2,
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mii_opcode:2,
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mii_phyaddr:5,
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mii_regaddr:5,
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mii_turnaround:2;
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u_int16_t mii_data;
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};
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#else
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struct tl_mii_frame {
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u_int8_t mii_stdelim;
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u_int8_t mii_opcode;
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u_int8_t mii_phyaddr;
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u_int8_t mii_regaddr;
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u_int8_t mii_turnaround;
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u_int16_t mii_data;
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};
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#endif
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|
/*
|
|
* MII constants
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|
*/
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#define TL_MII_STARTDELIM 0x01
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#define TL_MII_READOP 0x02
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#define TL_MII_WRITEOP 0x01
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#define TL_MII_TURNAROUND 0x02
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|
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#define TL_LAST_FRAG 0x80000000
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#define TL_CSTAT_UNUSED 0x8000
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#define TL_CSTAT_FRAMECMP 0x4000
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#define TL_CSTAT_READY 0x3000
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#define TL_CSTAT_UNUSED13 0x2000
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#define TL_CSTAT_UNUSED12 0x1000
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#define TL_CSTAT_EOC 0x0800
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#define TL_CSTAT_RXERROR 0x0400
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#define TL_CSTAT_PASSCRC 0x0200
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#define TL_CSTAT_DPRIO 0x0100
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|
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#define TL_FRAME_MASK 0x00FFFFFF
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#define tl_tx_goodframes(x) (x.tl_txstat & TL_FRAME_MASK)
|
|
#define tl_tx_underrun(x) ((x.tl_txstat & ~TL_FRAME_MASK) >> 24)
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#define tl_rx_goodframes(x) (x.tl_rxstat & TL_FRAME_MASK)
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#define tl_rx_overrun(x) ((x.tl_rxstat & ~TL_FRAME_MASK) >> 24)
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|
|
struct tl_stats {
|
|
u_int32_t tl_txstat;
|
|
u_int32_t tl_rxstat;
|
|
u_int16_t tl_deferred;
|
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u_int8_t tl_crc_errors;
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|
u_int8_t tl_code_errors;
|
|
u_int16_t tl_tx_multi_collision;
|
|
u_int16_t tl_tx_single_collision;
|
|
u_int8_t tl_excessive_collision;
|
|
u_int8_t tl_late_collision;
|
|
u_int8_t tl_carrier_loss;
|
|
u_int8_t acommit;
|
|
};
|
|
|
|
/*
|
|
* These are the register definitions for the PHY (physical layer
|
|
* interface chip).
|
|
* The ThunderLAN chip has a built-in 10Mb/sec PHY which may be used
|
|
* in some configurations. The Compaq 10/100 cards based on the ThunderLAN
|
|
* use a National Semiconductor DP83840A PHY. The generic BMCR and BMSR
|
|
* layouts for both PHYs are identical, however some of the bits are not
|
|
* used by the ThunderLAN's internal PHY (most notably those dealing with
|
|
* switching between 10 and 100Mb/sec speeds). Since Both PHYs use the
|
|
* same bits, we #define them with generic names here.
|
|
*/
|
|
/*
|
|
* PHY BMCR Basic Mode Control Register
|
|
*/
|
|
#define PHY_BMCR 0x00
|
|
#define PHY_BMCR_RESET 0x8000
|
|
#define PHY_BMCR_LOOPBK 0x4000
|
|
#define PHY_BMCR_SPEEDSEL 0x2000
|
|
#define PHY_BMCR_AUTONEGENBL 0x1000
|
|
#define PHY_BMCR_RSVD0 0x0800 /* write as zero */
|
|
#define PHY_BMCR_ISOLATE 0x0400
|
|
#define PHY_BMCR_AUTONEGRSTR 0x0200
|
|
#define PHY_BMCR_DUPLEX 0x0100
|
|
#define PHY_BMCR_COLLTEST 0x0080
|
|
#define PHY_BMCR_RSVD1 0x0040 /* write as zero, don't care */
|
|
#define PHY_BMCR_RSVD2 0x0020 /* write as zero, don't care */
|
|
#define PHY_BMCR_RSVD3 0x0010 /* write as zero, don't care */
|
|
#define PHY_BMCR_RSVD4 0x0008 /* write as zero, don't care */
|
|
#define PHY_BMCR_RSVD5 0x0004 /* write as zero, don't care */
|
|
#define PHY_BMCR_RSVD6 0x0002 /* write as zero, don't care */
|
|
#define PHY_BMCR_RSVD7 0x0001 /* write as zero, don't care */
|
|
/*
|
|
* RESET: 1 == software reset, 0 == normal operation
|
|
* Resets status and control registers to default values.
|
|
* Relatches all hardware config values.
|
|
*
|
|
* LOOPBK: 1 == loopback operation enabled, 0 == normal operation
|
|
*
|
|
* SPEEDSEL: 1 == 100Mb/s, 0 == 10Mb/s
|
|
* Link speed is selected byt his bit or if auto-negotiation if bit
|
|
* 12 (AUTONEGENBL) is set (in which case the value of this register
|
|
* is ignored).
|
|
*
|
|
* AUTONEGENBL: 1 == Autonegotiation enabled, 0 == Autonegotiation disabled
|
|
* Bits 8 and 13 are ignored when autoneg is set, otherwise bits 8 and 13
|
|
* determine speed and mode. Should be cleared and then set if PHY configured
|
|
* for no autoneg on startup.
|
|
*
|
|
* ISOLATE: 1 == isolate PHY from MII, 0 == normal operation
|
|
*
|
|
* AUTONEGRSTR: 1 == restart autonegotiation, 0 = normal operation
|
|
*
|
|
* DUPLEX: 1 == full duplex mode, 0 == half duplex mode
|
|
*
|
|
* COLLTEST: 1 == collision test enabled, 0 == normal operation
|
|
*/
|
|
|
|
/*
|
|
* PHY, BMSR Basic Mode Status Register
|
|
*/
|
|
#define PHY_BMSR 0x01
|
|
#define PHY_BMSR_100BT4 0x8000
|
|
#define PHY_BMSR_100BTXFULL 0x4000
|
|
#define PHY_BMSR_100BTXHALF 0x2000
|
|
#define PHY_BMSR_10BTFULL 0x1000
|
|
#define PHY_BMSR_10BTHALF 0x0800
|
|
#define PHY_BMSR_RSVD1 0x0400 /* write as zero, don't care */
|
|
#define PHY_BMSR_RSVD2 0x0200 /* write as zero, don't care */
|
|
#define PHY_BMSR_RSVD3 0x0100 /* write as zero, don't care */
|
|
#define PHY_BMSR_RSVD4 0x0080 /* write as zero, don't care */
|
|
#define PHY_BMSR_MFPRESUP 0x0040
|
|
#define PHY_BMSR_AUTONEGCOMP 0x0020
|
|
#define PHY_BMSR_REMFAULT 0x0010
|
|
#define PHY_BMSR_CANAUTONEG 0x0008
|
|
#define PHY_BMSR_LINKSTAT 0x0004
|
|
#define PHY_BMSR_JABBER 0x0002
|
|
#define PHY_BMSR_EXTENDED 0x0001
|
|
|
|
#define PHY_CTL_IGLINK 0x8000
|
|
#define PHY_CTL_SWAPOL 0x4000
|
|
#define PHY_CTL_AUISEL 0x2000
|
|
#define PHY_CTL_SQEEN 0x1000
|
|
#define PHY_CTL_MTEST 0x0800
|
|
#define PHY_CTL_NFEW 0x0004
|
|
#define PHY_CTL_INTEN 0x0002
|
|
#define PHY_CTL_TINT 0x0001
|
|
|
|
#define TL_PHY_GENCTL 0x00
|
|
#define TL_PHY_GENSTS 0x01
|
|
|
|
/*
|
|
* PHY Generic Identifier Register, hi bits
|
|
*/
|
|
#define TL_PHY_VENID 0x02
|
|
|
|
/*
|
|
* PHY Generic Identifier Register, lo bits
|
|
*/
|
|
#define TL_PHY_DEVID 0x03
|
|
|
|
#define TL_PHY_ANAR 0x04
|
|
#define TL_PHY_LPAR 0x05
|
|
#define TL_PHY_ANEXP 0x06
|
|
|
|
#define TL_PHY_PHYID 0x10
|
|
#define TL_PHY_CTL 0x11
|
|
#define TL_PHY_STS 0x12
|
|
|
|
#define TL_LPAR_RMFLT 0x2000
|
|
#define TL_LPAR_RSVD0 0x1000
|
|
#define TL_LPAR_RSVD1 0x0800
|
|
#define TL_LPAR_100BT4 0x0400
|
|
#define TL_LPAR_100BTXFULL 0x0200
|
|
#define TL_LPAR_100BTXHALF 0x0100
|
|
#define TL_LPAR_10BTFULL 0x0080
|
|
#define TL_LPAR_10BTHALF 0x0040
|
|
|
|
/*
|
|
* PHY Antoneg advertisement register.
|
|
*/
|
|
#define PHY_ANAR TL_PHY_ANAR
|
|
#define PHY_ANAR_NEXTPAGE 0x8000
|
|
#define PHY_ANAR_RSVD0 0x4000
|
|
#define PHY_ANAR_TLRFLT 0x2000
|
|
#define PHY_ANAR_RSVD1 0x1000
|
|
#define PHY_RSVD_RSDV2 0x0800
|
|
#define PHY_RSVD_RSVD3 0x0400
|
|
#define PHY_ANAR_100BT4 0x0200
|
|
#define PHY_ANAR_100BTXFULL 0x0100
|
|
#define PHY_ANAR_100BTXHALF 0x0080
|
|
#define PHY_ANAR_10BTFULL 0x0040
|
|
#define PHY_ANAR_10BTHALF 0x0020
|
|
#define PHY_ANAR_PROTO4 0x0010
|
|
#define PHY_ANAR_PROTO3 0x0008
|
|
#define PHY_ANAR_PROTO2 0x0004
|
|
#define PHY_AHAR_PROTO1 0x0002
|
|
#define PHY_AHAR_PROTO0 0x0001
|
|
|
|
/*
|
|
* DP83840 PHY, PCS Confifguration Register
|
|
*/
|
|
#define TL_DP83840_PCS 0x17
|
|
#define TL_DP83840_PCS_LED4_MODE 0x0002
|
|
#define TL_DP83840_PCS_F_CONNECT 0x0020
|
|
#define TL_DP83840_PCS_BIT8 0x0100
|
|
#define TL_DP83840_PCS_BIT10 0x0400
|
|
|
|
/*
|
|
* DP83840 PHY, PAR register
|
|
*/
|
|
#define TL_DP83840_PAR 0x19
|
|
|
|
#define PAR_RSVD0 0x8000
|
|
#define PAR_RSVD1 0x4000
|
|
#define PAR_RSVD2 0x2000
|
|
#define PAR_RSVD3 0x1000
|
|
#define PAR_DIS_CRS_JAB 0x0800
|
|
#define PAR_AN_EN_STAT 0x0400
|
|
#define PAR_RSVD4 0x0200
|
|
#define PAR_FEFI_EN 0x0100
|
|
#define PAR_DUPLEX_STAT 0x0080
|
|
#define PAR_SPEED_10 0x0040
|
|
#define PAR_CIM_STATUS 0x0020
|
|
#define PAR_PHYADDR4 0x0010
|
|
#define PAR_PHYADDR3 0x0008
|
|
#define PAR_PHYADDR2 0x0004
|
|
#define PAR_PHYADDR1 0x0002
|
|
#define PAR_PHYADDR0 0x0001
|
|
|
|
|
|
/*
|
|
* Microchip Technology 24Cxx EEPROM control bytes
|
|
*/
|
|
#define EEPROM_CTL_READ 0xA1 /* 0101 0001 */
|
|
#define EEPROM_CTL_WRITE 0xA0 /* 0101 0000 */
|