874 lines
15 KiB
C
874 lines
15 KiB
C
/*-
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* SPDX-License-Identifier: BSD-2-Clause
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*
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* Copyright (c) 2018 Emmanuel Vadot <manu@freebsd.org>
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* Copyright (c) 2018 Val Packett <val@packett.cool>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
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* OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
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* SUCH DAMAGE.
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*/
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#include <sys/param.h>
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#include <sys/systm.h>
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#include <sys/bus.h>
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#include <sys/rman.h>
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#include <sys/kernel.h>
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#include <sys/module.h>
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#include <machine/bus.h>
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#include <dev/fdt/simplebus.h>
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#include <dev/ofw/ofw_bus.h>
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#include <dev/ofw/ofw_bus_subr.h>
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#include <dev/extres/clk/clk_div.h>
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#include <dev/extres/clk/clk_fixed.h>
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#include <dev/extres/clk/clk_mux.h>
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#include <arm64/rockchip/clk/rk_cru.h>
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#define CRU_CLKSEL_CON(x) (0x80 + (x) * 0x4)
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#define CRU_CLKGATE_CON(x) (0x100 + (x) * 0x4)
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#define PLL_PPLL 1
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#define SCLK_32K_SUSPEND_PMU 2
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#define SCLK_SPI3_PMU 3
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#define SCLK_TIMER12_PMU 4
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#define SCLK_TIMER13_PMU 5
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#define SCLK_UART4_PMU 6
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#define SCLK_PVTM_PMU 7
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#define SCLK_WIFI_PMU 8
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#define SCLK_I2C0_PMU 9
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#define SCLK_I2C4_PMU 10
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#define SCLK_I2C8_PMU 11
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#define PCLK_PMU_SRC 19
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#define PCLK_PMU 20
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#define PCLK_PMUGRF_PMU 21
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#define PCLK_INTMEM1_PMU 22
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#define PCLK_GPIO0_PMU 23
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#define PCLK_GPIO1_PMU 24
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#define PCLK_SGRF_PMU 25
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#define PCLK_NOC_PMU 26
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#define PCLK_I2C0_PMU 27
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#define PCLK_I2C4_PMU 28
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#define PCLK_I2C8_PMU 29
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#define PCLK_RKPWM_PMU 30
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#define PCLK_SPI3_PMU 31
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#define PCLK_TIMER_PMU 32
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#define PCLK_MAILBOX_PMU 33
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#define PCLK_UART4_PMU 34
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#define PCLK_WDT_M0_PMU 35
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#define FCLK_CM0S_SRC_PMU 44
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#define FCLK_CM0S_PMU 45
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#define SCLK_CM0S_PMU 46
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#define HCLK_CM0S_PMU 47
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#define DCLK_CM0S_PMU 48
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#define PCLK_INTR_ARB_PMU 49
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#define HCLK_NOC_PMU 50
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/* GATES */
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static struct rk_cru_gate rk3399_pmu_gates[] = {
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/* PMUCRU_CLKGATE_CON0 */
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/* 0 Reserved */
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/* 1 fclk_cm0s_pmu_ppll_src_en */
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GATE(SCLK_SPI3_PMU, "clk_spi3_pmu", "clk_spi3_c", 0, 2),
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GATE(SCLK_TIMER12_PMU, "clk_timer0_pmu", "clk_timer_sel", 0, 3),
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GATE(SCLK_TIMER13_PMU, "clk_timer1_pmu", "clk_timer_sel", 0, 4),
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GATE(SCLK_UART4_PMU, "clk_uart4_pmu", "clk_uart4_sel", 0, 5),
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GATE(0, "clk_uart4_frac", "clk_uart4_frac_frac", 0, 6),
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/* 7 clk_pvtm_pmu_en */
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GATE(SCLK_WIFI_PMU, "clk_wifi_pmu", "clk_wifi_sel", 0, 8),
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GATE(SCLK_I2C0_PMU, "clk_i2c0_src", "clk_i2c0_div", 0, 9),
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GATE(SCLK_I2C4_PMU, "clk_i2c4_src", "clk_i2c4_div", 0, 10),
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GATE(SCLK_I2C8_PMU, "clk_i2c8_src", "clk_i2c8_div", 0, 11),
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/* 12:15 Reserved */
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/* PMUCRU_CLKGATE_CON1 */
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GATE(PCLK_PMU, "pclk_pmu", "pclk_pmu_src", 1, 0),
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/* 1 pclk_pmugrf_en */
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/* 2 pclk_intmem1_en */
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GATE(PCLK_GPIO0_PMU, "pclk_gpio0_pmu", "pclk_pmu_src", 1, 3),
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GATE(PCLK_GPIO1_PMU, "pclk_gpio1_pmu", "pclk_pmu_src", 1, 4),
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/* 5 pclk_sgrf_en */
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/* 6 pclk_noc_pmu_en */
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GATE(PCLK_I2C0_PMU, "pclk_i2c0_pmu", "pclk_pmu_src", 1, 7),
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GATE(PCLK_I2C4_PMU, "pclk_i2c4_pmu", "pclk_pmu_src", 1, 8),
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GATE(PCLK_I2C8_PMU, "pclk_i2c8_pmu", "pclk_pmu_src", 1, 9),
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GATE(PCLK_RKPWM_PMU, "pclk_rkpwm_pmu", "pclk_pmu_src", 1, 10),
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GATE(PCLK_SPI3_PMU, "pclk_spi3_pmu", "pclk_pmu_src", 1, 11),
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GATE(PCLK_TIMER_PMU, "pclk_timer_pmu", "pclk_pmu_src", 1, 12),
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GATE(PCLK_MAILBOX_PMU, "pclk_mailbox_pmu", "pclk_pmu_src", 1, 13),
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/* 14 pclk_uartm0_en */
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/* 15 pclk_wdt_m0_pmu_en */
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/* PMUCRU_CLKGATE_CON2 */
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/* 0 fclk_cm0s_en */
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/* 1 sclk_cm0s_en */
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/* 2 hclk_cm0s_en */
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/* 3 dclk_cm0s_en */
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/* 4 Reserved */
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/* 5 hclk_noc_pmu_en */
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/* 6:15 Reserved */
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};
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/*
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* PLLs
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*/
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static struct rk_clk_pll_rate rk3399_pll_rates[] = {
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{
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.freq = 2208000000,
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.refdiv = 1,
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.fbdiv = 92,
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.postdiv1 = 1,
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.postdiv2 = 1,
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.dsmpd = 1,
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},
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{
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.freq = 2184000000,
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.refdiv = 1,
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.fbdiv = 91,
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.postdiv1 = 1,
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.postdiv2 = 1,
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.dsmpd = 1,
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},
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{
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.freq = 2160000000,
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.refdiv = 1,
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.fbdiv = 90,
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.postdiv1 = 1,
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.postdiv2 = 1,
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.dsmpd = 1,
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},
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{
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.freq = 2136000000,
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.refdiv = 1,
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.fbdiv = 89,
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.postdiv1 = 1,
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.postdiv2 = 1,
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.dsmpd = 1,
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},
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{
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.freq = 2112000000,
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.refdiv = 1,
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.fbdiv = 88,
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.postdiv1 = 1,
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.postdiv2 = 1,
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.dsmpd = 1,
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},
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{
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.freq = 2088000000,
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.refdiv = 1,
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.fbdiv = 87,
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.postdiv1 = 1,
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.postdiv2 = 1,
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.dsmpd = 1,
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},
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{
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.freq = 2064000000,
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.refdiv = 1,
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.fbdiv = 86,
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.postdiv1 = 1,
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.postdiv2 = 1,
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.dsmpd = 1,
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},
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{
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.freq = 2040000000,
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.refdiv = 1,
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.fbdiv = 85,
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.postdiv1 = 1,
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.postdiv2 = 1,
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.dsmpd = 1,
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},
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{
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.freq = 2016000000,
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.refdiv = 1,
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.fbdiv = 84,
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.postdiv1 = 1,
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.postdiv2 = 1,
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.dsmpd = 1,
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},
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{
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.freq = 1992000000,
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.refdiv = 1,
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.fbdiv = 83,
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.postdiv1 = 1,
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.postdiv2 = 1,
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.dsmpd = 1,
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},
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{
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.freq = 1968000000,
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.refdiv = 1,
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.fbdiv = 82,
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.postdiv1 = 1,
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.postdiv2 = 1,
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.dsmpd = 1,
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},
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{
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.freq = 1944000000,
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.refdiv = 1,
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.fbdiv = 81,
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.postdiv1 = 1,
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.postdiv2 = 1,
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.dsmpd = 1,
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},
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{
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.freq = 1920000000,
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.refdiv = 1,
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.fbdiv = 80,
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.postdiv1 = 1,
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.postdiv2 = 1,
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.dsmpd = 1,
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},
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{
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.freq = 1896000000,
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.refdiv = 1,
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.fbdiv = 79,
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.postdiv1 = 1,
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.postdiv2 = 1,
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.dsmpd = 1,
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},
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{
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.freq = 1872000000,
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.refdiv = 1,
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.fbdiv = 78,
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.postdiv1 = 1,
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.postdiv2 = 1,
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.dsmpd = 1,
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},
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{
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.freq = 1848000000,
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.refdiv = 1,
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.fbdiv = 77,
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.postdiv1 = 1,
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.postdiv2 = 1,
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.dsmpd = 1,
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},
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{
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.freq = 1824000000,
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.refdiv = 1,
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.fbdiv = 76,
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.postdiv1 = 1,
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.postdiv2 = 1,
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.dsmpd = 1,
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},
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{
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.freq = 1800000000,
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.refdiv = 1,
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.fbdiv = 75,
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.postdiv1 = 1,
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.postdiv2 = 1,
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.dsmpd = 1,
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},
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{
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.freq = 1776000000,
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.refdiv = 1,
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.fbdiv = 74,
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.postdiv1 = 1,
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.postdiv2 = 1,
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.dsmpd = 1,
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},
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{
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.freq = 1752000000,
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.refdiv = 1,
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.fbdiv = 73,
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.postdiv1 = 1,
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.postdiv2 = 1,
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.dsmpd = 1,
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},
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{
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.freq = 1728000000,
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.refdiv = 1,
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.fbdiv = 72,
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.postdiv1 = 1,
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.postdiv2 = 1,
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.dsmpd = 1,
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},
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{
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.freq = 1704000000,
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.refdiv = 1,
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.fbdiv = 71,
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.postdiv1 = 1,
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.postdiv2 = 1,
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.dsmpd = 1,
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},
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{
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.freq = 1680000000,
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.refdiv = 1,
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.fbdiv = 70,
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.postdiv1 = 1,
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.postdiv2 = 1,
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.dsmpd = 1,
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},
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{
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.freq = 1656000000,
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.refdiv = 1,
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.fbdiv = 69,
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.postdiv1 = 1,
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.postdiv2 = 1,
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.dsmpd = 1,
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},
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{
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.freq = 1632000000,
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.refdiv = 1,
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.fbdiv = 68,
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.postdiv1 = 1,
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.postdiv2 = 1,
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.dsmpd = 1,
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},
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{
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.freq = 1608000000,
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.refdiv = 1,
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.fbdiv = 67,
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.postdiv1 = 1,
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.postdiv2 = 1,
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.dsmpd = 1,
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},
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{
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.freq = 1600000000,
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.refdiv = 3,
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.fbdiv = 200,
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.postdiv1 = 1,
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.postdiv2 = 1,
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.dsmpd = 1,
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},
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{
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.freq = 1584000000,
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.refdiv = 1,
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.fbdiv = 66,
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.postdiv1 = 1,
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.postdiv2 = 1,
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.dsmpd = 1,
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},
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{
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.freq = 1560000000,
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.refdiv = 1,
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.fbdiv = 65,
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.postdiv1 = 1,
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.postdiv2 = 1,
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.dsmpd = 1,
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},
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{
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.freq = 1536000000,
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.refdiv = 1,
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.fbdiv = 64,
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.postdiv1 = 1,
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.postdiv2 = 1,
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.dsmpd = 1,
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},
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{
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.freq = 1512000000,
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.refdiv = 1,
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.fbdiv = 63,
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.postdiv1 = 1,
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.postdiv2 = 1,
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.dsmpd = 1,
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},
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{
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.freq = 1488000000,
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.refdiv = 1,
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.fbdiv = 62,
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.postdiv1 = 1,
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.postdiv2 = 1,
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.dsmpd = 1,
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},
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{
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.freq = 1464000000,
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.refdiv = 1,
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.fbdiv = 61,
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.postdiv1 = 1,
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.postdiv2 = 1,
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.dsmpd = 1,
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},
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{
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.freq = 1440000000,
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.refdiv = 1,
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.fbdiv = 60,
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.postdiv1 = 1,
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.postdiv2 = 1,
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.dsmpd = 1,
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},
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{
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.freq = 1416000000,
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.refdiv = 1,
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.fbdiv = 59,
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.postdiv1 = 1,
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.postdiv2 = 1,
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.dsmpd = 1,
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},
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{
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.freq = 1392000000,
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.refdiv = 1,
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.fbdiv = 58,
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.postdiv1 = 1,
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.postdiv2 = 1,
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.dsmpd = 1,
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},
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{
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.freq = 1368000000,
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.refdiv = 1,
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.fbdiv = 57,
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.postdiv1 = 1,
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.postdiv2 = 1,
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.dsmpd = 1,
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},
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{
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.freq = 1344000000,
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.refdiv = 1,
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.fbdiv = 56,
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.postdiv1 = 1,
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.postdiv2 = 1,
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.dsmpd = 1,
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},
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{
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.freq = 1320000000,
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.refdiv = 1,
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.fbdiv = 55,
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.postdiv1 = 1,
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.postdiv2 = 1,
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.dsmpd = 1,
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},
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{
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.freq = 1296000000,
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.refdiv = 1,
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.fbdiv = 54,
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.postdiv1 = 1,
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.postdiv2 = 1,
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.dsmpd = 1,
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},
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{
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.freq = 1272000000,
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.refdiv = 1,
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.fbdiv = 53,
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.postdiv1 = 1,
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.postdiv2 = 1,
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.dsmpd = 1,
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},
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{
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.freq = 1248000000,
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.refdiv = 1,
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.fbdiv = 52,
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.postdiv1 = 1,
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.postdiv2 = 1,
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.dsmpd = 1,
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},
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{
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.freq = 1200000000,
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.refdiv = 1,
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.fbdiv = 50,
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.postdiv1 = 1,
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.postdiv2 = 1,
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.dsmpd = 1,
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},
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{
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.freq = 1188000000,
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.refdiv = 2,
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.fbdiv = 99,
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.postdiv1 = 1,
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.postdiv2 = 1,
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.dsmpd = 1,
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},
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{
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.freq = 1104000000,
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.refdiv = 1,
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.fbdiv = 46,
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.postdiv1 = 1,
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.postdiv2 = 1,
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.dsmpd = 1,
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},
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{
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.freq = 1100000000,
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.refdiv = 12,
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.fbdiv = 550,
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.postdiv1 = 1,
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.postdiv2 = 1,
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.dsmpd = 1,
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},
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{
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.freq = 1008000000,
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.refdiv = 1,
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.fbdiv = 84,
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.postdiv1 = 2,
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.postdiv2 = 1,
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.dsmpd = 1,
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},
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{
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.freq = 1000000000,
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.refdiv = 1,
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.fbdiv = 125,
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.postdiv1 = 3,
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.postdiv2 = 1,
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.dsmpd = 1,
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},
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{
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.freq = 984000000,
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.refdiv = 1,
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.fbdiv = 82,
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.postdiv1 = 2,
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.postdiv2 = 1,
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.dsmpd = 1,
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},
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{
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.freq = 960000000,
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.refdiv = 1,
|
|
.fbdiv = 80,
|
|
.postdiv1 = 2,
|
|
.postdiv2 = 1,
|
|
.dsmpd = 1,
|
|
},
|
|
{
|
|
.freq = 936000000,
|
|
.refdiv = 1,
|
|
.fbdiv = 78,
|
|
.postdiv1 = 2,
|
|
.postdiv2 = 1,
|
|
.dsmpd = 1,
|
|
},
|
|
{
|
|
.freq = 912000000,
|
|
.refdiv = 1,
|
|
.fbdiv = 76,
|
|
.postdiv1 = 2,
|
|
.postdiv2 = 1,
|
|
.dsmpd = 1,
|
|
},
|
|
{
|
|
.freq = 900000000,
|
|
.refdiv = 4,
|
|
.fbdiv = 300,
|
|
.postdiv1 = 2,
|
|
.postdiv2 = 1,
|
|
.dsmpd = 1,
|
|
},
|
|
{
|
|
.freq = 888000000,
|
|
.refdiv = 1,
|
|
.fbdiv = 74,
|
|
.postdiv1 = 2,
|
|
.postdiv2 = 1,
|
|
.dsmpd = 1,
|
|
},
|
|
{
|
|
.freq = 864000000,
|
|
.refdiv = 1,
|
|
.fbdiv = 72,
|
|
.postdiv1 = 2,
|
|
.postdiv2 = 1,
|
|
.dsmpd = 1,
|
|
},
|
|
{
|
|
.freq = 840000000,
|
|
.refdiv = 1,
|
|
.fbdiv = 70,
|
|
.postdiv1 = 2,
|
|
.postdiv2 = 1,
|
|
.dsmpd = 1,
|
|
},
|
|
{
|
|
.freq = 816000000,
|
|
.refdiv = 1,
|
|
.fbdiv = 68,
|
|
.postdiv1 = 2,
|
|
.postdiv2 = 1,
|
|
.dsmpd = 1,
|
|
},
|
|
{
|
|
.freq = 800000000,
|
|
.refdiv = 1,
|
|
.fbdiv = 100,
|
|
.postdiv1 = 3,
|
|
.postdiv2 = 1,
|
|
.dsmpd = 1,
|
|
},
|
|
{
|
|
.freq = 700000000,
|
|
.refdiv = 6,
|
|
.fbdiv = 350,
|
|
.postdiv1 = 2,
|
|
.postdiv2 = 1,
|
|
.dsmpd = 1,
|
|
},
|
|
{
|
|
.freq = 696000000,
|
|
.refdiv = 1,
|
|
.fbdiv = 58,
|
|
.postdiv1 = 2,
|
|
.postdiv2 = 1,
|
|
.dsmpd = 1,
|
|
},
|
|
{
|
|
.freq = 676000000,
|
|
.refdiv = 3,
|
|
.fbdiv = 169,
|
|
.postdiv1 = 2,
|
|
.postdiv2 = 1,
|
|
.dsmpd = 1,
|
|
},
|
|
{
|
|
.freq = 600000000,
|
|
.refdiv = 1,
|
|
.fbdiv = 75,
|
|
.postdiv1 = 3,
|
|
.postdiv2 = 1,
|
|
.dsmpd = 1,
|
|
},
|
|
{
|
|
.freq = 594000000,
|
|
.refdiv = 1,
|
|
.fbdiv = 99,
|
|
.postdiv1 = 4,
|
|
.postdiv2 = 1,
|
|
.dsmpd = 1,
|
|
},
|
|
{
|
|
.freq = 533250000,
|
|
.refdiv = 8,
|
|
.fbdiv = 711,
|
|
.postdiv1 = 4,
|
|
.postdiv2 = 1,
|
|
.dsmpd = 1,
|
|
},
|
|
{
|
|
.freq = 504000000,
|
|
.refdiv = 1,
|
|
.fbdiv = 63,
|
|
.postdiv1 = 3,
|
|
.postdiv2 = 1,
|
|
.dsmpd = 1,
|
|
},
|
|
{
|
|
.freq = 500000000,
|
|
.refdiv = 6,
|
|
.fbdiv = 250,
|
|
.postdiv1 = 2,
|
|
.postdiv2 = 1,
|
|
.dsmpd = 1,
|
|
},
|
|
{
|
|
.freq = 408000000,
|
|
.refdiv = 1,
|
|
.fbdiv = 68,
|
|
.postdiv1 = 2,
|
|
.postdiv2 = 2,
|
|
.dsmpd = 1,
|
|
},
|
|
{
|
|
.freq = 312000000,
|
|
.refdiv = 1,
|
|
.fbdiv = 52,
|
|
.postdiv1 = 2,
|
|
.postdiv2 = 2,
|
|
.dsmpd = 1,
|
|
},
|
|
{
|
|
.freq = 297000000,
|
|
.refdiv = 1,
|
|
.fbdiv = 99,
|
|
.postdiv1 = 4,
|
|
.postdiv2 = 2,
|
|
.dsmpd = 1,
|
|
},
|
|
{
|
|
.freq = 216000000,
|
|
.refdiv = 1,
|
|
.fbdiv = 72,
|
|
.postdiv1 = 4,
|
|
.postdiv2 = 2,
|
|
.dsmpd = 1,
|
|
},
|
|
{
|
|
.freq = 148500000,
|
|
.refdiv = 1,
|
|
.fbdiv = 99,
|
|
.postdiv1 = 4,
|
|
.postdiv2 = 4,
|
|
.dsmpd = 1,
|
|
},
|
|
{
|
|
.freq = 106500000,
|
|
.refdiv = 1,
|
|
.fbdiv = 71,
|
|
.postdiv1 = 4,
|
|
.postdiv2 = 4,
|
|
.dsmpd = 1,
|
|
},
|
|
{
|
|
.freq = 96000000,
|
|
.refdiv = 1,
|
|
.fbdiv = 64,
|
|
.postdiv1 = 4,
|
|
.postdiv2 = 4,
|
|
.dsmpd = 1,
|
|
},
|
|
{
|
|
.freq = 74250000,
|
|
.refdiv = 2,
|
|
.fbdiv = 99,
|
|
.postdiv1 = 4,
|
|
.postdiv2 = 4,
|
|
.dsmpd = 1,
|
|
},
|
|
{
|
|
.freq = 65000000,
|
|
.refdiv = 1,
|
|
.fbdiv = 65,
|
|
.postdiv1 = 6,
|
|
.postdiv2 = 4,
|
|
.dsmpd = 1,
|
|
},
|
|
{
|
|
.freq = 54000000,
|
|
.refdiv = 1,
|
|
.fbdiv = 54,
|
|
.postdiv1 = 6,
|
|
.postdiv2 = 4,
|
|
.dsmpd = 1,
|
|
},
|
|
{
|
|
.freq = 27000000,
|
|
.refdiv = 1,
|
|
.fbdiv = 27,
|
|
.postdiv1 = 6,
|
|
.postdiv2 = 4,
|
|
.dsmpd = 1,
|
|
},
|
|
{},
|
|
};
|
|
|
|
PLIST(xin24m_p) = {"xin24m"};
|
|
PLIST(xin24m_xin32k_p) = {"xin24m", "xin32k"};
|
|
PLIST(xin24m_ppll_p) = {"xin24m", "ppll"};
|
|
PLIST(uart4_p) = {"clk_uart4_c", "clk_uart4_frac", "xin24m"};
|
|
PLIST(wifi_p) = {"clk_wifi_c", "clk_wifi_frac"};
|
|
|
|
static struct rk_clk_pll_def ppll = {
|
|
.clkdef = {
|
|
.id = PLL_PPLL,
|
|
.name = "ppll",
|
|
.parent_names = xin24m_p,
|
|
.parent_cnt = nitems(xin24m_p),
|
|
},
|
|
.base_offset = 0x00,
|
|
|
|
.rates = rk3399_pll_rates,
|
|
};
|
|
|
|
static struct rk_clk rk3399_pmu_clks[] = {
|
|
/* Linked clocks */
|
|
LINK("xin32k"),
|
|
|
|
{
|
|
.type = RK3399_CLK_PLL,
|
|
.clk.pll = &ppll
|
|
},
|
|
|
|
/* PMUCRU_CLKSEL_CON0 */
|
|
CDIV(PCLK_PMU_SRC, "pclk_pmu_src", "ppll", 0, 0, 0, 5),
|
|
/* 5:7 Reserved */
|
|
/* 8:12 cm0s_div */
|
|
/* 13:14 Reserved */
|
|
/* 15 cm0s_clk_pll_sel */
|
|
|
|
/* PMUCRU_CLKSEL_CON1 */
|
|
COMP(0, "clk_spi3_c", xin24m_ppll_p, 0, 1, 0, 7, 7, 1),
|
|
COMP(0, "clk_wifi_c", xin24m_ppll_p, 0, 1, 8, 5, 13, 1),
|
|
MUX(0, "clk_wifi_sel", wifi_p, 0, 1, 14, 1),
|
|
MUX(0, "clk_timer_sel", xin24m_xin32k_p, 0, 1, 15, 1),
|
|
|
|
/* PMUCRU_CLKSEL_CON2 */
|
|
CDIV(0, "clk_i2c0_div", "ppll", 0, 2, 0, 7),
|
|
/* 7 Reserved */
|
|
CDIV(0, "clk_i2c8_div", "ppll", 0, 2, 8, 7),
|
|
/* 15 Reserved */
|
|
|
|
/* PMUCRU_CLKSEL_CON3 */
|
|
CDIV(0, "clk_i2c4_div", "ppll", 0, 3, 0, 7),
|
|
/* 7:15 Reserved */
|
|
|
|
/* PMUCRU_CLKSEL_CON4 */
|
|
/* 0:9 clk_32k_suspend_div */
|
|
/* 10:14 Reserved */
|
|
/* 15 clk_32k_suspend_sel */
|
|
|
|
/* PMUCRU_CLKSEL_CON5 */
|
|
COMP(0, "clk_uart4_c", xin24m_ppll_p, 0, 5, 0, 7, 10, 1),
|
|
/* 7 Reserved */
|
|
MUX(0, "clk_uart4_sel", uart4_p, 0, 5, 8, 2),
|
|
/* 11:15 Reserved */
|
|
|
|
/* PMUCRU_CLKFRAC_CON0 / PMUCRU_CLKSEL_CON6 */
|
|
FRACT(0, "clk_uart4_frac_frac", "clk_uart4_sel", 0, 6),
|
|
|
|
/* PMUCRU_CLKFRAC_CON1 / PMUCRU_CLKSEL_CON7 */
|
|
FRACT(0, "clk_wifi_frac", "clk_wifi_c", 0, 7),
|
|
};
|
|
|
|
static int
|
|
rk3399_pmucru_probe(device_t dev)
|
|
{
|
|
|
|
if (!ofw_bus_status_okay(dev))
|
|
return (ENXIO);
|
|
|
|
if (ofw_bus_is_compatible(dev, "rockchip,rk3399-pmucru")) {
|
|
device_set_desc(dev, "Rockchip RK3399 PMU Clock and Reset Unit");
|
|
return (BUS_PROBE_DEFAULT);
|
|
}
|
|
|
|
return (ENXIO);
|
|
}
|
|
|
|
static int
|
|
rk3399_pmucru_attach(device_t dev)
|
|
{
|
|
struct rk_cru_softc *sc;
|
|
|
|
sc = device_get_softc(dev);
|
|
sc->dev = dev;
|
|
|
|
sc->gates = rk3399_pmu_gates;
|
|
sc->ngates = nitems(rk3399_pmu_gates);
|
|
|
|
sc->clks = rk3399_pmu_clks;
|
|
sc->nclks = nitems(rk3399_pmu_clks);
|
|
|
|
sc->reset_offset = 0x110;
|
|
sc->reset_num = 30;
|
|
|
|
return (rk_cru_attach(dev));
|
|
}
|
|
|
|
static device_method_t rk3399_pmucru_methods[] = {
|
|
/* Device interface */
|
|
DEVMETHOD(device_probe, rk3399_pmucru_probe),
|
|
DEVMETHOD(device_attach, rk3399_pmucru_attach),
|
|
|
|
DEVMETHOD_END
|
|
};
|
|
|
|
DEFINE_CLASS_1(rk3399_pmucru, rk3399_pmucru_driver, rk3399_pmucru_methods,
|
|
sizeof(struct rk_cru_softc), rk_cru_driver);
|
|
|
|
EARLY_DRIVER_MODULE(rk3399_pmucru, simplebus, rk3399_pmucru_driver, 0, 0,
|
|
BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);
|