2001-02-13 11:02:15 +00:00
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# ex:ts=8
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# New ports collection makefile for: iverilog
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# Date created: Feb 13, 2001
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# Whom: Ying-Chieh Liao <ijliao@FreeBSD.org>
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#
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# $FreeBSD$
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#
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PORTNAME= iverilog
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2003-01-31 17:49:45 +00:00
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PORTVERSION= 0.7
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2001-02-13 11:02:15 +00:00
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CATEGORIES= cad
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MASTER_SITES= ftp://icarus.com/pub/eda/verilog/v${PORTVERSION}/
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DISTNAME= verilog-${PORTVERSION}
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2003-05-19 08:24:55 +00:00
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MAINTAINER= watchman@ludd.luth.se
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2003-05-17 03:17:55 +00:00
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COMMENT= A Verilog simulation and synthesis tool
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2001-02-13 11:02:15 +00:00
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2001-02-22 04:58:04 +00:00
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USE_BISON= yes
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2001-02-13 11:02:15 +00:00
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USE_GMAKE= yes
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2003-05-17 03:17:55 +00:00
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GNU_CONFIGURE= yes
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2001-02-13 11:02:15 +00:00
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2003-05-17 03:17:55 +00:00
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MAN1= iverilog-vpi.1 iverilog.1 vvp.1
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2001-02-13 11:02:15 +00:00
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.include <bsd.port.mk>
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