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Change Id->FreeBSD.
1999-08-25 04:58:03 +00:00
# $FreeBSD$
New cad group
1995-01-13 11:10:43 +00:00
#
Clean up subdir Makefiles. They now all look like this: ===== # Id line # # RESTRICTED: restricted_port_1 (comment1) # RESTRICTED: restricted_port_2 (comment2) # # BROKEN: broken_port_3 (comment3) # BROKEN: broken_port_4 (comment4) # BROKEN: broken_port_5 (comment5) # SUBDIR= good_port_1 good_port_2 ... ===== Basically, the idea is to make it easy to find restricted or broken ports by doing a "grep".
1995-05-14 03:30:07 +00:00
Remove category pkg/COMMENT files in favour of a COMMENT variable in the category makefile. Submitted by: Matthew Seaman <m.seaman@infracaninophile.co.uk> PR: 59651
2004-04-02 07:29:48 +00:00
COMMENT = CAD tools
NEW port CAD/admesh A tool to analyze STL (stereolitholigraphy) files. PR: ports/52997 Submitted by: Pedro F. Giffuni <giffunip@yahoo.com>
2003-10-10 05:16:19 +00:00
SUBDIR += admesh
ADMS is a code generator that converts electrical compact device models specified in high-level description language into ready-to-compile c code for the API of spice simulators. WWW: http://mot-adms.sourceforge.net/ PR: ports/101014 Submitted by: Stanislav Sedov <ssedov at mbsd.msk.ru>
2006-07-29 21:10:26 +00:00
SUBDIR += adms
Add cad/alliance, which is a complete set of free CAD tools and portable libraries for VLSI design. It includes a VHDL compiler and simulator, logic synthesis tools, automatic place and route tools, and portable CMOS libraries. Approved by: linimon (mentor)
2004-05-13 18:51:03 +00:00
SUBDIR += alliance
Add astk-client , graphical interface for Code_Aster (client side). PR: 54765 Submitted by: thierry@pompo.net
2003-07-23 11:25:42 +00:00
SUBDIR += astk-client
Add astk-serveur 1.0.14, graphical interface for Code_Aster (server side). PR: 54764 Submitted by: thierry@pompo.net
2003-07-23 11:20:26 +00:00
SUBDIR += astk-serveur
New port atlc version 4.0.1: A tool to calculate the impedance of transmission lines Submitted by: blackend
2002-11-13 20:21:29 +00:00
SUBDIR += atlc
BasicDSP is an educational tool that makes it easy to experiment with simple Digital Signal Processing algorithms for audio signals. The input can either be taken from the sound card, or be a locally generated sine wave, white noise or impulse signal. The output is fed to the sound card, as well as to a virtual oscilloscope and spectrum analyzer.
2008-08-17 20:22:21 +00:00
SUBDIR += basicdsp
BrickUtils is a simple utility for builders that use LEGO Digital Designer or LDraw-compatible CAD for designing models. WWW: http://bricksnspace.wordpress.com/brickutils/
2014-03-06 13:34:59 +00:00
SUBDIR += brickutils
Add brlcad 7.0.4, CSG modelling system from the US Balistic Research Laboratory. PR: 76122 Submitted by: Pedro F. Giffuni
2005-02-20 22:00:46 +00:00
SUBDIR += brlcad
A Three-Dimensional Structural Finite Element Program Submitted by : Pedro F. Giffuni <giffunip@yahoo.com> Almost writeen by: maho
2003-05-05 13:06:37 +00:00
SUBDIR += calculix
New port cascade version 1.4: A simple tool to analyze noise and distortion of a RF system Submitted by: blackend
2002-11-13 19:12:13 +00:00
SUBDIR += cascade
Add chipmunk, convert to new format along the way.
1995-08-25 10:06:06 +00:00
SUBDIR += chipmunk
add chipvault 200211 A project organizer for VHDL and Verilog RTL hardware designs
2003-01-29 03:45:13 +00:00
SUBDIR += chipvault
cider version 1b1 A mixed-level circuit and device simulator (includes SPICE3). PR: 15462 Submitted by: AMAKAWA Shuhei <amakawa@jp.FreeBSD.org>
1999-12-25 15:40:48 +00:00
SUBDIR += cider
Add dinotrace, a mature signal waveform viewer used to debug digital design simulations. PR: ports/68688 Submitted by: Joachim Strombergson <watchman@ludd.ltu.se>
2004-07-05 21:02:41 +00:00
SUBDIR += dinotrace
add dxf2fig 2.07 DXF to FIG converter
2004-08-26 09:38:31 +00:00
SUBDIR += dxf2fig
Activate Electric. PR: ports/18380 Submitted by: Mario Sergio Fujikawa Ferreira <lioux@linf.unb.br>
2000-07-30 07:14:47 +00:00
SUBDIR += electric
Electric is a sophisticated electrical CAD system that can handle many forms of circuit design, including: - Custom IC layout (ASICs) - Schematic drawing - Hardware description language specifications Author: Static Free Software & Sun Microsystems, Inc. WWW: http://www.staticfreesoft.com/ PR: ports/100355 Submitted by: me (stas) Approved by: sem (mentor)
2006-09-30 09:41:07 +00:00
SUBDIR += electric-ng
Add feappv 2.0, finite Element Analysis Program "personal version". This is a FEA program used in a classic FEM book. A complete (commercial) version is available here: <http://www.ce.berkeley.edu/~rlt/feap/> The "personal version" is very limited, but it keeps the same format as the complete (commercial) version and cad/netgen can produce files for it. PR: ports/95210 Submitted by: Pedro F. Giffuni <giffunip (at) asme.org>
2006-04-03 19:57:24 +00:00
SUBDIR += feappv
FidoCadJ is an easy to use graphical editor, with a library of electrical symbols and footprints (traditional and SMD). It aims to be an agile and effective small EDA tool for hobbyists. FidoCadJ stores its drawings in a compact text format, practical for the copy and paste in newsgroups and forums: this has determined its success on the Usenet and in numerous communities. WWW: http://davbucci.chez-alice.fr/index.php?argument=elettronica/fidocadj/fidocadj.inc
2012-05-05 16:51:14 +00:00
SUBDIR += fidocadj
FindHier is a road-map generator for Magic/CIF/gdsII/PCSTR/GED/TeX. ---When you have a large number of or big layout/schematic/TeX files which have possibly many top cells made by other people, how can you manage those layout/schematic/TeXs? FH is written for that. It can be useful up to your imagination or shell programming skill. FH analyses the hidden hierarchies of those cells and shows you the hierarchy information.
2007-04-28 17:01:15 +00:00
SUBDIR += findhier
The goals of the FreeHDL project are to develop a VHDL simulator that has a graphical waveform viewer and a source level debugger. It also aims at VHDL-93 compliancy. The project is at a very early development stage. WWW: http://www.freehdl.seul.org/ PR: ports/104634 Submitted by: lon_kamikaze at gmx.de
2006-11-05 20:51:06 +00:00
SUBDIR += freehdl
GDSreader is a simple Calma (GDSii) parser/printer tool.
2007-04-28 16:56:55 +00:00
SUBDIR += gdsreader
GDT (graphics data text) format translator written in C/C++ that converts a binary gdsii file to a text format that is compact and easy to parse.
2007-04-29 07:20:02 +00:00
SUBDIR += gdt
Activate geda.
1998-12-06 14:13:23 +00:00
SUBDIR += geda
Various documentation for gEDA suite, including architecture-related docs as well as examples of usage and tutorials. WWW: http://www.geda.seul.org PR: ports/99565 Submitted by: Stanislav Sedov <ssedov@mbsd.msk.ru>
2006-07-04 15:26:09 +00:00
SUBDIR += geda-docs
Various examples for gEDA suite. This includes: 1) gTAG - USB to JTAG interface 2) lightning_detector - a lightning detector 3) RF_Amp - schematics and associated materials for a SPICE model 4) TwoStageAmp - a two stage amplifier SPICE playpen WWW: http://www.geda.seul.org PR: ports/99564 Submitted by: Stanislav Sedov <ssedov@mbsd.msk.ru>
2006-07-04 15:31:24 +00:00
SUBDIR += geda-examples
Gattrib is gEDA's attribute editor. WWW: http://www.geda.seul.org PR: ports/99480 Submitted by: Stanislav Sedov <ssedov@mbsd.msk.ru>
2006-06-26 22:09:30 +00:00
SUBDIR += geda-gattrib
- gschem -> geda-gschem - gnetlist -> geda-netlist PR: ports/100222, ports/100230 Submitted by: maintainer
2006-07-16 04:00:28 +00:00
SUBDIR += geda-gschem
SUBDIR += geda-netlist
geda-symbols is the basic component of geda package. Submitted byu.schwander@technologist.com
2001-04-07 00:17:32 +00:00
SUBDIR += geda-symbols
add geda-symcheck gEDA symbol checking utility PR: 43563 Submitted by: bruno <bruno@mail.tinkerbox.org>
2002-10-10 18:35:25 +00:00
SUBDIR += geda-symcheck
add geda-utils gEDA utilities PR: 43563 Submitted by: bruno <bruno@mail.tinkerbox.org>
2002-10-10 18:38:37 +00:00
SUBDIR += geda-utils
add gerbv 0.0.9 A Free Gerber Viewer
2002-07-15 20:00:33 +00:00
SUBDIR += gerbv
Add gmsh 1.45.1, an automatic 3D finite element mesh generator. PR: 52201 Submitted by: Pedro Giffuni <giffunip@yahoo.com>
2003-07-23 14:21:51 +00:00
SUBDIR += gmsh
Adding Gmsh with support of OpenCascade.
2008-12-31 12:52:26 +00:00
SUBDIR += gmsh-occ
add gnucap 0.30 The Gnu Circuit Analysis Package
2002-02-07 07:07:48 +00:00
SUBDIR += gnucap
[NEW PORT] cad/gplcver: A Verilog HDL simulator GPL Cver is a full 1995 P1364 Verilog standard HDL simulator. It also implements some of the 2001 P1364 standard features including all three PLI interfaces (tf_, acc_ and vpi_) as defined in the 2001 Language Reference Manual (LRM). Verilog is the name for both a language for describing electronic hardware called a hardware description language (HDL) and the name of the program that simulates HDL circuit descriptions to verify that described circuits will function correctly when the are constructed. Verilog is used only for describing digital logic circuits. Other HDLs such as Spice are used for describing analog circuits. There is an IEEE standard named P1364 that standardizes the Verilog HDL and the behavior of Verilog simulators. Verilog is officially defined in the IEEE P1364 Language Reference Manual (LRM) that can be purchased from IEEE. There are many good books for learning that teach the Verilog HDL and/or that teach digital circuit design using Verilog. WWW: http://www.pragmatic-c.com/gpl-cver/ PR: ports/80968 Submitted by: Ying-Chieh Liao <ijliao@csie.nctu.edu.tw>
2005-12-29 03:48:58 +00:00
SUBDIR += gplcver
This port provides a GUI for two freely available SPICE electronic circuit simulation engines: GNU-Cap and Ng-Spice. Current features: Import gschem schematic files using gentlist. Load and parse circuit description (net list) files. Provides a GUI interface for GNU-Cap OP, DC, AC and Transient analyses and generates appropriate simulator commands based on user input. Provides a GUI interface for Ng-Spice DC, AC and Transient analyses and generates appropriate simulator commands based on user input. The raw output may be viewed for any processes initiated by gspiceui. Formatting of simulator output so that it may be plotted using gwave. WWW: http://www.geda.seul.org/tools/gspiceui/index.html PR: ports/99357 Submitted by: Stanislav Sedov <ssedov at mbsd.msk.ru>
2006-08-01 20:22:11 +00:00
SUBDIR += gspiceui
Update to latest version 3.3.39. Move to cad/gtkwave since we only have one version of this port, and the move will make maitenance easier. Approved by: kwm (mentor)
2012-09-04 08:46:18 +00:00
SUBDIR += gtkwave
add impact 0.5.3 Dynamic Finite Element Program Suite
2005-03-04 07:36:48 +00:00
SUBDIR += impact
Add chipmunk, convert to new format along the way.
1995-08-25 10:06:06 +00:00
SUBDIR += irsim
add iverilog, a Verilog simulation and synthesis tool
2001-02-13 11:02:15 +00:00
SUBDIR += iverilog
Jspice3 is a circuit simulator developed to meet the needs of researchers working with superconducting Josephson junction circuits, yet the program has the flexibility and power to meet the needs of other technologies. Jspice3 is an adaptation of the Berkeley Spice3f4 program, with added features. One added feature is a built-in graphical input front end for schematic capture. While displayed, simulations can be run and data plotted through this graphical interface. While not as powerful or as pretty as the Xic graphical interface, it holds its own in functionality. A significantly enhanced output plotting capability is provided, and Jspice3 has enhanced script interpretation capability. WWW: http://www.wrcad.com/jspice3.html PR: ports/93958 Submitted by: Pedro F. Giffuni Pedro can't maintain this port anymore and Stanislav Sedov agree to maintiant it.
2006-07-11 19:34:46 +00:00
SUBDIR += jspice3
Add Kicad, a software for the creation of electronic schematic diagrams and printed circuit board artwork. Kicad is a set of four softwares and a project manager: * Eeschema: Schematic entry. * Pcbnew: Board editor. * Gerbview: GERBER viewer (photoplotter documents). * Cvpcb: footprint selector for components used in the circuit design. * Kicad: project manager.
2005-12-08 23:30:13 +00:00
SUBDIR += kicad
Add kicad-devel to the build
2009-10-27 08:26:57 +00:00
SUBDIR += kicad-devel
Separate the libraries from the port cad/kicad.
2010-05-24 14:00:19 +00:00
SUBDIR += kicad-library
KLayout is a Qt-based GDS2 viewer.
2007-04-28 18:55:05 +00:00
SUBDIR += klayout
Add cad/layouteditor, an IC/MEMS layout editor with the following features: all angle, font generator, macros, boolean operations, design rule checker, crossplatform compatible. This supports Calma GDSII, OASIS (Open Artwork System Interchange Standard), DXF, CIF (Caltech Intermediate Form). WWW: http://www.layouteditor.net/index.html
2011-01-05 07:58:25 +00:00
SUBDIR += layouteditor
LDraw is an open standard for LEGO CAD programs that allow the user to create virtual LEGO models and scenes. You can use it to document models you have physically built, create building instructions just like LEGO, render 3D photo realistic images of your virtual models and even make animations. The possibilities are endless. Unlike real LEGO bricks where you are limited by the number of parts and colors, in LDraw nothing is impossible. WWW: http://www.ldraw.org/ PR: ports/174901 Submitted by: nemysis@gmx.ch
2013-03-13 21:39:40 +00:00
SUBDIR += ldraw
Add leocad 0.73, a CAD program that uses bricks similar to those found in many toys. PR: 35231 Submitted by: David Yeske <dyeske@yahoo.com>
2002-03-03 00:40:21 +00:00
SUBDIR += leocad
libgeda is a a base library common to all the gEDA tools Submitted by: bruno.schwander@technologist.com
2001-04-07 00:09:57 +00:00
SUBDIR += libgeda
Connect librecad
2012-01-04 09:06:40 +00:00
SUBDIR += librecad
Connect cad/linux-eagle5 to the build. Forgotten by: bsam (me) Requested by: linimon
2009-11-07 09:34:31 +00:00
SUBDIR += linux-eagle5
Logisim is an educational tool for designing and simulating digital logic circuits. With its simple toolbar interface and simulation of circuits as you build them, it is simple enough to facilitate learning the most basic concepts related to logic circuits. With the capacity to build larger circuits from smaller subcircuits, and to draw bundles of wires with a single mouse drag, Logisim can be used (and is used) to design and simulate entire CPUs for educational purposes. Logisim is used by students at colleges and universities around the world in many types of classes, ranging from a brief unit on logic in general-education computer science surveys, to computer organization courses, to full-semester courses on computer architecture. WWW: http://ozark.hendrix.edu/~burch/logisim/ PR: ports/176354 Submitted by: Javad Kouhi <javad.kouhi@gmail.com>
2013-03-02 13:26:40 +00:00
SUBDIR += logisim
Add chipmunk, convert to new format along the way.
1995-08-25 10:06:06 +00:00
SUBDIR += magic
- New port: cad/meshdev MeshDev is a mesh comparison software. It accepts two meshes as input and computes the geometrical deviation between the two meshes. It return numerical values and can optionaly generate visual results (with a pseudo-colored mesh corresponding to the measured deviation) in OpenInventor format. This port features a patch (by myself) to read binary and ASCII STL files. This feature was removed in the transition from version 0.4 -> 0.5. Distfiles are unfetchable from sourceforce. For this reason, they're hosted on our infrastructure. WWW: http://meshdev.sourceforge.net/
2012-02-06 15:57:20 +00:00
SUBDIR += meshdev
- New port: cad/meshlab MeshLab is an open source, portable, and extensible system for the processing and editing of unstructured 3D triangular meshes. WWW: http://meshlab.sourceforge.net/
2011-02-14 07:44:02 +00:00
SUBDIR += meshlab
Add netgen 4.3.1, an automatic 3D tetrahedral mesh generator.
2004-05-05 19:57:56 +00:00
SUBDIR += netgen
Initial import of ngspice_rework Ngspice_rework is a circuit simulator derived from spice3f5. PR: 34589 Submitted by: AMAKAWA Shuhei <amakawa@jp.FreeBSD.org>
2002-02-09 10:03:42 +00:00
SUBDIR += ngspice_rework
Open CASCADE Technology is a software development platform freely available in open source. It includes components for 3D surface and solid modeling, visualization, data exchange and rapid application development. Open CASCADE Technology can be best applied in development of numerical simulation software including CAD/CAM/CAE, AEC and GIS, as well as PDM applications. BUGS: the module WOK does not work, but the other modules (the most interesting parts) are OK.
2007-04-01 09:04:04 +00:00
SUBDIR += opencascade
Add openscad. OpenSCAD is a software for creating 3D CAD objects. Unlike most free software for creating 3D models, it does not focus on the artistic aspects of 3D modelling but instead on the CAD aspects. Thus it is more suitable for creating 3D models of machine parts but perhaps not when creating computer-animated movies. OpenSCAD is not an interactive modeller. Instead it is something like a 3D-compiler that reads in a script file that describes the object and renders the 3D model from this script file. This gives designers full control over the modelling process and enables them to easily change any step in the modelling process or make designes that are defined by configurable parameters. WWW: http://www.openscad.org/ Obtained from (slightly): OpenBSD
2011-08-19 11:02:10 +00:00
SUBDIR += openscad
NASA Open Source Parametric Geometry OpenVSP allows the user to create a 3D model of an aircraft defined by common engineering parameters. This model can be processed into formats suitable for engineering analysis. WWW: http://www.openvsp.org/ PR: ports/166825 Submitted by: Fernando Apesteguia <fernando.apesteguia@gmail.com>
2012-04-22 12:06:12 +00:00
SUBDIR += openvsp
p5-GDS2, a Perl module for quickly creating programs to read and/or write GDS2 files.
2007-04-29 07:17:29 +00:00
SUBDIR += p5-GDS2
The Verilog-Perl library is a building point for Verilog support in the Perl language. It includes: * Verilog::Getopt which parses command line options similar to C++ and VCS. * Verilog::Language which knows the language keywords and parses numbers. * Verilog::Netlist which builds netlists out of Verilog files. This allows easy scripts to determine things such as the hierarchy of modules. * Verilog::Parser invokes callbacks for language tokens. * Verilog::Preproc preprocesses the language, and allows reading post-processed files right from Perl without temporary files. * vpassert inserts PLIish warnings and assertions for any simulator. * vppreproc preprocesses the complete Verilog 2001 and SystemVerilog language. * vrename renames and cross-references Verilog symbols. Vrename creates Verilog cross references and makes it easy to rename signal and module names across multiple files. Vrename uses a simple and efficient three step process. First, you run vrename to create a list of signals in the design. You then edit this list, changing as many symbols as you wish. Vrename is then run a second time to apply the changes. WWW: http://www.veripool.org/wiki/verilog-perl PR: ports/134124 Submitted by: Otacílio de Araújo Ramos Neto <otacilio.neto at ee.ufcg.edu.br>
2009-05-26 11:01:39 +00:00
SUBDIR += p5-Verilog-Perl
Add chipmunk, convert to new format along the way.
1995-08-25 10:06:06 +00:00
SUBDIR += pcb
add pdnmesh A finite element program PR: 30115 Submitted by: Sarod Yatawatta <sarod@cs.pdn.ac.lk>
2001-10-14 17:54:31 +00:00
SUBDIR += pdnmesh
add pythoncad release 10 An open-source CAD package built designed around Python
2003-11-12 02:01:27 +00:00
SUBDIR += pythoncad
Readd qcad and upgrade to version 3.2.1 PR: ports/181199 Submitted by: Thierry Thomas (thierry@)
2013-08-21 07:52:35 +00:00
SUBDIR += qcad
- Keep category Makefiles sorted
2014-01-28 03:25:28 +00:00
SUBDIR += qcad-partslib
QElectroTech is a Qt4 application to design electric diagrams. It uses XML files for elements and diagrams, and includes both a diagram editor and an element editor. WWW: http://qelectrotech.org/ PR: ports/146513 Submitted by: Gvozdikov Veniamin <g.veniamin at googlemail.com> Approved by: pgj (mentor)
2010-07-21 09:57:57 +00:00
SUBDIR += qelectrotech
add qfsm 0.30 A graphical tool for designing finite state machines
2002-04-11 18:27:36 +00:00
SUBDIR += qfsm
add qmls Quine-McCluskey Logic Simplifier
2001-12-10 05:18:39 +00:00
SUBDIR += qmls
RepSnapper is a host software for controlling a RepRap 3D printer. It has a 3D OpenGL interface, slices objects and calculates the extrusion toolpath. It can manipulate 3D objects and save constellations in STL and AMF format. WWW: http://reprap.org/wiki/RepSnapper_Manual:Introduction PR: ports/171796 Submitted by: Martin Dieringer <martin.dieringe@gmx.de>
2012-09-28 22:32:18 +00:00
SUBDIR += repsnapper
SCEPTRE (System for Circuit Evaluation and Prediction of Transient Radiation Effects) is a general purpose circuit analysis program which provides all three major analyses, AC, DC, and transient analysis, on either linear or nonlinear networks. It employs a free-form input language and state variable methods to simulate problems of interest to electrical engineers. Requested-by: "Pedro F. Giffuni" <pfg1+@pitt.edu>
2001-02-11 06:58:11 +00:00
SUBDIR += sceptre
SCOTCH is a software package and libraries for graph, mesh and hypergraph partitioning, static mapping, and sparse matrix block ordering. Its purpose of Scotch is to apply graph theory, with a divide and conquer approach, to scientific computing problems such as graph and mesh partitioning, static mapping, and sparse matrix ordering, in application domains ranging from structural mechanics to operating systems or bio-chemistry. Note: there is an older tarball included in Aster's distfile, but I prefer a separate distfile from the official site.
2006-02-03 22:19:54 +00:00
SUBDIR += scotch
The SystemC Verification (SCV) library is an extension library to SystemC which adds advanced verification capabilities to SystemC, including constrained randomization, complex constraint solvers, data-structure creation, Transaction Level Modeling (TLM), concurrency, and dynamic resource allocation management. WWW: http://www.systemc.org/ PR: ports/106822 Submitted by: Peter Johnson
2006-12-22 09:09:38 +00:00
SUBDIR += scv
add slffea 1.25 San Le's Free Finite Element Analysis
2002-02-09 07:30:11 +00:00
SUBDIR += slffea
Sort entries. In particular, "large", "medium", "small" sort in this order, dispite their meanings. (Sometimes we're too smart for computers. :) Found by: sorting ports/INDEX by "sort -t '|' +1 -2" (Note: the whole "x11" category appears at the end with the above sort command, but I'll leave that the way it is for now -- "ls" shows it before other x11-* entries.)
1998-12-07 02:22:12 +00:00
SUBDIR += spice
Sweet Home 3D is a free interior design application that helps you place your furniture on a house 2D plan, with a 3D preview. WWW: http://www.sweethome3d.com PR: ports/171760 Submitted by: Matthias Petermann <matthias@petermann.it>
2013-03-21 20:16:53 +00:00
SUBDIR += sweethome3d
Add systemc 2.1.v1, a modeling platform for system-level C++ models. PR: ports/89987 Submitted by: Daniel Thiele
2005-12-18 11:23:43 +00:00
SUBDIR += systemc
Add new port cad/tochnog tochnog is a free finite element program with many features which is distributed under GPL. TOCHNOG accepts free format input. Boundary conditions can be imposed at geometrical entities, as well as nodes and elements. PR: 52088 Submitted by: Pedro F. Giffuni <giffunip@yahoo.com>
2003-07-13 05:29:48 +00:00
SUBDIR += tochnog
add transcalc 0.13 A analysis and synthesis tool for RF and microwave transmission lines
2002-09-06 09:40:18 +00:00
SUBDIR += transcalc
NEW port CAD/varkon A free CAD system and high level development tool for Engineering. It's a very interesting port for some branches of engineering. PR: ports/52202 Submitted by: Pedro F. Giffuni <giffunip@yahoo.com>
2003-05-20 23:03:37 +00:00
SUBDIR += varkon
- Add port for verilog-mode.el, Emacs Verilog editing mode. WWW: http://www.veripool.org/wiki/verilog-mode
2009-01-12 09:44:37 +00:00
SUBDIR += verilog-mode.el
Activate xcircuit.
1998-05-18 04:21:53 +00:00
SUBDIR += xcircuit
Add z88 11.0, a compact Finite Element Analysis System. PR: 75698 Submitted by: Pedro F. Giffuni.
2005-01-22 16:27:18 +00:00
SUBDIR += z88
New cad group
1995-01-13 11:10:43 +00:00
.include <bsd.port.subdir.mk>
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