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bc5bf9ebb7
freebsd-ports
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cad
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iverilog
History
Ying-Chieh Liao
7bf8e1d6ec
add iverilog, a Verilog simulation and synthesis tool
2001-02-13 11:02:15 +00:00
..
distinfo
add iverilog, a Verilog simulation and synthesis tool
2001-02-13 11:02:15 +00:00
Makefile
add iverilog, a Verilog simulation and synthesis tool
2001-02-13 11:02:15 +00:00
pkg-comment
add iverilog, a Verilog simulation and synthesis tool
2001-02-13 11:02:15 +00:00
pkg-descr
add iverilog, a Verilog simulation and synthesis tool
2001-02-13 11:02:15 +00:00
pkg-plist
add iverilog, a Verilog simulation and synthesis tool
2001-02-13 11:02:15 +00:00